16313Sgblack@eecs.umich.edu/* 214128Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2019 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146313Sgblack@eecs.umich.edu * Copyright (c) 2009 The Regents of The University of Michigan 156313Sgblack@eecs.umich.edu * All rights reserved. 166313Sgblack@eecs.umich.edu * 176313Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186313Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196313Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216313Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226313Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236313Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246313Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256313Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266313Sgblack@eecs.umich.edu * this software without specific prior written permission. 276313Sgblack@eecs.umich.edu * 286313Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296313Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306313Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316313Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326313Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336313Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346313Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356313Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366313Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376313Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386313Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396313Sgblack@eecs.umich.edu * 406313Sgblack@eecs.umich.edu * Authors: Gabe Black 416313Sgblack@eecs.umich.edu */ 426313Sgblack@eecs.umich.edu 436313Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_ISA_HH__ 447404SAli.Saidi@ARM.com#define __ARCH_ARM_ISA_HH__ 456313Sgblack@eecs.umich.edu 4610461SAndreas.Sandberg@ARM.com#include "arch/arm/isa_device.hh" 4712479SCurtis.Dunham@arm.com#include "arch/arm/miscregs.hh" 486333Sgblack@eecs.umich.edu#include "arch/arm/registers.hh" 4910037SARM gem5 Developers#include "arch/arm/system.hh" 507404SAli.Saidi@ARM.com#include "arch/arm/tlb.hh" 516313Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 5212109SRekai.GonzalezAlberquilla@arm.com#include "arch/generic/traits.hh" 538232Snate@binkert.org#include "debug/Checkpoint.hh" 5412109SRekai.GonzalezAlberquilla@arm.com#include "enums/VecRegRenameMode.hh" 559384SAndreas.Sandberg@arm.com#include "sim/sim_object.hh" 5611165SRekai.GonzalezAlberquilla@arm.com#include "enums/DecoderFlavour.hh" 576313Sgblack@eecs.umich.edu 589384SAndreas.Sandberg@arm.comstruct ArmISAParams; 5910461SAndreas.Sandberg@ARM.comstruct DummyArmISADeviceParams; 606333Sgblack@eecs.umich.educlass ThreadContext; 616313Sgblack@eecs.umich.educlass Checkpoint; 626313Sgblack@eecs.umich.educlass EventManager; 636313Sgblack@eecs.umich.edu 646313Sgblack@eecs.umich.edunamespace ArmISA 656313Sgblack@eecs.umich.edu{ 669384SAndreas.Sandberg@arm.com class ISA : public SimObject 676313Sgblack@eecs.umich.edu { 686313Sgblack@eecs.umich.edu protected: 6910037SARM gem5 Developers // Parent system 7010037SARM gem5 Developers ArmSystem *system; 7110037SARM gem5 Developers 7211165SRekai.GonzalezAlberquilla@arm.com // Micro Architecture 7311165SRekai.GonzalezAlberquilla@arm.com const Enums::DecoderFlavour _decoderFlavour; 7412109SRekai.GonzalezAlberquilla@arm.com const Enums::VecRegRenameMode _vecRegRenameMode; 7511165SRekai.GonzalezAlberquilla@arm.com 7610461SAndreas.Sandberg@ARM.com /** Dummy device for to handle non-existing ISA devices */ 7710461SAndreas.Sandberg@ARM.com DummyISADevice dummyDevice; 7810461SAndreas.Sandberg@ARM.com 7910461SAndreas.Sandberg@ARM.com // PMU belonging to this ISA 8010461SAndreas.Sandberg@ARM.com BaseISADevice *pmu; 8110461SAndreas.Sandberg@ARM.com 8210844Sandreas.sandberg@arm.com // Generic timer interface belonging to this ISA 8310844Sandreas.sandberg@arm.com std::unique_ptr<BaseISADevice> timer; 8410844Sandreas.sandberg@arm.com 8513531Sjairo.balart@metempsy.com // GICv3 CPU interface belonging to this ISA 8613531Sjairo.balart@metempsy.com std::unique_ptr<BaseISADevice> gicv3CpuInterface; 8713531Sjairo.balart@metempsy.com 8810037SARM gem5 Developers // Cached copies of system-level properties 8911771SCurtis.Dunham@arm.com bool highestELIs64; 9010037SARM gem5 Developers bool haveSecurity; 9110037SARM gem5 Developers bool haveLPAE; 9210037SARM gem5 Developers bool haveVirtualization; 9313173Sgiacomo.travaglini@arm.com bool haveCrypto; 9410037SARM gem5 Developers bool haveLargeAsid64; 9513531Sjairo.balart@metempsy.com bool haveGICv3CPUInterface; 9613114Sgiacomo.travaglini@arm.com uint8_t physAddrRange; 9713759Sgiacomo.gabrielli@arm.com bool haveSVE; 9814133Sjordi.vaquero@metempsy.com bool haveLSE; 9914128Sgiacomo.travaglini@arm.com bool havePAN; 10013759Sgiacomo.gabrielli@arm.com 10113759Sgiacomo.gabrielli@arm.com /** SVE vector length in quadwords */ 10213759Sgiacomo.gabrielli@arm.com unsigned sveVL; 10310037SARM gem5 Developers 10412714Sgiacomo.travaglini@arm.com /** 10512714Sgiacomo.travaglini@arm.com * If true, accesses to IMPLEMENTATION DEFINED registers are treated 10612714Sgiacomo.travaglini@arm.com * as NOP hence not causing UNDEFINED INSTRUCTION. 10712714Sgiacomo.travaglini@arm.com */ 10812714Sgiacomo.travaglini@arm.com bool impdefAsNop; 10912714Sgiacomo.travaglini@arm.com 11014000Sgiacomo.travaglini@arm.com bool afterStartup; 11114000Sgiacomo.travaglini@arm.com 11212478SCurtis.Dunham@arm.com /** MiscReg metadata **/ 11310037SARM gem5 Developers struct MiscRegLUTEntry { 11412477SCurtis.Dunham@arm.com uint32_t lower; // Lower half mapped to this register 11512477SCurtis.Dunham@arm.com uint32_t upper; // Upper half mapped to this register 11612478SCurtis.Dunham@arm.com uint64_t _reset; // value taken on reset (i.e. initialization) 11712478SCurtis.Dunham@arm.com uint64_t _res0; // reserved 11812478SCurtis.Dunham@arm.com uint64_t _res1; // reserved 11912478SCurtis.Dunham@arm.com uint64_t _raz; // read as zero (fixed at 0) 12012478SCurtis.Dunham@arm.com uint64_t _rao; // read as one (fixed at 1) 12112478SCurtis.Dunham@arm.com public: 12212478SCurtis.Dunham@arm.com MiscRegLUTEntry() : 12312478SCurtis.Dunham@arm.com lower(0), upper(0), 12412478SCurtis.Dunham@arm.com _reset(0), _res0(0), _res1(0), _raz(0), _rao(0) {} 12512478SCurtis.Dunham@arm.com uint64_t reset() const { return _reset; } 12612478SCurtis.Dunham@arm.com uint64_t res0() const { return _res0; } 12712478SCurtis.Dunham@arm.com uint64_t res1() const { return _res1; } 12812478SCurtis.Dunham@arm.com uint64_t raz() const { return _raz; } 12912478SCurtis.Dunham@arm.com uint64_t rao() const { return _rao; } 13012478SCurtis.Dunham@arm.com // raz/rao implies writes ignored 13112478SCurtis.Dunham@arm.com uint64_t wi() const { return _raz | _rao; } 13210037SARM gem5 Developers }; 13310037SARM gem5 Developers 13412477SCurtis.Dunham@arm.com /** Metadata table accessible via the value of the register */ 13512479SCurtis.Dunham@arm.com static std::vector<struct MiscRegLUTEntry> lookUpMiscReg; 13612477SCurtis.Dunham@arm.com 13712477SCurtis.Dunham@arm.com class MiscRegLUTEntryInitializer { 13812477SCurtis.Dunham@arm.com struct MiscRegLUTEntry &entry; 13912479SCurtis.Dunham@arm.com std::bitset<NUM_MISCREG_INFOS> &info; 14012477SCurtis.Dunham@arm.com typedef const MiscRegLUTEntryInitializer& chain; 14112477SCurtis.Dunham@arm.com public: 14212477SCurtis.Dunham@arm.com chain mapsTo(uint32_t l, uint32_t u = 0) const { 14312477SCurtis.Dunham@arm.com entry.lower = l; 14412477SCurtis.Dunham@arm.com entry.upper = u; 14512477SCurtis.Dunham@arm.com return *this; 14612477SCurtis.Dunham@arm.com } 14712478SCurtis.Dunham@arm.com chain res0(uint64_t mask) const { 14812478SCurtis.Dunham@arm.com entry._res0 = mask; 14912478SCurtis.Dunham@arm.com return *this; 15012478SCurtis.Dunham@arm.com } 15112478SCurtis.Dunham@arm.com chain res1(uint64_t mask) const { 15212478SCurtis.Dunham@arm.com entry._res1 = mask; 15312478SCurtis.Dunham@arm.com return *this; 15412478SCurtis.Dunham@arm.com } 15512478SCurtis.Dunham@arm.com chain raz(uint64_t mask) const { 15612478SCurtis.Dunham@arm.com entry._raz = mask; 15712478SCurtis.Dunham@arm.com return *this; 15812478SCurtis.Dunham@arm.com } 15912478SCurtis.Dunham@arm.com chain rao(uint64_t mask) const { 16012478SCurtis.Dunham@arm.com entry._rao = mask; 16112478SCurtis.Dunham@arm.com return *this; 16212478SCurtis.Dunham@arm.com } 16312479SCurtis.Dunham@arm.com chain implemented(bool v = true) const { 16412479SCurtis.Dunham@arm.com info[MISCREG_IMPLEMENTED] = v; 16512479SCurtis.Dunham@arm.com return *this; 16612479SCurtis.Dunham@arm.com } 16712479SCurtis.Dunham@arm.com chain unimplemented() const { 16812479SCurtis.Dunham@arm.com return implemented(false); 16912479SCurtis.Dunham@arm.com } 17012479SCurtis.Dunham@arm.com chain unverifiable(bool v = true) const { 17112479SCurtis.Dunham@arm.com info[MISCREG_UNVERIFIABLE] = v; 17212479SCurtis.Dunham@arm.com return *this; 17312479SCurtis.Dunham@arm.com } 17412479SCurtis.Dunham@arm.com chain warnNotFail(bool v = true) const { 17512479SCurtis.Dunham@arm.com info[MISCREG_WARN_NOT_FAIL] = v; 17612479SCurtis.Dunham@arm.com return *this; 17712479SCurtis.Dunham@arm.com } 17812479SCurtis.Dunham@arm.com chain mutex(bool v = true) const { 17912479SCurtis.Dunham@arm.com info[MISCREG_MUTEX] = v; 18012479SCurtis.Dunham@arm.com return *this; 18112479SCurtis.Dunham@arm.com } 18212479SCurtis.Dunham@arm.com chain banked(bool v = true) const { 18312479SCurtis.Dunham@arm.com info[MISCREG_BANKED] = v; 18412479SCurtis.Dunham@arm.com return *this; 18512479SCurtis.Dunham@arm.com } 18614242Sgiacomo.travaglini@arm.com chain banked64(bool v = true) const { 18714242Sgiacomo.travaglini@arm.com info[MISCREG_BANKED64] = v; 18814242Sgiacomo.travaglini@arm.com return *this; 18914242Sgiacomo.travaglini@arm.com } 19012479SCurtis.Dunham@arm.com chain bankedChild(bool v = true) const { 19112479SCurtis.Dunham@arm.com info[MISCREG_BANKED_CHILD] = v; 19212479SCurtis.Dunham@arm.com return *this; 19312479SCurtis.Dunham@arm.com } 19412479SCurtis.Dunham@arm.com chain userNonSecureRead(bool v = true) const { 19512479SCurtis.Dunham@arm.com info[MISCREG_USR_NS_RD] = v; 19612479SCurtis.Dunham@arm.com return *this; 19712479SCurtis.Dunham@arm.com } 19812479SCurtis.Dunham@arm.com chain userNonSecureWrite(bool v = true) const { 19912479SCurtis.Dunham@arm.com info[MISCREG_USR_NS_WR] = v; 20012479SCurtis.Dunham@arm.com return *this; 20112479SCurtis.Dunham@arm.com } 20212479SCurtis.Dunham@arm.com chain userSecureRead(bool v = true) const { 20312479SCurtis.Dunham@arm.com info[MISCREG_USR_S_RD] = v; 20412479SCurtis.Dunham@arm.com return *this; 20512479SCurtis.Dunham@arm.com } 20612479SCurtis.Dunham@arm.com chain userSecureWrite(bool v = true) const { 20712479SCurtis.Dunham@arm.com info[MISCREG_USR_S_WR] = v; 20812479SCurtis.Dunham@arm.com return *this; 20912479SCurtis.Dunham@arm.com } 21012479SCurtis.Dunham@arm.com chain user(bool v = true) const { 21112479SCurtis.Dunham@arm.com userNonSecureRead(v); 21212479SCurtis.Dunham@arm.com userNonSecureWrite(v); 21312479SCurtis.Dunham@arm.com userSecureRead(v); 21412479SCurtis.Dunham@arm.com userSecureWrite(v); 21512479SCurtis.Dunham@arm.com return *this; 21612479SCurtis.Dunham@arm.com } 21712479SCurtis.Dunham@arm.com chain privNonSecureRead(bool v = true) const { 21812479SCurtis.Dunham@arm.com info[MISCREG_PRI_NS_RD] = v; 21912479SCurtis.Dunham@arm.com return *this; 22012479SCurtis.Dunham@arm.com } 22112479SCurtis.Dunham@arm.com chain privNonSecureWrite(bool v = true) const { 22212479SCurtis.Dunham@arm.com info[MISCREG_PRI_NS_WR] = v; 22312479SCurtis.Dunham@arm.com return *this; 22412479SCurtis.Dunham@arm.com } 22512668Sgiacomo.travaglini@arm.com chain privNonSecure(bool v = true) const { 22612668Sgiacomo.travaglini@arm.com privNonSecureRead(v); 22712668Sgiacomo.travaglini@arm.com privNonSecureWrite(v); 22812668Sgiacomo.travaglini@arm.com return *this; 22912668Sgiacomo.travaglini@arm.com } 23012479SCurtis.Dunham@arm.com chain privSecureRead(bool v = true) const { 23112479SCurtis.Dunham@arm.com info[MISCREG_PRI_S_RD] = v; 23212479SCurtis.Dunham@arm.com return *this; 23312479SCurtis.Dunham@arm.com } 23412479SCurtis.Dunham@arm.com chain privSecureWrite(bool v = true) const { 23512479SCurtis.Dunham@arm.com info[MISCREG_PRI_S_WR] = v; 23612479SCurtis.Dunham@arm.com return *this; 23712479SCurtis.Dunham@arm.com } 23812479SCurtis.Dunham@arm.com chain privSecure(bool v = true) const { 23912479SCurtis.Dunham@arm.com privSecureRead(v); 24012479SCurtis.Dunham@arm.com privSecureWrite(v); 24112479SCurtis.Dunham@arm.com return *this; 24212479SCurtis.Dunham@arm.com } 24312668Sgiacomo.travaglini@arm.com chain priv(bool v = true) const { 24412668Sgiacomo.travaglini@arm.com privSecure(v); 24512668Sgiacomo.travaglini@arm.com privNonSecure(v); 24612668Sgiacomo.travaglini@arm.com return *this; 24712668Sgiacomo.travaglini@arm.com } 24813395Sgiacomo.travaglini@arm.com chain privRead(bool v = true) const { 24913395Sgiacomo.travaglini@arm.com privSecureRead(v); 25013395Sgiacomo.travaglini@arm.com privNonSecureRead(v); 25113395Sgiacomo.travaglini@arm.com return *this; 25213395Sgiacomo.travaglini@arm.com } 25312479SCurtis.Dunham@arm.com chain hypRead(bool v = true) const { 25412479SCurtis.Dunham@arm.com info[MISCREG_HYP_RD] = v; 25512479SCurtis.Dunham@arm.com return *this; 25612479SCurtis.Dunham@arm.com } 25712479SCurtis.Dunham@arm.com chain hypWrite(bool v = true) const { 25812479SCurtis.Dunham@arm.com info[MISCREG_HYP_WR] = v; 25912479SCurtis.Dunham@arm.com return *this; 26012479SCurtis.Dunham@arm.com } 26112479SCurtis.Dunham@arm.com chain hyp(bool v = true) const { 26212479SCurtis.Dunham@arm.com hypRead(v); 26312479SCurtis.Dunham@arm.com hypWrite(v); 26412479SCurtis.Dunham@arm.com return *this; 26512479SCurtis.Dunham@arm.com } 26612479SCurtis.Dunham@arm.com chain monSecureRead(bool v = true) const { 26712479SCurtis.Dunham@arm.com info[MISCREG_MON_NS0_RD] = v; 26812479SCurtis.Dunham@arm.com return *this; 26912479SCurtis.Dunham@arm.com } 27012479SCurtis.Dunham@arm.com chain monSecureWrite(bool v = true) const { 27112479SCurtis.Dunham@arm.com info[MISCREG_MON_NS0_WR] = v; 27212479SCurtis.Dunham@arm.com return *this; 27312479SCurtis.Dunham@arm.com } 27412479SCurtis.Dunham@arm.com chain monNonSecureRead(bool v = true) const { 27512479SCurtis.Dunham@arm.com info[MISCREG_MON_NS1_RD] = v; 27612479SCurtis.Dunham@arm.com return *this; 27712479SCurtis.Dunham@arm.com } 27812479SCurtis.Dunham@arm.com chain monNonSecureWrite(bool v = true) const { 27912479SCurtis.Dunham@arm.com info[MISCREG_MON_NS1_WR] = v; 28012479SCurtis.Dunham@arm.com return *this; 28112479SCurtis.Dunham@arm.com } 28212479SCurtis.Dunham@arm.com chain mon(bool v = true) const { 28312479SCurtis.Dunham@arm.com monSecureRead(v); 28412479SCurtis.Dunham@arm.com monSecureWrite(v); 28512479SCurtis.Dunham@arm.com monNonSecureRead(v); 28612479SCurtis.Dunham@arm.com monNonSecureWrite(v); 28712479SCurtis.Dunham@arm.com return *this; 28812479SCurtis.Dunham@arm.com } 28912479SCurtis.Dunham@arm.com chain monSecure(bool v = true) const { 29012479SCurtis.Dunham@arm.com monSecureRead(v); 29112479SCurtis.Dunham@arm.com monSecureWrite(v); 29212479SCurtis.Dunham@arm.com return *this; 29312479SCurtis.Dunham@arm.com } 29412479SCurtis.Dunham@arm.com chain monNonSecure(bool v = true) const { 29512479SCurtis.Dunham@arm.com monNonSecureRead(v); 29612479SCurtis.Dunham@arm.com monNonSecureWrite(v); 29712479SCurtis.Dunham@arm.com return *this; 29812479SCurtis.Dunham@arm.com } 29912479SCurtis.Dunham@arm.com chain allPrivileges(bool v = true) const { 30012479SCurtis.Dunham@arm.com userNonSecureRead(v); 30112479SCurtis.Dunham@arm.com userNonSecureWrite(v); 30212479SCurtis.Dunham@arm.com userSecureRead(v); 30312479SCurtis.Dunham@arm.com userSecureWrite(v); 30412479SCurtis.Dunham@arm.com privNonSecureRead(v); 30512479SCurtis.Dunham@arm.com privNonSecureWrite(v); 30612479SCurtis.Dunham@arm.com privSecureRead(v); 30712479SCurtis.Dunham@arm.com privSecureWrite(v); 30812479SCurtis.Dunham@arm.com hypRead(v); 30912479SCurtis.Dunham@arm.com hypWrite(v); 31012479SCurtis.Dunham@arm.com monSecureRead(v); 31112479SCurtis.Dunham@arm.com monSecureWrite(v); 31212479SCurtis.Dunham@arm.com monNonSecureRead(v); 31312479SCurtis.Dunham@arm.com monNonSecureWrite(v); 31412479SCurtis.Dunham@arm.com return *this; 31512479SCurtis.Dunham@arm.com } 31612479SCurtis.Dunham@arm.com chain nonSecure(bool v = true) const { 31712479SCurtis.Dunham@arm.com userNonSecureRead(v); 31812479SCurtis.Dunham@arm.com userNonSecureWrite(v); 31912479SCurtis.Dunham@arm.com privNonSecureRead(v); 32012479SCurtis.Dunham@arm.com privNonSecureWrite(v); 32112479SCurtis.Dunham@arm.com hypRead(v); 32212479SCurtis.Dunham@arm.com hypWrite(v); 32312479SCurtis.Dunham@arm.com monNonSecureRead(v); 32412479SCurtis.Dunham@arm.com monNonSecureWrite(v); 32512479SCurtis.Dunham@arm.com return *this; 32612479SCurtis.Dunham@arm.com } 32712479SCurtis.Dunham@arm.com chain secure(bool v = true) const { 32812479SCurtis.Dunham@arm.com userSecureRead(v); 32912479SCurtis.Dunham@arm.com userSecureWrite(v); 33012479SCurtis.Dunham@arm.com privSecureRead(v); 33112479SCurtis.Dunham@arm.com privSecureWrite(v); 33212479SCurtis.Dunham@arm.com monSecureRead(v); 33312479SCurtis.Dunham@arm.com monSecureWrite(v); 33412479SCurtis.Dunham@arm.com return *this; 33512479SCurtis.Dunham@arm.com } 33612479SCurtis.Dunham@arm.com chain reads(bool v) const { 33712479SCurtis.Dunham@arm.com userNonSecureRead(v); 33812479SCurtis.Dunham@arm.com userSecureRead(v); 33912479SCurtis.Dunham@arm.com privNonSecureRead(v); 34012479SCurtis.Dunham@arm.com privSecureRead(v); 34112479SCurtis.Dunham@arm.com hypRead(v); 34212479SCurtis.Dunham@arm.com monSecureRead(v); 34312479SCurtis.Dunham@arm.com monNonSecureRead(v); 34412479SCurtis.Dunham@arm.com return *this; 34512479SCurtis.Dunham@arm.com } 34612479SCurtis.Dunham@arm.com chain writes(bool v) const { 34712479SCurtis.Dunham@arm.com userNonSecureWrite(v); 34812479SCurtis.Dunham@arm.com userSecureWrite(v); 34912479SCurtis.Dunham@arm.com privNonSecureWrite(v); 35012479SCurtis.Dunham@arm.com privSecureWrite(v); 35112479SCurtis.Dunham@arm.com hypWrite(v); 35212479SCurtis.Dunham@arm.com monSecureWrite(v); 35312479SCurtis.Dunham@arm.com monNonSecureWrite(v); 35412479SCurtis.Dunham@arm.com return *this; 35512479SCurtis.Dunham@arm.com } 35612479SCurtis.Dunham@arm.com chain exceptUserMode() const { 35712479SCurtis.Dunham@arm.com user(0); 35812479SCurtis.Dunham@arm.com return *this; 35912479SCurtis.Dunham@arm.com } 36012479SCurtis.Dunham@arm.com MiscRegLUTEntryInitializer(struct MiscRegLUTEntry &e, 36112479SCurtis.Dunham@arm.com std::bitset<NUM_MISCREG_INFOS> &i) 36212479SCurtis.Dunham@arm.com : entry(e), 36312479SCurtis.Dunham@arm.com info(i) 36412479SCurtis.Dunham@arm.com { 36512479SCurtis.Dunham@arm.com // force unimplemented registers to be thusly declared 36612479SCurtis.Dunham@arm.com implemented(1); 36712479SCurtis.Dunham@arm.com } 36810037SARM gem5 Developers }; 36910037SARM gem5 Developers 37012477SCurtis.Dunham@arm.com const MiscRegLUTEntryInitializer InitReg(uint32_t reg) { 37112479SCurtis.Dunham@arm.com return MiscRegLUTEntryInitializer(lookUpMiscReg[reg], 37212479SCurtis.Dunham@arm.com miscRegInfo[reg]); 37312477SCurtis.Dunham@arm.com } 37410037SARM gem5 Developers 37512477SCurtis.Dunham@arm.com void initializeMiscRegMetadata(); 37610037SARM gem5 Developers 37713581Sgabeblack@google.com RegVal miscRegs[NumMiscRegs]; 3786718Sgblack@eecs.umich.edu const IntRegIndex *intRegMap; 3796718Sgblack@eecs.umich.edu 3806718Sgblack@eecs.umich.edu void 3816718Sgblack@eecs.umich.edu updateRegMap(CPSR cpsr) 3826718Sgblack@eecs.umich.edu { 38310037SARM gem5 Developers if (cpsr.width == 0) { 38410037SARM gem5 Developers intRegMap = IntReg64Map; 38510037SARM gem5 Developers } else { 38610037SARM gem5 Developers switch (cpsr.mode) { 38710037SARM gem5 Developers case MODE_USER: 38810037SARM gem5 Developers case MODE_SYSTEM: 38910037SARM gem5 Developers intRegMap = IntRegUsrMap; 39010037SARM gem5 Developers break; 39110037SARM gem5 Developers case MODE_FIQ: 39210037SARM gem5 Developers intRegMap = IntRegFiqMap; 39310037SARM gem5 Developers break; 39410037SARM gem5 Developers case MODE_IRQ: 39510037SARM gem5 Developers intRegMap = IntRegIrqMap; 39610037SARM gem5 Developers break; 39710037SARM gem5 Developers case MODE_SVC: 39810037SARM gem5 Developers intRegMap = IntRegSvcMap; 39910037SARM gem5 Developers break; 40010037SARM gem5 Developers case MODE_MON: 40110037SARM gem5 Developers intRegMap = IntRegMonMap; 40210037SARM gem5 Developers break; 40310037SARM gem5 Developers case MODE_ABORT: 40410037SARM gem5 Developers intRegMap = IntRegAbtMap; 40510037SARM gem5 Developers break; 40610037SARM gem5 Developers case MODE_HYP: 40710037SARM gem5 Developers intRegMap = IntRegHypMap; 40810037SARM gem5 Developers break; 40910037SARM gem5 Developers case MODE_UNDEFINED: 41010037SARM gem5 Developers intRegMap = IntRegUndMap; 41110037SARM gem5 Developers break; 41210037SARM gem5 Developers default: 41310037SARM gem5 Developers panic("Unrecognized mode setting in CPSR.\n"); 41410037SARM gem5 Developers } 4156718Sgblack@eecs.umich.edu } 4166718Sgblack@eecs.umich.edu } 4176313Sgblack@eecs.umich.edu 41810844Sandreas.sandberg@arm.com BaseISADevice &getGenericTimer(ThreadContext *tc); 41913531Sjairo.balart@metempsy.com BaseISADevice &getGICv3CPUInterface(ThreadContext *tc); 42010037SARM gem5 Developers 42110037SARM gem5 Developers 42210037SARM gem5 Developers private: 42310037SARM gem5 Developers inline void assert32(ThreadContext *tc) { 42410037SARM gem5 Developers CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 42510037SARM gem5 Developers assert(cpsr.width); 42610037SARM gem5 Developers } 42710037SARM gem5 Developers 42810037SARM gem5 Developers inline void assert64(ThreadContext *tc) { 42910037SARM gem5 Developers CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc); 43010037SARM gem5 Developers assert(!cpsr.width); 43110037SARM gem5 Developers } 43210037SARM gem5 Developers 4336313Sgblack@eecs.umich.edu public: 4347427Sgblack@eecs.umich.edu void clear(); 43513114Sgiacomo.travaglini@arm.com 43613114Sgiacomo.travaglini@arm.com protected: 43713393Sgiacomo.travaglini@arm.com void clear32(const ArmISAParams *p, const SCTLR &sctlr_rst); 43810037SARM gem5 Developers void clear64(const ArmISAParams *p); 43913114Sgiacomo.travaglini@arm.com void initID32(const ArmISAParams *p); 44013114Sgiacomo.travaglini@arm.com void initID64(const ArmISAParams *p); 4416313Sgblack@eecs.umich.edu 44213114Sgiacomo.travaglini@arm.com public: 44313581Sgabeblack@google.com RegVal readMiscRegNoEffect(int misc_reg) const; 44413581Sgabeblack@google.com RegVal readMiscReg(int misc_reg, ThreadContext *tc); 44513582Sgabeblack@google.com void setMiscRegNoEffect(int misc_reg, RegVal val); 44613582Sgabeblack@google.com void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc); 4476313Sgblack@eecs.umich.edu 44812106SRekai.GonzalezAlberquilla@arm.com RegId 44912106SRekai.GonzalezAlberquilla@arm.com flattenRegId(const RegId& regId) const 45012106SRekai.GonzalezAlberquilla@arm.com { 45112106SRekai.GonzalezAlberquilla@arm.com switch (regId.classValue()) { 45212106SRekai.GonzalezAlberquilla@arm.com case IntRegClass: 45312106SRekai.GonzalezAlberquilla@arm.com return RegId(IntRegClass, flattenIntIndex(regId.index())); 45412106SRekai.GonzalezAlberquilla@arm.com case FloatRegClass: 45512106SRekai.GonzalezAlberquilla@arm.com return RegId(FloatRegClass, flattenFloatIndex(regId.index())); 45612109SRekai.GonzalezAlberquilla@arm.com case VecRegClass: 45712109SRekai.GonzalezAlberquilla@arm.com return RegId(VecRegClass, flattenVecIndex(regId.index())); 45812109SRekai.GonzalezAlberquilla@arm.com case VecElemClass: 45913545Sgiacomo.travaglini@arm.com return RegId(VecElemClass, flattenVecElemIndex(regId.index()), 46013545Sgiacomo.travaglini@arm.com regId.elemIndex()); 46113610Sgiacomo.gabrielli@arm.com case VecPredRegClass: 46213610Sgiacomo.gabrielli@arm.com return RegId(VecPredRegClass, 46313610Sgiacomo.gabrielli@arm.com flattenVecPredIndex(regId.index())); 46412106SRekai.GonzalezAlberquilla@arm.com case CCRegClass: 46512106SRekai.GonzalezAlberquilla@arm.com return RegId(CCRegClass, flattenCCIndex(regId.index())); 46612106SRekai.GonzalezAlberquilla@arm.com case MiscRegClass: 46712106SRekai.GonzalezAlberquilla@arm.com return RegId(MiscRegClass, flattenMiscIndex(regId.index())); 46812106SRekai.GonzalezAlberquilla@arm.com } 46912106SRekai.GonzalezAlberquilla@arm.com return RegId(); 47012106SRekai.GonzalezAlberquilla@arm.com } 47112106SRekai.GonzalezAlberquilla@arm.com 4726313Sgblack@eecs.umich.edu int 47310035Sandreas.hansson@arm.com flattenIntIndex(int reg) const 4746313Sgblack@eecs.umich.edu { 4756718Sgblack@eecs.umich.edu assert(reg >= 0); 4766718Sgblack@eecs.umich.edu if (reg < NUM_ARCH_INTREGS) { 4776718Sgblack@eecs.umich.edu return intRegMap[reg]; 4786726Sgblack@eecs.umich.edu } else if (reg < NUM_INTREGS) { 4796726Sgblack@eecs.umich.edu return reg; 48010037SARM gem5 Developers } else if (reg == INTREG_SPX) { 48110037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 48210037SARM gem5 Developers ExceptionLevel el = opModeToEL( 48310037SARM gem5 Developers (OperatingMode) (uint8_t) cpsr.mode); 48410037SARM gem5 Developers if (!cpsr.sp && el != EL0) 48510037SARM gem5 Developers return INTREG_SP0; 48610037SARM gem5 Developers switch (el) { 48710037SARM gem5 Developers case EL3: 48810037SARM gem5 Developers return INTREG_SP3; 48911574SCurtis.Dunham@arm.com case EL2: 49011574SCurtis.Dunham@arm.com return INTREG_SP2; 49110037SARM gem5 Developers case EL1: 49210037SARM gem5 Developers return INTREG_SP1; 49310037SARM gem5 Developers case EL0: 49410037SARM gem5 Developers return INTREG_SP0; 49510037SARM gem5 Developers default: 49610037SARM gem5 Developers panic("Invalid exception level"); 49713020Sshunhsingou@google.com return 0; // Never happens. 49810037SARM gem5 Developers } 4996718Sgblack@eecs.umich.edu } else { 50010037SARM gem5 Developers return flattenIntRegModeIndex(reg); 5016718Sgblack@eecs.umich.edu } 5026313Sgblack@eecs.umich.edu } 5036313Sgblack@eecs.umich.edu 5046313Sgblack@eecs.umich.edu int 50510035Sandreas.hansson@arm.com flattenFloatIndex(int reg) const 5066313Sgblack@eecs.umich.edu { 50710338SCurtis.Dunham@arm.com assert(reg >= 0); 5086313Sgblack@eecs.umich.edu return reg; 5096313Sgblack@eecs.umich.edu } 5106313Sgblack@eecs.umich.edu 5119920Syasuko.eckert@amd.com int 51212109SRekai.GonzalezAlberquilla@arm.com flattenVecIndex(int reg) const 51312109SRekai.GonzalezAlberquilla@arm.com { 51412109SRekai.GonzalezAlberquilla@arm.com assert(reg >= 0); 51512109SRekai.GonzalezAlberquilla@arm.com return reg; 51612109SRekai.GonzalezAlberquilla@arm.com } 51712109SRekai.GonzalezAlberquilla@arm.com 51812109SRekai.GonzalezAlberquilla@arm.com int 51912109SRekai.GonzalezAlberquilla@arm.com flattenVecElemIndex(int reg) const 52012109SRekai.GonzalezAlberquilla@arm.com { 52112109SRekai.GonzalezAlberquilla@arm.com assert(reg >= 0); 52212109SRekai.GonzalezAlberquilla@arm.com return reg; 52312109SRekai.GonzalezAlberquilla@arm.com } 52412109SRekai.GonzalezAlberquilla@arm.com 52512109SRekai.GonzalezAlberquilla@arm.com int 52613610Sgiacomo.gabrielli@arm.com flattenVecPredIndex(int reg) const 52713610Sgiacomo.gabrielli@arm.com { 52813610Sgiacomo.gabrielli@arm.com assert(reg >= 0); 52913610Sgiacomo.gabrielli@arm.com return reg; 53013610Sgiacomo.gabrielli@arm.com } 53113610Sgiacomo.gabrielli@arm.com 53213610Sgiacomo.gabrielli@arm.com int 53310035Sandreas.hansson@arm.com flattenCCIndex(int reg) const 5349920Syasuko.eckert@amd.com { 53510338SCurtis.Dunham@arm.com assert(reg >= 0); 5369920Syasuko.eckert@amd.com return reg; 5379920Syasuko.eckert@amd.com } 5389920Syasuko.eckert@amd.com 5397614Sminkyu.jeong@arm.com int 54010035Sandreas.hansson@arm.com flattenMiscIndex(int reg) const 5417614Sminkyu.jeong@arm.com { 54210338SCurtis.Dunham@arm.com assert(reg >= 0); 54310037SARM gem5 Developers int flat_idx = reg; 54410037SARM gem5 Developers 5457614Sminkyu.jeong@arm.com if (reg == MISCREG_SPSR) { 5467614Sminkyu.jeong@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 5477614Sminkyu.jeong@arm.com switch (cpsr.mode) { 54810037SARM gem5 Developers case MODE_EL0T: 54910037SARM gem5 Developers warn("User mode does not have SPSR\n"); 55010037SARM gem5 Developers flat_idx = MISCREG_SPSR; 55110037SARM gem5 Developers break; 55210037SARM gem5 Developers case MODE_EL1T: 55310037SARM gem5 Developers case MODE_EL1H: 55410037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL1; 55510037SARM gem5 Developers break; 55610037SARM gem5 Developers case MODE_EL2T: 55710037SARM gem5 Developers case MODE_EL2H: 55810037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL2; 55910037SARM gem5 Developers break; 56010037SARM gem5 Developers case MODE_EL3T: 56110037SARM gem5 Developers case MODE_EL3H: 56210037SARM gem5 Developers flat_idx = MISCREG_SPSR_EL3; 56310037SARM gem5 Developers break; 5647614Sminkyu.jeong@arm.com case MODE_USER: 5657614Sminkyu.jeong@arm.com warn("User mode does not have SPSR\n"); 56610037SARM gem5 Developers flat_idx = MISCREG_SPSR; 5677614Sminkyu.jeong@arm.com break; 5687614Sminkyu.jeong@arm.com case MODE_FIQ: 56910037SARM gem5 Developers flat_idx = MISCREG_SPSR_FIQ; 5707614Sminkyu.jeong@arm.com break; 5717614Sminkyu.jeong@arm.com case MODE_IRQ: 57210037SARM gem5 Developers flat_idx = MISCREG_SPSR_IRQ; 5737614Sminkyu.jeong@arm.com break; 5747614Sminkyu.jeong@arm.com case MODE_SVC: 57510037SARM gem5 Developers flat_idx = MISCREG_SPSR_SVC; 5767614Sminkyu.jeong@arm.com break; 5777614Sminkyu.jeong@arm.com case MODE_MON: 57810037SARM gem5 Developers flat_idx = MISCREG_SPSR_MON; 5797614Sminkyu.jeong@arm.com break; 5807614Sminkyu.jeong@arm.com case MODE_ABORT: 58110037SARM gem5 Developers flat_idx = MISCREG_SPSR_ABT; 58210037SARM gem5 Developers break; 58310037SARM gem5 Developers case MODE_HYP: 58410037SARM gem5 Developers flat_idx = MISCREG_SPSR_HYP; 5857614Sminkyu.jeong@arm.com break; 5867614Sminkyu.jeong@arm.com case MODE_UNDEFINED: 58710037SARM gem5 Developers flat_idx = MISCREG_SPSR_UND; 5887614Sminkyu.jeong@arm.com break; 5897614Sminkyu.jeong@arm.com default: 5907614Sminkyu.jeong@arm.com warn("Trying to access SPSR in an invalid mode: %d\n", 5917614Sminkyu.jeong@arm.com cpsr.mode); 59210037SARM gem5 Developers flat_idx = MISCREG_SPSR; 5937614Sminkyu.jeong@arm.com break; 5947614Sminkyu.jeong@arm.com } 59510037SARM gem5 Developers } else if (miscRegInfo[reg][MISCREG_MUTEX]) { 59610037SARM gem5 Developers // Mutually exclusive CP15 register 59710037SARM gem5 Developers switch (reg) { 59810037SARM gem5 Developers case MISCREG_PRRR_MAIR0: 59910037SARM gem5 Developers case MISCREG_PRRR_MAIR0_NS: 60010037SARM gem5 Developers case MISCREG_PRRR_MAIR0_S: 60110037SARM gem5 Developers { 60210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 60310037SARM gem5 Developers // If the muxed reg has been flattened, work out the 60410037SARM gem5 Developers // offset and apply it to the unmuxed reg 60510037SARM gem5 Developers int idxOffset = reg - MISCREG_PRRR_MAIR0; 60610037SARM gem5 Developers if (ttbcr.eae) 60710037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_MAIR0 + 60810037SARM gem5 Developers idxOffset); 60910037SARM gem5 Developers else 61010037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PRRR + 61110037SARM gem5 Developers idxOffset); 61210037SARM gem5 Developers } 61310037SARM gem5 Developers break; 61410037SARM gem5 Developers case MISCREG_NMRR_MAIR1: 61510037SARM gem5 Developers case MISCREG_NMRR_MAIR1_NS: 61610037SARM gem5 Developers case MISCREG_NMRR_MAIR1_S: 61710037SARM gem5 Developers { 61810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 61910037SARM gem5 Developers // If the muxed reg has been flattened, work out the 62010037SARM gem5 Developers // offset and apply it to the unmuxed reg 62110037SARM gem5 Developers int idxOffset = reg - MISCREG_NMRR_MAIR1; 62210037SARM gem5 Developers if (ttbcr.eae) 62310037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_MAIR1 + 62410037SARM gem5 Developers idxOffset); 62510037SARM gem5 Developers else 62610037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_NMRR + 62710037SARM gem5 Developers idxOffset); 62810037SARM gem5 Developers } 62910037SARM gem5 Developers break; 63010037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 63110037SARM gem5 Developers { 63210037SARM gem5 Developers PMSELR pmselr = miscRegs[MISCREG_PMSELR]; 63310037SARM gem5 Developers if (pmselr.sel == 31) 63410037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PMCCFILTR); 63510037SARM gem5 Developers else 63610037SARM gem5 Developers flat_idx = flattenMiscIndex(MISCREG_PMXEVTYPER); 63710037SARM gem5 Developers } 63810037SARM gem5 Developers break; 63910037SARM gem5 Developers default: 64010037SARM gem5 Developers panic("Unrecognized misc. register.\n"); 64110037SARM gem5 Developers break; 64210037SARM gem5 Developers } 64310037SARM gem5 Developers } else { 64410037SARM gem5 Developers if (miscRegInfo[reg][MISCREG_BANKED]) { 64511771SCurtis.Dunham@arm.com bool secureReg = haveSecurity && !highestELIs64 && 64610037SARM gem5 Developers inSecureState(miscRegs[MISCREG_SCR], 64710037SARM gem5 Developers miscRegs[MISCREG_CPSR]); 64810037SARM gem5 Developers flat_idx += secureReg ? 2 : 1; 64914242Sgiacomo.travaglini@arm.com } else { 65014242Sgiacomo.travaglini@arm.com flat_idx = snsBankedIndex64((MiscRegIndex)reg, 65114242Sgiacomo.travaglini@arm.com !inSecureState(miscRegs[MISCREG_SCR], 65214242Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPSR])); 65310037SARM gem5 Developers } 6547614Sminkyu.jeong@arm.com } 65510037SARM gem5 Developers return flat_idx; 6567614Sminkyu.jeong@arm.com } 6577614Sminkyu.jeong@arm.com 65814242Sgiacomo.travaglini@arm.com int 65914242Sgiacomo.travaglini@arm.com snsBankedIndex64(MiscRegIndex reg, bool ns) const 66014242Sgiacomo.travaglini@arm.com { 66114242Sgiacomo.travaglini@arm.com int reg_as_int = static_cast<int>(reg); 66214242Sgiacomo.travaglini@arm.com if (miscRegInfo[reg][MISCREG_BANKED64]) { 66314242Sgiacomo.travaglini@arm.com reg_as_int += (haveSecurity && !ns) ? 2 : 1; 66414242Sgiacomo.travaglini@arm.com } 66514242Sgiacomo.travaglini@arm.com return reg_as_int; 66614242Sgiacomo.travaglini@arm.com } 66714242Sgiacomo.travaglini@arm.com 66811771SCurtis.Dunham@arm.com std::pair<int,int> getMiscIndices(int misc_reg) const 66911771SCurtis.Dunham@arm.com { 67011771SCurtis.Dunham@arm.com // Note: indexes of AArch64 registers are left unchanged 67111771SCurtis.Dunham@arm.com int flat_idx = flattenMiscIndex(misc_reg); 67211771SCurtis.Dunham@arm.com 67311771SCurtis.Dunham@arm.com if (lookUpMiscReg[flat_idx].lower == 0) { 67411771SCurtis.Dunham@arm.com return std::make_pair(flat_idx, 0); 67511771SCurtis.Dunham@arm.com } 67611771SCurtis.Dunham@arm.com 67711771SCurtis.Dunham@arm.com // do additional S/NS flattenings if mapped to NS while in S 67811771SCurtis.Dunham@arm.com bool S = haveSecurity && !highestELIs64 && 67911771SCurtis.Dunham@arm.com inSecureState(miscRegs[MISCREG_SCR], 68011771SCurtis.Dunham@arm.com miscRegs[MISCREG_CPSR]); 68111771SCurtis.Dunham@arm.com int lower = lookUpMiscReg[flat_idx].lower; 68211771SCurtis.Dunham@arm.com int upper = lookUpMiscReg[flat_idx].upper; 68311771SCurtis.Dunham@arm.com // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op) 68411771SCurtis.Dunham@arm.com lower += S && miscRegInfo[lower][MISCREG_BANKED_CHILD]; 68511771SCurtis.Dunham@arm.com upper += S && miscRegInfo[upper][MISCREG_BANKED_CHILD]; 68611771SCurtis.Dunham@arm.com return std::make_pair(lower, upper); 68711771SCurtis.Dunham@arm.com } 68811771SCurtis.Dunham@arm.com 68913759Sgiacomo.gabrielli@arm.com unsigned getCurSveVecLenInBits(ThreadContext *tc) const; 69013759Sgiacomo.gabrielli@arm.com 69113759Sgiacomo.gabrielli@arm.com unsigned getCurSveVecLenInBitsAtReset() const { return sveVL * 128; } 69213759Sgiacomo.gabrielli@arm.com 69313759Sgiacomo.gabrielli@arm.com static void zeroSveVecRegUpperPart(VecRegContainer &vc, 69413759Sgiacomo.gabrielli@arm.com unsigned eCount); 69513759Sgiacomo.gabrielli@arm.com 69610905Sandreas.sandberg@arm.com void serialize(CheckpointOut &cp) const 6977733SAli.Saidi@ARM.com { 6987733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n"); 69912529Sgiacomo.travaglini@arm.com SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); 70010037SARM gem5 Developers 70111771SCurtis.Dunham@arm.com SERIALIZE_SCALAR(highestELIs64); 70210037SARM gem5 Developers SERIALIZE_SCALAR(haveSecurity); 70310037SARM gem5 Developers SERIALIZE_SCALAR(haveLPAE); 70410037SARM gem5 Developers SERIALIZE_SCALAR(haveVirtualization); 70510037SARM gem5 Developers SERIALIZE_SCALAR(haveLargeAsid64); 70613114Sgiacomo.travaglini@arm.com SERIALIZE_SCALAR(physAddrRange); 70713759Sgiacomo.gabrielli@arm.com SERIALIZE_SCALAR(haveSVE); 70813759Sgiacomo.gabrielli@arm.com SERIALIZE_SCALAR(sveVL); 70914133Sjordi.vaquero@metempsy.com SERIALIZE_SCALAR(haveLSE); 71014128Sgiacomo.travaglini@arm.com SERIALIZE_SCALAR(havePAN); 7117733SAli.Saidi@ARM.com } 71210905Sandreas.sandberg@arm.com void unserialize(CheckpointIn &cp) 7137733SAli.Saidi@ARM.com { 7147733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n"); 71512529Sgiacomo.travaglini@arm.com UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS); 7167733SAli.Saidi@ARM.com CPSR tmp_cpsr = miscRegs[MISCREG_CPSR]; 7177733SAli.Saidi@ARM.com updateRegMap(tmp_cpsr); 71810037SARM gem5 Developers 71911771SCurtis.Dunham@arm.com UNSERIALIZE_SCALAR(highestELIs64); 72010037SARM gem5 Developers UNSERIALIZE_SCALAR(haveSecurity); 72110037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLPAE); 72210037SARM gem5 Developers UNSERIALIZE_SCALAR(haveVirtualization); 72310037SARM gem5 Developers UNSERIALIZE_SCALAR(haveLargeAsid64); 72413114Sgiacomo.travaglini@arm.com UNSERIALIZE_SCALAR(physAddrRange); 72513759Sgiacomo.gabrielli@arm.com UNSERIALIZE_SCALAR(haveSVE); 72613759Sgiacomo.gabrielli@arm.com UNSERIALIZE_SCALAR(sveVL); 72714133Sjordi.vaquero@metempsy.com UNSERIALIZE_SCALAR(haveLSE); 72814128Sgiacomo.travaglini@arm.com UNSERIALIZE_SCALAR(havePAN); 7297733SAli.Saidi@ARM.com } 7306313Sgblack@eecs.umich.edu 73112972Sandreas.sandberg@arm.com void startup(ThreadContext *tc); 7329461Snilay@cs.wisc.edu 73311165SRekai.GonzalezAlberquilla@arm.com Enums::DecoderFlavour decoderFlavour() const { return _decoderFlavour; } 73411165SRekai.GonzalezAlberquilla@arm.com 73514000Sgiacomo.travaglini@arm.com /** Getter for haveGICv3CPUInterface */ 73614000Sgiacomo.travaglini@arm.com bool haveGICv3CpuIfc() const 73714000Sgiacomo.travaglini@arm.com { 73814000Sgiacomo.travaglini@arm.com // haveGICv3CPUInterface is initialized at startup time, hence 73914000Sgiacomo.travaglini@arm.com // trying to read its value before the startup stage will lead 74014000Sgiacomo.travaglini@arm.com // to an error 74114000Sgiacomo.travaglini@arm.com assert(afterStartup); 74214000Sgiacomo.travaglini@arm.com return haveGICv3CPUInterface; 74314000Sgiacomo.travaglini@arm.com } 74414000Sgiacomo.travaglini@arm.com 74512109SRekai.GonzalezAlberquilla@arm.com Enums::VecRegRenameMode 74612109SRekai.GonzalezAlberquilla@arm.com vecRegRenameMode() const 74712109SRekai.GonzalezAlberquilla@arm.com { 74812109SRekai.GonzalezAlberquilla@arm.com return _vecRegRenameMode; 74912109SRekai.GonzalezAlberquilla@arm.com } 75012109SRekai.GonzalezAlberquilla@arm.com 7519553Sandreas.hansson@arm.com /// Explicitly import the otherwise hidden startup 7529553Sandreas.hansson@arm.com using SimObject::startup; 7539553Sandreas.hansson@arm.com 7549384SAndreas.Sandberg@arm.com typedef ArmISAParams Params; 7557400SAli.Saidi@ARM.com 7569384SAndreas.Sandberg@arm.com const Params *params() const; 7579384SAndreas.Sandberg@arm.com 7589384SAndreas.Sandberg@arm.com ISA(Params *p); 7596313Sgblack@eecs.umich.edu }; 7606313Sgblack@eecs.umich.edu} 7616313Sgblack@eecs.umich.edu 76212109SRekai.GonzalezAlberquilla@arm.comtemplate<> 76313601Sgiacomo.travaglini@arm.comstruct RenameMode<ArmISA::ISA> 76412109SRekai.GonzalezAlberquilla@arm.com{ 76513601Sgiacomo.travaglini@arm.com static Enums::VecRegRenameMode 76613601Sgiacomo.travaglini@arm.com init(const ArmISA::ISA* isa) 76712109SRekai.GonzalezAlberquilla@arm.com { 76812109SRekai.GonzalezAlberquilla@arm.com return isa->vecRegRenameMode(); 76912109SRekai.GonzalezAlberquilla@arm.com } 77013601Sgiacomo.travaglini@arm.com 77113601Sgiacomo.travaglini@arm.com static Enums::VecRegRenameMode 77213601Sgiacomo.travaglini@arm.com mode(const ArmISA::PCState& pc) 77312109SRekai.GonzalezAlberquilla@arm.com { 77413601Sgiacomo.travaglini@arm.com if (pc.aarch64()) { 77513601Sgiacomo.travaglini@arm.com return Enums::Full; 77613601Sgiacomo.travaglini@arm.com } else { 77713601Sgiacomo.travaglini@arm.com return Enums::Elem; 77813601Sgiacomo.travaglini@arm.com } 77913601Sgiacomo.travaglini@arm.com } 78013601Sgiacomo.travaglini@arm.com 78113601Sgiacomo.travaglini@arm.com static bool 78213601Sgiacomo.travaglini@arm.com equalsInit(const ArmISA::ISA* isa1, const ArmISA::ISA* isa2) 78313601Sgiacomo.travaglini@arm.com { 78413601Sgiacomo.travaglini@arm.com return init(isa1) == init(isa2); 78512109SRekai.GonzalezAlberquilla@arm.com } 78612109SRekai.GonzalezAlberquilla@arm.com}; 78712109SRekai.GonzalezAlberquilla@arm.com 7886313Sgblack@eecs.umich.edu#endif 789