110037SARM gem5 Developers/* 214001Sgiacomo.travaglini@arm.com * Copyright (c) 2011-2013,2017-2019 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Gabe Black 3814127Sgiacomo.travaglini@arm.com * Giacomo Travaglini 3910037SARM gem5 Developers */ 4010037SARM gem5 Developers 4110037SARM gem5 Developers#include "arch/arm/insts/misc64.hh" 4214001Sgiacomo.travaglini@arm.com#include "arch/arm/isa.hh" 4310037SARM gem5 Developers 4410037SARM gem5 Developersstd::string 4512538Sgiacomo.travaglini@arm.comImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 4612538Sgiacomo.travaglini@arm.com{ 4712538Sgiacomo.travaglini@arm.com std::stringstream ss; 4812538Sgiacomo.travaglini@arm.com printMnemonic(ss, "", false); 4912538Sgiacomo.travaglini@arm.com ccprintf(ss, "#0x%x", imm); 5012538Sgiacomo.travaglini@arm.com return ss.str(); 5112538Sgiacomo.travaglini@arm.com} 5212538Sgiacomo.travaglini@arm.com 5312538Sgiacomo.travaglini@arm.comstd::string 5410037SARM gem5 DevelopersRegRegImmImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 5510037SARM gem5 Developers{ 5610037SARM gem5 Developers std::stringstream ss; 5710037SARM gem5 Developers printMnemonic(ss, "", false); 5812104Snathanael.premillieu@arm.com printIntReg(ss, dest); 5910037SARM gem5 Developers ss << ", "; 6012104Snathanael.premillieu@arm.com printIntReg(ss, op1); 6110037SARM gem5 Developers ccprintf(ss, ", #%d, #%d", imm1, imm2); 6210037SARM gem5 Developers return ss.str(); 6310037SARM gem5 Developers} 6410037SARM gem5 Developers 6510037SARM gem5 Developersstd::string 6610037SARM gem5 DevelopersRegRegRegImmOp64::generateDisassembly( 6712280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 6810037SARM gem5 Developers{ 6910037SARM gem5 Developers std::stringstream ss; 7010037SARM gem5 Developers printMnemonic(ss, "", false); 7112104Snathanael.premillieu@arm.com printIntReg(ss, dest); 7210037SARM gem5 Developers ss << ", "; 7312104Snathanael.premillieu@arm.com printIntReg(ss, op1); 7410037SARM gem5 Developers ss << ", "; 7512104Snathanael.premillieu@arm.com printIntReg(ss, op2); 7610037SARM gem5 Developers ccprintf(ss, ", #%d", imm); 7710037SARM gem5 Developers return ss.str(); 7810037SARM gem5 Developers} 7910037SARM gem5 Developers 8010037SARM gem5 Developersstd::string 8110037SARM gem5 DevelopersUnknownOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8210037SARM gem5 Developers{ 8313895Sgiacomo.travaglini@arm.com return csprintf("%-10s (inst %#08x)", "unknown", encoding()); 8410037SARM gem5 Developers} 8512280Sgiacomo.travaglini@arm.com 8613364Sgiacomo.travaglini@arm.comFault 8713364Sgiacomo.travaglini@arm.comMiscRegOp64::trap(ThreadContext *tc, MiscRegIndex misc_reg, 8813364Sgiacomo.travaglini@arm.com ExceptionLevel el, uint32_t immediate) const 8913364Sgiacomo.travaglini@arm.com{ 9013364Sgiacomo.travaglini@arm.com bool is_vfp_neon = false; 9113364Sgiacomo.travaglini@arm.com 9213364Sgiacomo.travaglini@arm.com // Check for traps to supervisor (FP/SIMD regs) 9313364Sgiacomo.travaglini@arm.com if (el <= EL1 && checkEL1Trap(tc, misc_reg, el)) { 9413364Sgiacomo.travaglini@arm.com 9513364Sgiacomo.travaglini@arm.com return std::make_shared<SupervisorTrap>(machInst, 0x1E00000, 9613364Sgiacomo.travaglini@arm.com EC_TRAPPED_SIMD_FP); 9713364Sgiacomo.travaglini@arm.com } 9813364Sgiacomo.travaglini@arm.com 9913364Sgiacomo.travaglini@arm.com // Check for traps to hypervisor 10013364Sgiacomo.travaglini@arm.com if ((ArmSystem::haveVirtualization(tc) && el <= EL2) && 10113364Sgiacomo.travaglini@arm.com checkEL2Trap(tc, misc_reg, el, &is_vfp_neon)) { 10213364Sgiacomo.travaglini@arm.com 10313364Sgiacomo.travaglini@arm.com return std::make_shared<HypervisorTrap>( 10413364Sgiacomo.travaglini@arm.com machInst, is_vfp_neon ? 0x1E00000 : immediate, 10513364Sgiacomo.travaglini@arm.com is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); 10613364Sgiacomo.travaglini@arm.com } 10713364Sgiacomo.travaglini@arm.com 10813364Sgiacomo.travaglini@arm.com // Check for traps to secure monitor 10913364Sgiacomo.travaglini@arm.com if ((ArmSystem::haveSecurity(tc) && el <= EL3) && 11013364Sgiacomo.travaglini@arm.com checkEL3Trap(tc, misc_reg, el, &is_vfp_neon)) { 11113364Sgiacomo.travaglini@arm.com 11213364Sgiacomo.travaglini@arm.com return std::make_shared<SecureMonitorTrap>( 11313364Sgiacomo.travaglini@arm.com machInst, 11413364Sgiacomo.travaglini@arm.com is_vfp_neon ? 0x1E00000 : immediate, 11513364Sgiacomo.travaglini@arm.com is_vfp_neon ? EC_TRAPPED_SIMD_FP : EC_TRAPPED_MSR_MRS_64); 11613364Sgiacomo.travaglini@arm.com } 11713364Sgiacomo.travaglini@arm.com 11813364Sgiacomo.travaglini@arm.com return NoFault; 11913364Sgiacomo.travaglini@arm.com} 12013364Sgiacomo.travaglini@arm.com 12113364Sgiacomo.travaglini@arm.combool 12213364Sgiacomo.travaglini@arm.comMiscRegOp64::checkEL1Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 12313364Sgiacomo.travaglini@arm.com ExceptionLevel el) const 12413364Sgiacomo.travaglini@arm.com{ 12513364Sgiacomo.travaglini@arm.com const CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1); 12613364Sgiacomo.travaglini@arm.com 12713364Sgiacomo.travaglini@arm.com bool trap_to_sup = false; 12813364Sgiacomo.travaglini@arm.com switch (misc_reg) { 12913364Sgiacomo.travaglini@arm.com case MISCREG_FPCR: 13013364Sgiacomo.travaglini@arm.com case MISCREG_FPSR: 13113364Sgiacomo.travaglini@arm.com case MISCREG_FPEXC32_EL2: 13213364Sgiacomo.travaglini@arm.com if ((el == EL0 && cpacr.fpen != 0x3) || 13313364Sgiacomo.travaglini@arm.com (el == EL1 && !(cpacr.fpen & 0x1))) 13413364Sgiacomo.travaglini@arm.com trap_to_sup = true; 13513364Sgiacomo.travaglini@arm.com break; 13613364Sgiacomo.travaglini@arm.com default: 13713364Sgiacomo.travaglini@arm.com break; 13813364Sgiacomo.travaglini@arm.com } 13913364Sgiacomo.travaglini@arm.com return trap_to_sup; 14013364Sgiacomo.travaglini@arm.com} 14113364Sgiacomo.travaglini@arm.com 14213364Sgiacomo.travaglini@arm.combool 14313364Sgiacomo.travaglini@arm.comMiscRegOp64::checkEL2Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 14413364Sgiacomo.travaglini@arm.com ExceptionLevel el, bool * is_vfp_neon) const 14513364Sgiacomo.travaglini@arm.com{ 14613364Sgiacomo.travaglini@arm.com const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL2); 14713364Sgiacomo.travaglini@arm.com const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2); 14813364Sgiacomo.travaglini@arm.com const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); 14913364Sgiacomo.travaglini@arm.com const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 15013364Sgiacomo.travaglini@arm.com 15113364Sgiacomo.travaglini@arm.com bool trap_to_hyp = false; 15213364Sgiacomo.travaglini@arm.com *is_vfp_neon = false; 15313364Sgiacomo.travaglini@arm.com 15413364Sgiacomo.travaglini@arm.com if (!inSecureState(scr, cpsr) && (el != EL2)) { 15513364Sgiacomo.travaglini@arm.com switch (misc_reg) { 15613364Sgiacomo.travaglini@arm.com // FP/SIMD regs 15713364Sgiacomo.travaglini@arm.com case MISCREG_FPCR: 15813364Sgiacomo.travaglini@arm.com case MISCREG_FPSR: 15913364Sgiacomo.travaglini@arm.com case MISCREG_FPEXC32_EL2: 16013364Sgiacomo.travaglini@arm.com trap_to_hyp = cptr.tfp; 16113364Sgiacomo.travaglini@arm.com *is_vfp_neon = true; 16213364Sgiacomo.travaglini@arm.com break; 16313364Sgiacomo.travaglini@arm.com // CPACR 16413364Sgiacomo.travaglini@arm.com case MISCREG_CPACR_EL1: 16513364Sgiacomo.travaglini@arm.com trap_to_hyp = cptr.tcpac && el == EL1; 16613364Sgiacomo.travaglini@arm.com break; 16713364Sgiacomo.travaglini@arm.com // Virtual memory control regs 16813364Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL1: 16913364Sgiacomo.travaglini@arm.com case MISCREG_TTBR0_EL1: 17013364Sgiacomo.travaglini@arm.com case MISCREG_TTBR1_EL1: 17113364Sgiacomo.travaglini@arm.com case MISCREG_TCR_EL1: 17213364Sgiacomo.travaglini@arm.com case MISCREG_ESR_EL1: 17313364Sgiacomo.travaglini@arm.com case MISCREG_FAR_EL1: 17413364Sgiacomo.travaglini@arm.com case MISCREG_AFSR0_EL1: 17513364Sgiacomo.travaglini@arm.com case MISCREG_AFSR1_EL1: 17613364Sgiacomo.travaglini@arm.com case MISCREG_MAIR_EL1: 17713364Sgiacomo.travaglini@arm.com case MISCREG_AMAIR_EL1: 17813364Sgiacomo.travaglini@arm.com case MISCREG_CONTEXTIDR_EL1: 17913364Sgiacomo.travaglini@arm.com trap_to_hyp = 18013364Sgiacomo.travaglini@arm.com ((hcr.trvm && miscRead) || (hcr.tvm && !miscRead)) && 18113364Sgiacomo.travaglini@arm.com el == EL1; 18213364Sgiacomo.travaglini@arm.com break; 18313364Sgiacomo.travaglini@arm.com // TLB maintenance instructions 18413364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1: 18513364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 18613364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 18713364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 18813364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1_Xt: 18913364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1_Xt: 19013364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 19113364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1IS_Xt: 19213364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1IS_Xt: 19313364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1IS_Xt: 19413364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1IS_Xt: 19513364Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1IS_Xt: 19613364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.ttlb && el == EL1; 19713364Sgiacomo.travaglini@arm.com break; 19813364Sgiacomo.travaglini@arm.com // Cache maintenance instructions to the point of unification 19913364Sgiacomo.travaglini@arm.com case MISCREG_IC_IVAU_Xt: 20013364Sgiacomo.travaglini@arm.com case MISCREG_ICIALLU: 20113364Sgiacomo.travaglini@arm.com case MISCREG_ICIALLUIS: 20213364Sgiacomo.travaglini@arm.com case MISCREG_DC_CVAU_Xt: 20313364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tpu && el <= EL1; 20413364Sgiacomo.travaglini@arm.com break; 20513364Sgiacomo.travaglini@arm.com // Data/Unified cache maintenance instructions to the 20613364Sgiacomo.travaglini@arm.com // point of coherency 20713364Sgiacomo.travaglini@arm.com case MISCREG_DC_IVAC_Xt: 20813364Sgiacomo.travaglini@arm.com case MISCREG_DC_CIVAC_Xt: 20913364Sgiacomo.travaglini@arm.com case MISCREG_DC_CVAC_Xt: 21013364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tpc && el <= EL1; 21113364Sgiacomo.travaglini@arm.com break; 21213364Sgiacomo.travaglini@arm.com // Data/Unified cache maintenance instructions by set/way 21313364Sgiacomo.travaglini@arm.com case MISCREG_DC_ISW_Xt: 21413364Sgiacomo.travaglini@arm.com case MISCREG_DC_CSW_Xt: 21513364Sgiacomo.travaglini@arm.com case MISCREG_DC_CISW_Xt: 21613364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tsw && el == EL1; 21713364Sgiacomo.travaglini@arm.com break; 21813364Sgiacomo.travaglini@arm.com // ACTLR 21913364Sgiacomo.travaglini@arm.com case MISCREG_ACTLR_EL1: 22013364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tacr && el == EL1; 22113364Sgiacomo.travaglini@arm.com break; 22213364Sgiacomo.travaglini@arm.com 22313364Sgiacomo.travaglini@arm.com // @todo: Trap implementation-dependent functionality based on 22413364Sgiacomo.travaglini@arm.com // hcr.tidcp 22513364Sgiacomo.travaglini@arm.com 22613364Sgiacomo.travaglini@arm.com // ID regs, group 3 22713364Sgiacomo.travaglini@arm.com case MISCREG_ID_PFR0_EL1: 22813364Sgiacomo.travaglini@arm.com case MISCREG_ID_PFR1_EL1: 22913364Sgiacomo.travaglini@arm.com case MISCREG_ID_DFR0_EL1: 23013364Sgiacomo.travaglini@arm.com case MISCREG_ID_AFR0_EL1: 23113364Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR0_EL1: 23213364Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR1_EL1: 23313364Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR2_EL1: 23413364Sgiacomo.travaglini@arm.com case MISCREG_ID_MMFR3_EL1: 23513364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR0_EL1: 23613364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR1_EL1: 23713364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR2_EL1: 23813364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR3_EL1: 23913364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR4_EL1: 24013364Sgiacomo.travaglini@arm.com case MISCREG_ID_ISAR5_EL1: 24113364Sgiacomo.travaglini@arm.com case MISCREG_MVFR0_EL1: 24213364Sgiacomo.travaglini@arm.com case MISCREG_MVFR1_EL1: 24313364Sgiacomo.travaglini@arm.com case MISCREG_MVFR2_EL1: 24413364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64PFR0_EL1: 24513364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64PFR1_EL1: 24613364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64DFR0_EL1: 24713364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64DFR1_EL1: 24813364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64ISAR0_EL1: 24913364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64ISAR1_EL1: 25013364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR0_EL1: 25113364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR1_EL1: 25213364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR2_EL1: 25313364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64AFR0_EL1: 25413364Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64AFR1_EL1: 25513364Sgiacomo.travaglini@arm.com assert(miscRead); 25613364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tid3 && el == EL1; 25713364Sgiacomo.travaglini@arm.com break; 25813364Sgiacomo.travaglini@arm.com // ID regs, group 2 25913364Sgiacomo.travaglini@arm.com case MISCREG_CTR_EL0: 26013364Sgiacomo.travaglini@arm.com case MISCREG_CCSIDR_EL1: 26113364Sgiacomo.travaglini@arm.com case MISCREG_CLIDR_EL1: 26213364Sgiacomo.travaglini@arm.com case MISCREG_CSSELR_EL1: 26313364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tid2 && el <= EL1; 26413364Sgiacomo.travaglini@arm.com break; 26513364Sgiacomo.travaglini@arm.com // ID regs, group 1 26613364Sgiacomo.travaglini@arm.com case MISCREG_AIDR_EL1: 26713364Sgiacomo.travaglini@arm.com case MISCREG_REVIDR_EL1: 26813364Sgiacomo.travaglini@arm.com assert(miscRead); 26913364Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tid1 && el == EL1; 27013364Sgiacomo.travaglini@arm.com break; 27113365Sgiacomo.travaglini@arm.com case MISCREG_IMPDEF_UNIMPL: 27213365Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.tidcp && el == EL1; 27314002Sgiacomo.travaglini@arm.com break; 27414001Sgiacomo.travaglini@arm.com // GICv3 regs 27514001Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI0R_EL1: 27614001Sgiacomo.travaglini@arm.com if (tc->getIsaPtr()->haveGICv3CpuIfc()) 27714001Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.fmo && el == EL1; 27814001Sgiacomo.travaglini@arm.com break; 27914001Sgiacomo.travaglini@arm.com case MISCREG_ICC_SGI1R_EL1: 28014001Sgiacomo.travaglini@arm.com case MISCREG_ICC_ASGI1R_EL1: 28114001Sgiacomo.travaglini@arm.com if (tc->getIsaPtr()->haveGICv3CpuIfc()) 28214001Sgiacomo.travaglini@arm.com trap_to_hyp = hcr.imo && el == EL1; 28314001Sgiacomo.travaglini@arm.com break; 28413364Sgiacomo.travaglini@arm.com default: 28513364Sgiacomo.travaglini@arm.com break; 28613364Sgiacomo.travaglini@arm.com } 28713364Sgiacomo.travaglini@arm.com } 28813364Sgiacomo.travaglini@arm.com return trap_to_hyp; 28913364Sgiacomo.travaglini@arm.com} 29013364Sgiacomo.travaglini@arm.com 29113364Sgiacomo.travaglini@arm.combool 29213364Sgiacomo.travaglini@arm.comMiscRegOp64::checkEL3Trap(ThreadContext *tc, const MiscRegIndex misc_reg, 29313364Sgiacomo.travaglini@arm.com ExceptionLevel el, bool * is_vfp_neon) const 29413364Sgiacomo.travaglini@arm.com{ 29513364Sgiacomo.travaglini@arm.com const CPTR cptr = tc->readMiscReg(MISCREG_CPTR_EL3); 29613364Sgiacomo.travaglini@arm.com 29713364Sgiacomo.travaglini@arm.com bool trap_to_mon = false; 29813364Sgiacomo.travaglini@arm.com *is_vfp_neon = false; 29913364Sgiacomo.travaglini@arm.com 30013364Sgiacomo.travaglini@arm.com switch (misc_reg) { 30113364Sgiacomo.travaglini@arm.com // FP/SIMD regs 30213364Sgiacomo.travaglini@arm.com case MISCREG_FPCR: 30313364Sgiacomo.travaglini@arm.com case MISCREG_FPSR: 30413364Sgiacomo.travaglini@arm.com case MISCREG_FPEXC32_EL2: 30513364Sgiacomo.travaglini@arm.com trap_to_mon = cptr.tfp; 30613364Sgiacomo.travaglini@arm.com *is_vfp_neon = true; 30713364Sgiacomo.travaglini@arm.com break; 30813364Sgiacomo.travaglini@arm.com // CPACR, CPTR 30913364Sgiacomo.travaglini@arm.com case MISCREG_CPACR_EL1: 31013364Sgiacomo.travaglini@arm.com if (el == EL1 || el == EL2) { 31113364Sgiacomo.travaglini@arm.com trap_to_mon = cptr.tcpac; 31213364Sgiacomo.travaglini@arm.com } 31313364Sgiacomo.travaglini@arm.com break; 31413364Sgiacomo.travaglini@arm.com case MISCREG_CPTR_EL2: 31513364Sgiacomo.travaglini@arm.com if (el == EL2) { 31613364Sgiacomo.travaglini@arm.com trap_to_mon = cptr.tcpac; 31713364Sgiacomo.travaglini@arm.com } 31813364Sgiacomo.travaglini@arm.com break; 31913364Sgiacomo.travaglini@arm.com default: 32013364Sgiacomo.travaglini@arm.com break; 32113364Sgiacomo.travaglini@arm.com } 32213364Sgiacomo.travaglini@arm.com return trap_to_mon; 32313364Sgiacomo.travaglini@arm.com} 32413364Sgiacomo.travaglini@arm.com 32514127Sgiacomo.travaglini@arm.comRegVal 32614127Sgiacomo.travaglini@arm.comMiscRegImmOp64::miscRegImm() const 32714127Sgiacomo.travaglini@arm.com{ 32814127Sgiacomo.travaglini@arm.com if (dest == MISCREG_SPSEL) { 32914127Sgiacomo.travaglini@arm.com return imm & 0x1; 33014128Sgiacomo.travaglini@arm.com } else if (dest == MISCREG_PAN) { 33114128Sgiacomo.travaglini@arm.com return (imm & 0x1) << 22; 33214127Sgiacomo.travaglini@arm.com } else { 33314127Sgiacomo.travaglini@arm.com panic("Not a valid PSTATE field register\n"); 33414127Sgiacomo.travaglini@arm.com } 33514127Sgiacomo.travaglini@arm.com} 33614127Sgiacomo.travaglini@arm.com 33714127Sgiacomo.travaglini@arm.comstd::string 33814127Sgiacomo.travaglini@arm.comMiscRegImmOp64::generateDisassembly(Addr pc, const SymbolTable *symtab) const 33914127Sgiacomo.travaglini@arm.com{ 34014127Sgiacomo.travaglini@arm.com std::stringstream ss; 34114127Sgiacomo.travaglini@arm.com printMnemonic(ss); 34214127Sgiacomo.travaglini@arm.com printMiscReg(ss, dest); 34314127Sgiacomo.travaglini@arm.com ss << ", "; 34414127Sgiacomo.travaglini@arm.com ccprintf(ss, "#0x%x", imm); 34514127Sgiacomo.travaglini@arm.com return ss.str(); 34614127Sgiacomo.travaglini@arm.com} 34714127Sgiacomo.travaglini@arm.com 34812280Sgiacomo.travaglini@arm.comstd::string 34912280Sgiacomo.travaglini@arm.comMiscRegRegImmOp64::generateDisassembly( 35012280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 35112280Sgiacomo.travaglini@arm.com{ 35212280Sgiacomo.travaglini@arm.com std::stringstream ss; 35312280Sgiacomo.travaglini@arm.com printMnemonic(ss); 35412280Sgiacomo.travaglini@arm.com printMiscReg(ss, dest); 35512280Sgiacomo.travaglini@arm.com ss << ", "; 35612280Sgiacomo.travaglini@arm.com printIntReg(ss, op1); 35712280Sgiacomo.travaglini@arm.com return ss.str(); 35812280Sgiacomo.travaglini@arm.com} 35912280Sgiacomo.travaglini@arm.com 36012280Sgiacomo.travaglini@arm.comstd::string 36112280Sgiacomo.travaglini@arm.comRegMiscRegImmOp64::generateDisassembly( 36212280Sgiacomo.travaglini@arm.com Addr pc, const SymbolTable *symtab) const 36312280Sgiacomo.travaglini@arm.com{ 36412280Sgiacomo.travaglini@arm.com std::stringstream ss; 36512280Sgiacomo.travaglini@arm.com printMnemonic(ss); 36612280Sgiacomo.travaglini@arm.com printIntReg(ss, dest); 36712280Sgiacomo.travaglini@arm.com ss << ", "; 36812280Sgiacomo.travaglini@arm.com printMiscReg(ss, op1); 36912280Sgiacomo.travaglini@arm.com return ss.str(); 37012280Sgiacomo.travaglini@arm.com} 37113365Sgiacomo.travaglini@arm.com 37213365Sgiacomo.travaglini@arm.comFault 37313365Sgiacomo.travaglini@arm.comMiscRegImplDefined64::execute(ExecContext *xc, 37413365Sgiacomo.travaglini@arm.com Trace::InstRecord *traceData) const 37513365Sgiacomo.travaglini@arm.com{ 37613365Sgiacomo.travaglini@arm.com auto tc = xc->tcBase(); 37713365Sgiacomo.travaglini@arm.com const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 37813365Sgiacomo.travaglini@arm.com const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 37913365Sgiacomo.travaglini@arm.com 38013365Sgiacomo.travaglini@arm.com Fault fault = trap(tc, miscReg, el, imm); 38113365Sgiacomo.travaglini@arm.com 38213365Sgiacomo.travaglini@arm.com if (fault != NoFault) { 38313365Sgiacomo.travaglini@arm.com return fault; 38413365Sgiacomo.travaglini@arm.com 38513365Sgiacomo.travaglini@arm.com } else if (warning) { 38613365Sgiacomo.travaglini@arm.com warn_once("\tinstruction '%s' unimplemented\n", fullMnemonic.c_str()); 38713365Sgiacomo.travaglini@arm.com return NoFault; 38813365Sgiacomo.travaglini@arm.com 38913365Sgiacomo.travaglini@arm.com } else { 39013365Sgiacomo.travaglini@arm.com return std::make_shared<UndefinedInstruction>(machInst, false, 39113365Sgiacomo.travaglini@arm.com mnemonic); 39213365Sgiacomo.travaglini@arm.com } 39313365Sgiacomo.travaglini@arm.com} 39413365Sgiacomo.travaglini@arm.com 39513365Sgiacomo.travaglini@arm.comstd::string 39613365Sgiacomo.travaglini@arm.comMiscRegImplDefined64::generateDisassembly(Addr pc, 39713365Sgiacomo.travaglini@arm.com const SymbolTable *symtab) const 39813365Sgiacomo.travaglini@arm.com{ 39913365Sgiacomo.travaglini@arm.com return csprintf("%-10s (implementation defined)", fullMnemonic.c_str()); 40013365Sgiacomo.travaglini@arm.com} 401