/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/int_datatype/ |
H A D | int_datatype.cpp | 72 unsigned int op1 = VAL1; local 79 r1 = op1 * op2; // Multiplication 81 r2 = op1 / op2; // Division 83 r3 = op1 % op2; // Modulus 85 r4 = op1 + op2; // Addition 87 r5 = op1 - op2; // Subtraction 89 r6 = !op1; // Logical NOT 91 r7 = op1 && op2; // Logical AND 93 r8 = op1 || op2; // Logical OR 95 r9 = op1 < op [all...] |
/gem5/src/arch/arm/insts/ |
H A D | fplib.hh | 79 T fplibAdd(T op1, T op2, FPSCR &fpscr); 82 int fplibCompare(T op1, T op2, bool signal_nans, FPSCR &fpscr); 85 bool fplibCompareEQ(T op1, T op2, FPSCR &fpscr); 88 bool fplibCompareGE(T op1, T op2, FPSCR &fpscr); 91 bool fplibCompareGT(T op1, T op2, FPSCR &fpscr); 94 bool fplibCompareUN(T op1, T op2, FPSCR &fpscr); 100 T fplibDiv(T op1, T op2, FPSCR &fpscr); 106 T fplibMax(T op1, T op2, FPSCR &fpscr); 109 T fplibMaxNum(T op1, T op2, FPSCR &fpscr); 112 T fplibMin(T op1, [all...] |
H A D | data64.hh | 51 IntRegIndex dest, op1; member in class:ArmISA::DataXImmOp 57 dest(_dest), op1(_op1), imm(_imm) 83 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXSRegOp 91 dest(_dest), op1(_op1), op2(_op2), 102 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXERegOp 110 dest(_dest), op1(_op1), op2(_op2), 121 IntRegIndex dest, op1; member in class:ArmISA::DataX1RegOp 125 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 135 IntRegIndex dest, op1; member in class:ArmISA::DataX1RegImmOp 140 ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op 151 IntRegIndex dest, op1; member in class:ArmISA::DataX1Reg2ImmOp 168 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegOp 183 IntRegIndex dest, op1, op2; member in class:ArmISA::DataX2RegImmOp 200 IntRegIndex dest, op1, op2, op3; member in class:ArmISA::DataX3RegOp 216 IntRegIndex op1; member in class:ArmISA::DataXCondCompImmOp 235 IntRegIndex op1, op2; member in class:ArmISA::DataXCondCompRegOp 253 IntRegIndex dest, op1, op2; member in class:ArmISA::DataXCondSelOp [all...] |
H A D | branch.hh | 82 IntRegIndex op1; member in class:ArmISA::BranchReg 87 PredOp(mnem, _machInst, __opClass), op1(_op1) 111 IntRegIndex op1; member in class:ArmISA::BranchRegReg 117 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2) 128 IntRegIndex op1; member in class:ArmISA::BranchImmReg 133 PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
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H A D | sve.hh | 91 IntRegIndex op1; member in class:ArmISA::SveIndexRIOp 98 dest(_dest), op1(_op1), imm2(_imm2) 106 IntRegIndex op1; member in class:ArmISA::SveIndexRROp 113 dest(_dest), op1(_op1), op2(_op2) 140 IntRegIndex op1; member in class:ArmISA::SvePredCountPredOp 147 dest(_dest), op1(_op1), gp(_gp) 155 IntRegIndex dest, op1, op2; member in class:ArmISA::SveWhileOp 162 dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b) 170 IntRegIndex op1, op2; member in class:ArmISA::SveCompTermOp 175 op1(_op 183 IntRegIndex dest, op1, gp; member in class:ArmISA::SveUnaryPredOp 197 IntRegIndex dest, op1; member in class:ArmISA::SveUnaryUnpredOp 246 IntRegIndex dest, op1; member in class:ArmISA::SveBinImmUnpredConstrOp 308 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveBinConstrPredOp 325 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinUnpredOp 339 IntRegIndex dest, op1, op2; member in class:ArmISA::SveBinIdxUnpredOp 355 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SvePredLogicalOp 371 IntRegIndex dest, op1, op2; member in class:ArmISA::SvePredBinPermOp 386 IntRegIndex dest, gp, op1, op2; member in class:ArmISA::SveCmpOp 401 IntRegIndex dest, gp, op1; member in class:ArmISA::SveCmpImmOp 417 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveTerPredOp 448 IntRegIndex dest, op1, gp; member in class:ArmISA::SveReducOp 462 IntRegIndex dest, op1, gp; member in class:ArmISA::SveOrdReducOp 492 IntRegIndex op1, op2; member in class:ArmISA::SveIntCmpOp 509 IntRegIndex op1; member in class:ArmISA::SveIntCmpImmOp 532 IntRegIndex dest, op1, op2; member in class:ArmISA::SveAdrOp 572 IntRegIndex op1; member in class:ArmISA::SvePartBrkOp 588 IntRegIndex op1; member in class:ArmISA::SvePartBrkPropOp 605 IntRegIndex op1; member in class:ArmISA::SveSelectOp 628 IntRegIndex op1; member in class:ArmISA::SveUnaryPredPredOp 644 IntRegIndex op1; member in class:ArmISA::SveTblOp 659 IntRegIndex op1; member in class:ArmISA::SveUnpackOp 672 IntRegIndex op1; member in class:ArmISA::SvePredTestOp 714 IntRegIndex op1; member in class:ArmISA::SvePredUnaryWImplicitDstOp 738 IntRegIndex op1; member in class:ArmISA::SveBinImmUnpredDestrOp 753 IntRegIndex dest, op1; member in class:ArmISA::SveBinImmIdxUnpredOp 769 IntRegIndex dest, op1; member in class:ArmISA::SveUnarySca2VecUnpredOp 785 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdIdxOp 803 IntRegIndex dest, op1, op2; member in class:ArmISA::SveDotProdOp 820 IntRegIndex dest, op1, op2, gp; member in class:ArmISA::SveComplexOp 837 IntRegIndex dest, op1, op2; member in class:ArmISA::SveComplexIdxOp [all...] |
H A D | vfp.cc | 54 printIntReg(ss, op1); 71 printIntReg(ss, op1); 86 printFloatReg(ss, op1); 107 printFloatReg(ss, op1); 119 printFloatReg(ss, op1); 134 printFloatReg(ss, op1); 147 printFloatReg(ss, op1); 162 printFloatReg(ss, op1); 221 fixDest(bool flush, bool defaultNan, fpType val, fpType op1) argument 228 const bool nan = std::isnan(op1); 251 fixDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument 292 fixDivDest(bool flush, bool defaultNan, fpType val, fpType op1, fpType op2) argument 330 float op1 = 0.0; local 366 double op1 = 0.0; local 907 processNans(FPSCR &fpscr, bool &done, bool defaultNan, fpType op1, fpType op2) const argument 951 ternaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType op3, fpType (*func)(fpType, fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const argument 1029 binaryOp(FPSCR &fpscr, fpType op1, fpType op2, fpType (*func)(fpType, fpType), bool flush, bool defaultNan, uint32_t rMode) const argument 1100 unaryOp(FPSCR &fpscr, fpType op1, fpType (*func)(fpType), bool flush, uint32_t rMode) const argument 1170 nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2) argument 1182 nextIdxs(IntRegIndex &dest, IntRegIndex &op1) argument [all...] |
H A D | misc.hh | 89 IntRegIndex op1; member in class:MsrRegOp 93 MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1) 103 MiscRegIndex op1; member in class:MrrcOp 111 PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest), 122 IntRegIndex op1; member in class:McrrOp 130 PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2), 171 IntRegIndex op1; member in class:RegRegOp 175 PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1) 187 IntRegIndex op1; member in class:RegImmRegOp 192 dest(_dest), imm(_imm), op1(_op 203 IntRegIndex op1; member in class:RegRegRegImmOp 222 IntRegIndex op1; member in class:RegRegRegRegOp 241 IntRegIndex op1; member in class:RegRegRegOp 258 IntRegIndex op1; member in class:RegRegImmOp 276 IntRegIndex op1; member in class:MiscRegRegImmOp 294 MiscRegIndex op1; member in class:RegMiscRegImmOp 329 IntRegIndex op1; member in class:RegRegImmImmOp 349 IntRegIndex op1; member in class:RegImmRegShiftOp [all...] |
H A D | branch64.hh | 88 IntRegIndex op1; member in class:ArmISA::BranchReg64 93 ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) 130 IntRegIndex op1; member in class:ArmISA::BranchImmReg64 135 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 154 IntRegIndex op1; member in class:ArmISA::BranchImmImmReg64 161 imm1(_imm1), imm2(_imm2), op1(_op1)
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H A D | branch.cc | 51 printIntReg(ss, op1); 69 printIntReg(ss, op1);
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H A D | data64.cc | 49 printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, 68 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 77 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 89 printIntReg(ss, op1); 100 printIntReg(ss, op1); 112 printIntReg(ss, op1); 124 printIntReg(ss, op1); 137 printIntReg(ss, op1); 151 printIntReg(ss, op1); 165 printIntReg(ss, op1); [all...] |
H A D | branch64.cc | 98 printIntReg(ss, op1); 108 if (op1 != INTREG_X30) 109 printIntReg(ss, op1); 128 printIntReg(ss, op1); 140 printIntReg(ss, op1);
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H A D | misc.cc | 143 printIntReg(ss, op1); 156 printMiscReg(ss, op1); 167 printIntReg(ss, op1); 199 printIntReg(ss, op1); 210 printIntReg(ss, op1); 224 printIntReg(ss, op1); 239 printIntReg(ss, op1); 252 printIntReg(ss, op1); 264 printIntReg(ss, op1); 275 printMiscReg(ss, op1); [all...] |
H A D | vfp.hh | 131 flushToZero(fpType &op1, fpType &op2) argument 133 bool flush1 = flushToZero(op1); 149 vfpFlushToZero(FPSCR &fpscr, fpType &op1, fpType &op2) argument 151 vfpFlushToZero(fpscr, op1); 219 fpType fixDest(FPSCR fpscr, fpType val, fpType op1); 222 fpType fixDest(FPSCR fpscr, fpType val, fpType op1, fpType op2); 225 fpType fixDivDest(FPSCR fpscr, fpType val, fpType op1, fpType op2); 471 void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2); 472 void nextIdxs(IntRegIndex &dest, IntRegIndex &op1); 589 fpMulAdd(T op1, argument 788 doOp(float op1, float op2) const argument 800 doOp(double op1, double op2) const argument 885 IntRegIndex op1, op2; member in class:ArmISA::FpCondCompRegOp 903 IntRegIndex dest, op1, op2; member in class:ArmISA::FpCondSelOp 921 IntRegIndex op1; member in class:ArmISA::FpRegRegOp 957 IntRegIndex op1; member in class:ArmISA::FpRegRegImmOp 976 IntRegIndex op1; member in class:ArmISA::FpRegRegRegOp 995 IntRegIndex op1; member in class:ArmISA::FpRegRegRegCondOp 1017 IntRegIndex op1; member in class:ArmISA::FpRegRegRegRegOp 1038 IntRegIndex op1; member in class:ArmISA::FpRegRegRegImmOp [all...] |
H A D | sve.cc | 69 printVecPredReg(ss, op1); 121 printIntReg(ss, op1); 133 printIntReg(ss, op1); 151 printIntReg(ss, op1, opWidth); 162 printIntReg(ss, op1); 177 printVecReg(ss, op1, true); 188 printVecReg(ss, op1, true); 227 printVecPredReg(ss, op1); 291 printVecReg(ss, op1, true); 304 printVecReg(ss, op1, tru [all...] |
H A D | fplib.cc | 2379 fplibAdd(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 2382 uint16_t result = fp16_add(op1, op2, 0, modeConv(fpscr), &flags); 2389 fplibAdd(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 2392 uint32_t result = fp32_add(op1, op2, 0, modeConv(fpscr), &flags); 2399 fplibAdd(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 2402 uint64_t result = fp64_add(op1, op2, 0, modeConv(fpscr), &flags); 2409 fplibCompare(uint16_t op1, uint16_t op2, bool signal_nans, FPSCR &fpscr) argument 2416 fp16_unpack(&sgn1, &exp1, &mnt1, op1, mode, &flags); 2425 if (op1 == op2 || (!mnt1 && !mnt2)) { 2443 fplibCompare(uint32_t op1, uint32_ argument 2477 fplibCompare(uint64_t op1, uint64_t op2, bool signal_nans, FPSCR &fpscr) argument 2864 fplibMulAdd(uint16_t addend, uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 2874 fplibMulAdd(uint32_t addend, uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 2884 fplibMulAdd(uint64_t addend, uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 2894 fplibDiv(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 2904 fplibDiv(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 2914 fplibDiv(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3131 fp16_minmaxnum(uint16_t *op1, uint16_t *op2, int sgn) argument 3143 fp32_minmaxnum(uint32_t *op1, uint32_t *op2, int sgn) argument 3155 fp64_minmaxnum(uint64_t *op1, uint64_t *op2, int sgn) argument 3168 fplibMax(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3191 fplibMax(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3214 fplibMax(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3237 fplibMaxNum(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3245 fplibMaxNum(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3253 fplibMaxNum(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3261 fplibMin(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3284 fplibMin(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3307 fplibMin(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3330 fplibMinNum(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3338 fplibMinNum(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3346 fplibMinNum(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3354 fplibMul(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3364 fplibMul(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3374 fplibMul(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3384 fplibMulX(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3415 fplibMulX(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3446 fplibMulX(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3622 fplibRSqrtStepFused(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3652 fplibRSqrtStepFused(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3682 fplibRSqrtStepFused(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 3898 fplibRecipStepFused(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 3928 fplibRecipStepFused(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 3958 fplibRecipStepFused(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 4380 fp16_muladd(coeff[op2 >> (FP16_BITS - 1)][coeff_index], op1, local 4388 fplibTrigMulAdd(uint8_t coeff_index, uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 4422 fplibTrigMulAdd(uint8_t coeff_index, uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 4456 fplibTrigSMul(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 4476 fplibTrigSMul(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 4495 fplibTrigSMul(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument 4514 fplibTrigSSel(uint16_t op1, uint16_t op2, FPSCR &fpscr) argument 4525 fplibTrigSSel(uint32_t op1, uint32_t op2, FPSCR &fpscr) argument 4536 fplibTrigSSel(uint64_t op1, uint64_t op2, FPSCR &fpscr) argument [all...] |
H A D | misc64.hh | 64 IntRegIndex op1; member in class:RegRegImmImmOp64 72 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 83 IntRegIndex op1; member in class:RegRegRegImmOp64 91 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 174 IntRegIndex op1; member in class:MiscRegRegImmOp64 181 dest(_dest), op1(_op1), imm(_imm) 192 MiscRegIndex op1; member in class:RegMiscRegImmOp64 199 dest(_dest), op1(_op1), imm(_imm)
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H A D | pred_inst.cc | 82 printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1, 91 printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1, 100 printDataInst(ss, false, false, /*XXX not really s*/ false, dest, op1,
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H A D | pred_inst.hh | 281 IntRegIndex dest, op1; member in class:ArmISA::DataImmOp 290 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 300 IntRegIndex dest, op1, op2; member in class:ArmISA::DataRegOp 308 dest(_dest), op1(_op1), op2(_op2), 319 IntRegIndex dest, op1, op2, shift; member in class:ArmISA::DataRegRegOp 326 dest(_dest), op1(_op1), op2(_op2), shift(_shift),
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H A D | static_inst.hh | 82 saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) argument 84 int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 115 uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) argument 117 int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
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H A D | misc64.cc | 60 printIntReg(ss, op1); 73 printIntReg(ss, op1); 356 printIntReg(ss, op1); 368 printMiscReg(ss, op1);
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H A D | macromem.hh | 134 RegIndex dest, op1; member in class:ArmISA::MicroNeonMixOp 140 dest(_dest), op1(_op1), step(_step) 165 RegIndex dest, op1; member in class:ArmISA::MicroNeonMixOp64 172 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1), 182 RegIndex dest, op1; member in class:ArmISA::MicroNeonMixLaneOp64 191 : MicroOp(mnem, machInst, __opClass), dest(_dest), op1(_op1),
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/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_vector_datatype/ |
H A D | std_ulogic_vector_datatype.cpp | 490 std_ulogic_vector<4> op1; local 491 op1 = VAL1; 503 // r1 = op1 * op2; // Multiplication 505 // r2 = op1 / op2; // Division 507 // r3 = op1 % op2; // Modulus 509 // r4 = op1 + op2; // Addition 511 // r5 = op1 - op2; // Subtraction 513 // r6 = !op1; // Logical NOT 515 // r7 = op1 && op2; // Logical AND 517 // r8 = op1 || op [all...] |
/gem5/src/systemc/tests/systemc/misc/unit/data/user_guide/ch9/std_ulogic_datatype/ |
H A D | std_ulogic_datatype.cpp | 196 std_ulogic op1 = sc_logic(VAL1); local 203 // r1 = op1 * op2; // Multiplication 205 // r2 = op1 / op2; // Division 207 // r3 = op1 % op2; // Modulus 209 // r4 = op1 + op2; // Addition 211 // r5 = op1 - op2; // Subtraction 213 // r6 = !op1; // Logical NOT 215 // r7 = op1 && op2; // Logical AND 217 // r8 = op1 || op2; // Logical OR 219 // r9 = op1 < op [all...] |
/gem5/src/base/ |
H A D | circular_queue.hh | 105 moduloAdd(uint32_t op1, uint32_t op2, uint32_t size) argument 107 return (op1 + op2) % size; 112 moduloSub(uint32_t op1, uint32_t op2, uint32_t size) argument 114 int32_t ret = sub(op1, op2, size); 119 sub(uint32_t op1, uint32_t op2, uint32_t size) argument 121 if (op1 > op2) 122 return (op1 - op2) % size; 124 return -((op2 - op1) % size);
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/gem5/src/arch/arm/kvm/ |
H A D | armv8_cpu.cc | 185 const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1)); 190 decodeAArch64SysReg(op0, op1, crn, crm, op2)); 192 inform(" %s (op0: %i, op1: %i, crn: %i, crm: %i, op2: %i): %s", 193 miscRegName[idx], op0, op1, crn, crm, op2, 375 const uint64_t op1(EXTRACT_FIELD(reg, KVM_REG_ARM64_SYSREG_OP1)); 379 const MiscRegIndex idx(decodeAArch64SysReg(op0, op1, crn, crm, op2));
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