113759Sgiacomo.gabrielli@arm.com/* 213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2017-2019 ARM Limited 313759Sgiacomo.gabrielli@arm.com * All rights reserved 413759Sgiacomo.gabrielli@arm.com * 513759Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613759Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713759Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813759Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913759Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013759Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113759Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213759Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313759Sgiacomo.gabrielli@arm.com * 1413759Sgiacomo.gabrielli@arm.com * Redistribution and use in source and binary forms, with or without 1513759Sgiacomo.gabrielli@arm.com * modification, are permitted provided that the following conditions are 1613759Sgiacomo.gabrielli@arm.com * met: redistributions of source code must retain the above copyright 1713759Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer; 1813759Sgiacomo.gabrielli@arm.com * redistributions in binary form must reproduce the above copyright 1913759Sgiacomo.gabrielli@arm.com * notice, this list of conditions and the following disclaimer in the 2013759Sgiacomo.gabrielli@arm.com * documentation and/or other materials provided with the distribution; 2113759Sgiacomo.gabrielli@arm.com * neither the name of the copyright holders nor the names of its 2213759Sgiacomo.gabrielli@arm.com * contributors may be used to endorse or promote products derived from 2313759Sgiacomo.gabrielli@arm.com * this software without specific prior written permission. 2413759Sgiacomo.gabrielli@arm.com * 2513759Sgiacomo.gabrielli@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2613759Sgiacomo.gabrielli@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2713759Sgiacomo.gabrielli@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2813759Sgiacomo.gabrielli@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2913759Sgiacomo.gabrielli@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3013759Sgiacomo.gabrielli@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3113759Sgiacomo.gabrielli@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3213759Sgiacomo.gabrielli@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3313759Sgiacomo.gabrielli@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3413759Sgiacomo.gabrielli@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3513759Sgiacomo.gabrielli@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3613759Sgiacomo.gabrielli@arm.com * 3713759Sgiacomo.gabrielli@arm.com * Authors: Giacomo Gabrielli 3813759Sgiacomo.gabrielli@arm.com */ 3913759Sgiacomo.gabrielli@arm.com 4013759Sgiacomo.gabrielli@arm.com// TODO: add support for suffixes of register specifiers in disasm strings. 4113759Sgiacomo.gabrielli@arm.com 4213759Sgiacomo.gabrielli@arm.com#include "arch/arm/insts/sve.hh" 4313759Sgiacomo.gabrielli@arm.com 4413759Sgiacomo.gabrielli@arm.comnamespace ArmISA { 4513759Sgiacomo.gabrielli@arm.com 4613759Sgiacomo.gabrielli@arm.comconst char* 4713759Sgiacomo.gabrielli@arm.comsvePredTypeToStr(SvePredType pt) 4813759Sgiacomo.gabrielli@arm.com{ 4913759Sgiacomo.gabrielli@arm.com switch (pt) { 5013759Sgiacomo.gabrielli@arm.com case SvePredType::MERGE: 5113759Sgiacomo.gabrielli@arm.com return "m"; 5213759Sgiacomo.gabrielli@arm.com case SvePredType::ZERO: 5313759Sgiacomo.gabrielli@arm.com return "z"; 5413759Sgiacomo.gabrielli@arm.com default: 5513759Sgiacomo.gabrielli@arm.com return ""; 5613759Sgiacomo.gabrielli@arm.com } 5713759Sgiacomo.gabrielli@arm.com} 5813759Sgiacomo.gabrielli@arm.com 5913759Sgiacomo.gabrielli@arm.comstd::string 6013759Sgiacomo.gabrielli@arm.comSvePredCountPredOp::generateDisassembly(Addr pc, 6113759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 6213759Sgiacomo.gabrielli@arm.com{ 6313759Sgiacomo.gabrielli@arm.com std::stringstream ss; 6413759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 6513759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest); 6613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 6713759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 6813759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 6913759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 7013759Sgiacomo.gabrielli@arm.com return ss.str(); 7113759Sgiacomo.gabrielli@arm.com} 7213759Sgiacomo.gabrielli@arm.com 7313759Sgiacomo.gabrielli@arm.comstd::string 7413759Sgiacomo.gabrielli@arm.comSvePredCountOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 7513759Sgiacomo.gabrielli@arm.com{ 7613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 7713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 7813759Sgiacomo.gabrielli@arm.com if (destIsVec) { 7913759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 8013759Sgiacomo.gabrielli@arm.com } else { 8113759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest); 8213759Sgiacomo.gabrielli@arm.com } 8313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 8413759Sgiacomo.gabrielli@arm.com uint8_t opWidth = 64; 8513759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 8613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 8713759Sgiacomo.gabrielli@arm.com if (srcIs32b) 8813759Sgiacomo.gabrielli@arm.com opWidth = 32; 8913759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest, opWidth); 9013759Sgiacomo.gabrielli@arm.com return ss.str(); 9113759Sgiacomo.gabrielli@arm.com} 9213759Sgiacomo.gabrielli@arm.com 9313759Sgiacomo.gabrielli@arm.comstd::string 9413759Sgiacomo.gabrielli@arm.comSveIndexIIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9513759Sgiacomo.gabrielli@arm.com{ 9613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 9713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 9813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 9913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d, #%d", imm1, imm2); 10013759Sgiacomo.gabrielli@arm.com return ss.str(); 10113759Sgiacomo.gabrielli@arm.com} 10213759Sgiacomo.gabrielli@arm.com 10313759Sgiacomo.gabrielli@arm.comstd::string 10413759Sgiacomo.gabrielli@arm.comSveIndexIROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 10513759Sgiacomo.gabrielli@arm.com{ 10613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 10713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 10813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 10913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d, ", imm1); 11013759Sgiacomo.gabrielli@arm.com printIntReg(ss, op2); 11113759Sgiacomo.gabrielli@arm.com return ss.str(); 11213759Sgiacomo.gabrielli@arm.com} 11313759Sgiacomo.gabrielli@arm.com 11413759Sgiacomo.gabrielli@arm.comstd::string 11513759Sgiacomo.gabrielli@arm.comSveIndexRIOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 11613759Sgiacomo.gabrielli@arm.com{ 11713759Sgiacomo.gabrielli@arm.com std::stringstream ss; 11813759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 11913759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 12013759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 12113759Sgiacomo.gabrielli@arm.com printIntReg(ss, op1); 12213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #%d", imm2); 12313759Sgiacomo.gabrielli@arm.com return ss.str(); 12413759Sgiacomo.gabrielli@arm.com} 12513759Sgiacomo.gabrielli@arm.com 12613759Sgiacomo.gabrielli@arm.comstd::string 12713759Sgiacomo.gabrielli@arm.comSveIndexRROp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 12813759Sgiacomo.gabrielli@arm.com{ 12913759Sgiacomo.gabrielli@arm.com std::stringstream ss; 13013759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 13113759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 13213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 13313759Sgiacomo.gabrielli@arm.com printIntReg(ss, op1); 13413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 13513759Sgiacomo.gabrielli@arm.com printIntReg(ss, op2); 13613759Sgiacomo.gabrielli@arm.com return ss.str(); 13713759Sgiacomo.gabrielli@arm.com} 13813759Sgiacomo.gabrielli@arm.com 13913759Sgiacomo.gabrielli@arm.comstd::string 14013759Sgiacomo.gabrielli@arm.comSveWhileOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 14113759Sgiacomo.gabrielli@arm.com{ 14213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 14313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 14413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 14513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 14613759Sgiacomo.gabrielli@arm.com uint8_t opWidth; 14713759Sgiacomo.gabrielli@arm.com if (srcIs32b) 14813759Sgiacomo.gabrielli@arm.com opWidth = 32; 14913759Sgiacomo.gabrielli@arm.com else 15013759Sgiacomo.gabrielli@arm.com opWidth = 64; 15113759Sgiacomo.gabrielli@arm.com printIntReg(ss, op1, opWidth); 15213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 15313759Sgiacomo.gabrielli@arm.com printIntReg(ss, op2, opWidth); 15413759Sgiacomo.gabrielli@arm.com return ss.str(); 15513759Sgiacomo.gabrielli@arm.com} 15613759Sgiacomo.gabrielli@arm.com 15713759Sgiacomo.gabrielli@arm.comstd::string 15813759Sgiacomo.gabrielli@arm.comSveCompTermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 15913759Sgiacomo.gabrielli@arm.com{ 16013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 16113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 16213759Sgiacomo.gabrielli@arm.com printIntReg(ss, op1); 16313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 16413759Sgiacomo.gabrielli@arm.com printIntReg(ss, op2); 16513759Sgiacomo.gabrielli@arm.com return ss.str(); 16613759Sgiacomo.gabrielli@arm.com} 16713759Sgiacomo.gabrielli@arm.com 16813759Sgiacomo.gabrielli@arm.comstd::string 16913759Sgiacomo.gabrielli@arm.comSveUnaryPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 17013759Sgiacomo.gabrielli@arm.com{ 17113759Sgiacomo.gabrielli@arm.com std::stringstream ss; 17213759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 17313759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 17413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 17513759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 17613759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/m, "); 17713759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 17813759Sgiacomo.gabrielli@arm.com return ss.str(); 17913759Sgiacomo.gabrielli@arm.com} 18013759Sgiacomo.gabrielli@arm.com 18113759Sgiacomo.gabrielli@arm.comstd::string 18213759Sgiacomo.gabrielli@arm.comSveUnaryUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 18313759Sgiacomo.gabrielli@arm.com{ 18413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 18513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 18613759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 18713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 18813759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 18913759Sgiacomo.gabrielli@arm.com return ss.str(); 19013759Sgiacomo.gabrielli@arm.com} 19113759Sgiacomo.gabrielli@arm.com 19213759Sgiacomo.gabrielli@arm.comstd::string 19313759Sgiacomo.gabrielli@arm.comSveUnaryWideImmUnpredOp::generateDisassembly(Addr pc, 19413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 19513759Sgiacomo.gabrielli@arm.com{ 19613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 19713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 19813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 19913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 20013759Sgiacomo.gabrielli@arm.com ss << imm; 20113759Sgiacomo.gabrielli@arm.com return ss.str(); 20213759Sgiacomo.gabrielli@arm.com} 20313759Sgiacomo.gabrielli@arm.com 20413759Sgiacomo.gabrielli@arm.comstd::string 20513759Sgiacomo.gabrielli@arm.comSveUnaryWideImmPredOp::generateDisassembly(Addr pc, 20613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 20713759Sgiacomo.gabrielli@arm.com{ 20813759Sgiacomo.gabrielli@arm.com std::stringstream ss; 20913759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 21013759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 21113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 21213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 21313759Sgiacomo.gabrielli@arm.com ccprintf(ss, (isMerging ? "/m" : "/z")); 21413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 21513759Sgiacomo.gabrielli@arm.com ss << imm; 21613759Sgiacomo.gabrielli@arm.com return ss.str(); 21713759Sgiacomo.gabrielli@arm.com} 21813759Sgiacomo.gabrielli@arm.com 21913759Sgiacomo.gabrielli@arm.comstd::string 22013759Sgiacomo.gabrielli@arm.comSveBinImmUnpredConstrOp::generateDisassembly(Addr pc, 22113759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 22213759Sgiacomo.gabrielli@arm.com{ 22313759Sgiacomo.gabrielli@arm.com std::stringstream ss; 22413759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 22513759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 22613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 22713759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 22813759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 22913759Sgiacomo.gabrielli@arm.com ss << imm; 23013759Sgiacomo.gabrielli@arm.com return ss.str(); 23113759Sgiacomo.gabrielli@arm.com} 23213759Sgiacomo.gabrielli@arm.com 23313759Sgiacomo.gabrielli@arm.comstd::string 23413759Sgiacomo.gabrielli@arm.comSveBinImmPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 23513759Sgiacomo.gabrielli@arm.com{ 23613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 23713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 23813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 23913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 24013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 24113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/m, "); 24213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 24313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 24413759Sgiacomo.gabrielli@arm.com ss << imm; 24513759Sgiacomo.gabrielli@arm.com return ss.str(); 24613759Sgiacomo.gabrielli@arm.com} 24713759Sgiacomo.gabrielli@arm.com 24813759Sgiacomo.gabrielli@arm.comstd::string 24913759Sgiacomo.gabrielli@arm.comSveBinWideImmUnpredOp::generateDisassembly(Addr pc, 25013759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 25113759Sgiacomo.gabrielli@arm.com{ 25213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 25313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 25413759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 25513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 25613759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 25713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 25813759Sgiacomo.gabrielli@arm.com ss << imm; 25913759Sgiacomo.gabrielli@arm.com return ss.str(); 26013759Sgiacomo.gabrielli@arm.com} 26113759Sgiacomo.gabrielli@arm.com 26213759Sgiacomo.gabrielli@arm.comstd::string 26313759Sgiacomo.gabrielli@arm.comSveBinDestrPredOp::generateDisassembly(Addr pc, 26413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 26513759Sgiacomo.gabrielli@arm.com{ 26613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 26713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 26813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 26913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 27013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 27113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/m, "); 27213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 27313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 27413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 27513759Sgiacomo.gabrielli@arm.com return ss.str(); 27613759Sgiacomo.gabrielli@arm.com} 27713759Sgiacomo.gabrielli@arm.com 27813759Sgiacomo.gabrielli@arm.comstd::string 27913759Sgiacomo.gabrielli@arm.comSveBinConstrPredOp::generateDisassembly(Addr pc, 28013759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 28113759Sgiacomo.gabrielli@arm.com{ 28213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 28313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 28413759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 28513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 28613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 28713759Sgiacomo.gabrielli@arm.com if (predType == SvePredType::MERGE || predType == SvePredType::ZERO) { 28813759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/%s", svePredTypeToStr(predType)); 28913759Sgiacomo.gabrielli@arm.com } 29013759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 29113759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 29213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 29313759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 29413759Sgiacomo.gabrielli@arm.com return ss.str(); 29513759Sgiacomo.gabrielli@arm.com} 29613759Sgiacomo.gabrielli@arm.com 29713759Sgiacomo.gabrielli@arm.comstd::string 29813759Sgiacomo.gabrielli@arm.comSveBinUnpredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 29913759Sgiacomo.gabrielli@arm.com{ 30013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 30113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 30213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 30313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 30413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 30513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 30613759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 30713759Sgiacomo.gabrielli@arm.com return ss.str(); 30813759Sgiacomo.gabrielli@arm.com} 30913759Sgiacomo.gabrielli@arm.com 31013759Sgiacomo.gabrielli@arm.comstd::string 31113759Sgiacomo.gabrielli@arm.comSveBinIdxUnpredOp::generateDisassembly(Addr pc, 31213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 31313759Sgiacomo.gabrielli@arm.com{ 31413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 31513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 31613759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 31713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 31813759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 31913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 32013759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 32113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "["); 32213759Sgiacomo.gabrielli@arm.com ss << (uint64_t)index; 32313759Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 32413759Sgiacomo.gabrielli@arm.com return ss.str(); 32513759Sgiacomo.gabrielli@arm.com} 32613759Sgiacomo.gabrielli@arm.com 32713759Sgiacomo.gabrielli@arm.comstd::string 32813759Sgiacomo.gabrielli@arm.comSvePredLogicalOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 32913759Sgiacomo.gabrielli@arm.com{ 33013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 33113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 33213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 33313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 33413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 33513759Sgiacomo.gabrielli@arm.com if (isSel) { 33613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 33713759Sgiacomo.gabrielli@arm.com } else { 33813759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 33913759Sgiacomo.gabrielli@arm.com } 34013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 34113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 34213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op2); 34313759Sgiacomo.gabrielli@arm.com return ss.str(); 34413759Sgiacomo.gabrielli@arm.com} 34513759Sgiacomo.gabrielli@arm.com 34613759Sgiacomo.gabrielli@arm.comstd::string 34713759Sgiacomo.gabrielli@arm.comSvePredBinPermOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 34813759Sgiacomo.gabrielli@arm.com{ 34913759Sgiacomo.gabrielli@arm.com std::stringstream ss; 35013759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 35113759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 35213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 35313759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 35413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 35513759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op2); 35613759Sgiacomo.gabrielli@arm.com return ss.str(); 35713759Sgiacomo.gabrielli@arm.com} 35813759Sgiacomo.gabrielli@arm.com 35913759Sgiacomo.gabrielli@arm.comstd::string 36013759Sgiacomo.gabrielli@arm.comSveCmpOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 36113759Sgiacomo.gabrielli@arm.com{ 36213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 36313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 36413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 36513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 36613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 36713759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 36813759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 36913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 37013759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 37113759Sgiacomo.gabrielli@arm.com return ss.str(); 37213759Sgiacomo.gabrielli@arm.com} 37313759Sgiacomo.gabrielli@arm.com 37413759Sgiacomo.gabrielli@arm.comstd::string 37513759Sgiacomo.gabrielli@arm.comSveCmpImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 37613759Sgiacomo.gabrielli@arm.com{ 37713759Sgiacomo.gabrielli@arm.com std::stringstream ss; 37813759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 37913759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 38013759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 38113759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 38213759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 38313759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 38413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 38513759Sgiacomo.gabrielli@arm.com ss << imm; 38613759Sgiacomo.gabrielli@arm.com return ss.str(); 38713759Sgiacomo.gabrielli@arm.com} 38813759Sgiacomo.gabrielli@arm.com 38913759Sgiacomo.gabrielli@arm.comstd::string 39013759Sgiacomo.gabrielli@arm.comSveTerPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 39113759Sgiacomo.gabrielli@arm.com{ 39213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 39313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 39413759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 39513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 39613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 39713759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/m, "); 39813759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 39913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 40013759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 40113759Sgiacomo.gabrielli@arm.com return ss.str(); 40213759Sgiacomo.gabrielli@arm.com} 40313759Sgiacomo.gabrielli@arm.com 40413759Sgiacomo.gabrielli@arm.comstd::string 40513759Sgiacomo.gabrielli@arm.comSveTerImmUnpredOp::generateDisassembly(Addr pc, 40613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 40713759Sgiacomo.gabrielli@arm.com{ 40813759Sgiacomo.gabrielli@arm.com std::stringstream ss; 40913759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 41013759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 41113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 41213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 41313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 41413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 41513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 41613759Sgiacomo.gabrielli@arm.com ss << imm; 41713759Sgiacomo.gabrielli@arm.com return ss.str(); 41813759Sgiacomo.gabrielli@arm.com} 41913759Sgiacomo.gabrielli@arm.com 42013759Sgiacomo.gabrielli@arm.comstd::string 42113759Sgiacomo.gabrielli@arm.comSveReducOp::generateDisassembly(Addr pc, 42213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 42313759Sgiacomo.gabrielli@arm.com{ 42413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 42513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 42613759Sgiacomo.gabrielli@arm.com printFloatReg(ss, dest); 42713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 42813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 42913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 43013759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 43113759Sgiacomo.gabrielli@arm.com return ss.str(); 43213759Sgiacomo.gabrielli@arm.com} 43313759Sgiacomo.gabrielli@arm.com 43413759Sgiacomo.gabrielli@arm.comstd::string 43513759Sgiacomo.gabrielli@arm.comSveOrdReducOp::generateDisassembly(Addr pc, 43613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 43713759Sgiacomo.gabrielli@arm.com{ 43813759Sgiacomo.gabrielli@arm.com std::stringstream ss; 43913759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 44013759Sgiacomo.gabrielli@arm.com printFloatReg(ss, dest); 44113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 44213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 44313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 44413759Sgiacomo.gabrielli@arm.com printFloatReg(ss, dest); 44513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 44613759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 44713759Sgiacomo.gabrielli@arm.com return ss.str(); 44813759Sgiacomo.gabrielli@arm.com} 44913759Sgiacomo.gabrielli@arm.com 45013759Sgiacomo.gabrielli@arm.comstd::string 45113759Sgiacomo.gabrielli@arm.comSvePtrueOp::generateDisassembly(Addr pc, 45213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 45313759Sgiacomo.gabrielli@arm.com{ 45413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 45513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 45613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 45713759Sgiacomo.gabrielli@arm.com if (imm != 0x1f) { 45813759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 45913759Sgiacomo.gabrielli@arm.com ss << sveDisasmPredCountImm(imm); 46013759Sgiacomo.gabrielli@arm.com } 46113759Sgiacomo.gabrielli@arm.com return ss.str(); 46213759Sgiacomo.gabrielli@arm.com} 46313759Sgiacomo.gabrielli@arm.com 46413759Sgiacomo.gabrielli@arm.comstd::string 46513759Sgiacomo.gabrielli@arm.comSveIntCmpOp::generateDisassembly(Addr pc, 46613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 46713759Sgiacomo.gabrielli@arm.com{ 46813759Sgiacomo.gabrielli@arm.com std::stringstream ss; 46913759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 47013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 47113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 47213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 47313759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 47413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 47513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 47613759Sgiacomo.gabrielli@arm.com if (op2IsWide) { 47713759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 47813759Sgiacomo.gabrielli@arm.com } else { 47913759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 48013759Sgiacomo.gabrielli@arm.com } 48113759Sgiacomo.gabrielli@arm.com return ss.str(); 48213759Sgiacomo.gabrielli@arm.com} 48313759Sgiacomo.gabrielli@arm.com 48413759Sgiacomo.gabrielli@arm.comstd::string 48513759Sgiacomo.gabrielli@arm.comSveIntCmpImmOp::generateDisassembly(Addr pc, 48613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 48713759Sgiacomo.gabrielli@arm.com{ 48813759Sgiacomo.gabrielli@arm.com std::stringstream ss; 48913759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 49013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 49113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 49213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 49313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 49413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 49513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 49613759Sgiacomo.gabrielli@arm.com ss << imm; 49713759Sgiacomo.gabrielli@arm.com return ss.str(); 49813759Sgiacomo.gabrielli@arm.com} 49913759Sgiacomo.gabrielli@arm.com 50013759Sgiacomo.gabrielli@arm.comstd::string 50113759Sgiacomo.gabrielli@arm.comSveAdrOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 50213759Sgiacomo.gabrielli@arm.com{ 50313759Sgiacomo.gabrielli@arm.com std::stringstream ss; 50413759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 50513759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 50613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", ["); 50713759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 50813759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 50913759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 51013759Sgiacomo.gabrielli@arm.com if (offsetFormat == SveAdrOffsetUnpackedSigned) { 51113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", sxtw"); 51213759Sgiacomo.gabrielli@arm.com } else if (offsetFormat == SveAdrOffsetUnpackedUnsigned) { 51313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", uxtw"); 51413759Sgiacomo.gabrielli@arm.com } else if (mult != 1) { 51513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", lsl"); 51613759Sgiacomo.gabrielli@arm.com } 51713759Sgiacomo.gabrielli@arm.com if (mult != 1) { 51813759Sgiacomo.gabrielli@arm.com ss << __builtin_ctz(mult); 51913759Sgiacomo.gabrielli@arm.com } 52013759Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 52113759Sgiacomo.gabrielli@arm.com return ss.str(); 52213759Sgiacomo.gabrielli@arm.com} 52313759Sgiacomo.gabrielli@arm.com 52413759Sgiacomo.gabrielli@arm.comstd::string 52513759Sgiacomo.gabrielli@arm.comSveElemCountOp::generateDisassembly(Addr pc, 52613759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 52713759Sgiacomo.gabrielli@arm.com{ 52813759Sgiacomo.gabrielli@arm.com static const char suffix[9] = 52913759Sgiacomo.gabrielli@arm.com {'\0', 'b', 'h', '\0', 'w', '\0', '\0', '\0', 'd'}; 53013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 53113759Sgiacomo.gabrielli@arm.com ss << " " << mnemonic << suffix[esize] << " "; 53213759Sgiacomo.gabrielli@arm.com if (dstIsVec) { 53313759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 53413759Sgiacomo.gabrielli@arm.com } else { 53513759Sgiacomo.gabrielli@arm.com if (dstIs32b) { 53613759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest, 32); 53713759Sgiacomo.gabrielli@arm.com } else { 53813759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest, 64); 53913759Sgiacomo.gabrielli@arm.com } 54013759Sgiacomo.gabrielli@arm.com } 54113759Sgiacomo.gabrielli@arm.com if (pattern != 0x1f) { 54213759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 54313759Sgiacomo.gabrielli@arm.com ss << sveDisasmPredCountImm(pattern); 54413759Sgiacomo.gabrielli@arm.com if (imm != 1) { 54513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", mul #"); 54613759Sgiacomo.gabrielli@arm.com ss << std::to_string(imm); 54713759Sgiacomo.gabrielli@arm.com } 54813759Sgiacomo.gabrielli@arm.com } 54913759Sgiacomo.gabrielli@arm.com return ss.str(); 55013759Sgiacomo.gabrielli@arm.com} 55113759Sgiacomo.gabrielli@arm.com 55213759Sgiacomo.gabrielli@arm.comstd::string 55313759Sgiacomo.gabrielli@arm.comSvePartBrkOp::generateDisassembly(Addr pc, 55413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 55513759Sgiacomo.gabrielli@arm.com{ 55613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 55713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 55813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 55913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 56013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 56113759Sgiacomo.gabrielli@arm.com ccprintf(ss, isMerging ? "/m, " : "/z, "); 56213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 56313759Sgiacomo.gabrielli@arm.com return ss.str(); 56413759Sgiacomo.gabrielli@arm.com} 56513759Sgiacomo.gabrielli@arm.com 56613759Sgiacomo.gabrielli@arm.comstd::string 56713759Sgiacomo.gabrielli@arm.comSvePartBrkPropOp::generateDisassembly(Addr pc, 56813759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 56913759Sgiacomo.gabrielli@arm.com{ 57013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 57113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 57213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 57313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 57413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 57513759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 57613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 57713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 57813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op2); 57913759Sgiacomo.gabrielli@arm.com return ss.str(); 58013759Sgiacomo.gabrielli@arm.com} 58113759Sgiacomo.gabrielli@arm.com 58213759Sgiacomo.gabrielli@arm.comstd::string 58313759Sgiacomo.gabrielli@arm.comSveSelectOp::generateDisassembly(Addr pc, 58413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 58513759Sgiacomo.gabrielli@arm.com{ 58613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 58713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 58813759Sgiacomo.gabrielli@arm.com if (scalar) 58913759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest, scalar_width); 59013759Sgiacomo.gabrielli@arm.com else if (simdFp) 59113759Sgiacomo.gabrielli@arm.com printFloatReg(ss, dest); 59213759Sgiacomo.gabrielli@arm.com else 59313759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 59413759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 59513759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 59613759Sgiacomo.gabrielli@arm.com if (conditional) { 59713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 59813759Sgiacomo.gabrielli@arm.com if (scalar) 59913759Sgiacomo.gabrielli@arm.com printIntReg(ss, dest, scalar_width); 60013759Sgiacomo.gabrielli@arm.com else 60113759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 60213759Sgiacomo.gabrielli@arm.com } 60313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 60413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 60513759Sgiacomo.gabrielli@arm.com return ss.str(); 60613759Sgiacomo.gabrielli@arm.com} 60713759Sgiacomo.gabrielli@arm.com 60813759Sgiacomo.gabrielli@arm.comstd::string 60913759Sgiacomo.gabrielli@arm.comSveUnaryPredPredOp::generateDisassembly(Addr pc, 61013759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 61113759Sgiacomo.gabrielli@arm.com{ 61213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 61313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 61413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 61513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 61613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 61713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 61813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 61913759Sgiacomo.gabrielli@arm.com return ss.str(); 62013759Sgiacomo.gabrielli@arm.com} 62113759Sgiacomo.gabrielli@arm.com 62213759Sgiacomo.gabrielli@arm.comstd::string 62313759Sgiacomo.gabrielli@arm.comSveTblOp::generateDisassembly(Addr pc, 62413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 62513759Sgiacomo.gabrielli@arm.com{ 62613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 62713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 62813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 62913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", { "); 63013759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 63113759Sgiacomo.gabrielli@arm.com ccprintf(ss, " }, "); 63213759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 63313759Sgiacomo.gabrielli@arm.com return ss.str(); 63413759Sgiacomo.gabrielli@arm.com} 63513759Sgiacomo.gabrielli@arm.com 63613759Sgiacomo.gabrielli@arm.comstd::string 63713759Sgiacomo.gabrielli@arm.comSveUnpackOp::generateDisassembly(Addr pc, 63813759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 63913759Sgiacomo.gabrielli@arm.com{ 64013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 64113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 64213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 64313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 64413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 64513759Sgiacomo.gabrielli@arm.com return ss.str(); 64613759Sgiacomo.gabrielli@arm.com} 64713759Sgiacomo.gabrielli@arm.com 64813759Sgiacomo.gabrielli@arm.comstd::string 64913759Sgiacomo.gabrielli@arm.comSvePredTestOp::generateDisassembly(Addr pc, 65013759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 65113759Sgiacomo.gabrielli@arm.com{ 65213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 65313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 65413759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 65513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 65613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 65713759Sgiacomo.gabrielli@arm.com return ss.str(); 65813759Sgiacomo.gabrielli@arm.com} 65913759Sgiacomo.gabrielli@arm.com 66013759Sgiacomo.gabrielli@arm.comstd::string 66113759Sgiacomo.gabrielli@arm.comSvePredUnaryWImplicitSrcOp::generateDisassembly(Addr pc, 66213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 66313759Sgiacomo.gabrielli@arm.com{ 66413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 66513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 66613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 66713759Sgiacomo.gabrielli@arm.com return ss.str(); 66813759Sgiacomo.gabrielli@arm.com} 66913759Sgiacomo.gabrielli@arm.com 67013759Sgiacomo.gabrielli@arm.comstd::string 67113759Sgiacomo.gabrielli@arm.comSvePredUnaryWImplicitSrcPredOp::generateDisassembly(Addr pc, 67213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 67313759Sgiacomo.gabrielli@arm.com{ 67413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 67513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 67613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 67713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 67813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 67913759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/z, "); 68013759Sgiacomo.gabrielli@arm.com return ss.str(); 68113759Sgiacomo.gabrielli@arm.com} 68213759Sgiacomo.gabrielli@arm.com 68313759Sgiacomo.gabrielli@arm.comstd::string 68413759Sgiacomo.gabrielli@arm.comSvePredUnaryWImplicitDstOp::generateDisassembly(Addr pc, 68513759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 68613759Sgiacomo.gabrielli@arm.com{ 68713759Sgiacomo.gabrielli@arm.com std::stringstream ss; 68813759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 68913759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 69013759Sgiacomo.gabrielli@arm.com return ss.str(); 69113759Sgiacomo.gabrielli@arm.com} 69213759Sgiacomo.gabrielli@arm.com 69313759Sgiacomo.gabrielli@arm.comstd::string 69413759Sgiacomo.gabrielli@arm.comSveWImplicitSrcDstOp::generateDisassembly(Addr pc, 69513759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 69613759Sgiacomo.gabrielli@arm.com{ 69713759Sgiacomo.gabrielli@arm.com std::stringstream ss; 69813759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 69913759Sgiacomo.gabrielli@arm.com return ss.str(); 70013759Sgiacomo.gabrielli@arm.com} 70113759Sgiacomo.gabrielli@arm.com 70213759Sgiacomo.gabrielli@arm.comstd::string 70313759Sgiacomo.gabrielli@arm.comSveBinImmUnpredDestrOp::generateDisassembly(Addr pc, 70413759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 70513759Sgiacomo.gabrielli@arm.com{ 70613759Sgiacomo.gabrielli@arm.com std::stringstream ss; 70713759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 70813759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 70913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 71013759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 71113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 71213759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 71313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 71413759Sgiacomo.gabrielli@arm.com ss << imm; 71513759Sgiacomo.gabrielli@arm.com return ss.str(); 71613759Sgiacomo.gabrielli@arm.com} 71713759Sgiacomo.gabrielli@arm.com 71813759Sgiacomo.gabrielli@arm.comstd::string 71913759Sgiacomo.gabrielli@arm.comSveBinImmIdxUnpredOp::generateDisassembly(Addr pc, 72013759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 72113759Sgiacomo.gabrielli@arm.com{ 72213759Sgiacomo.gabrielli@arm.com std::stringstream ss; 72313759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 72413759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 72513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 72613759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 72713759Sgiacomo.gabrielli@arm.com ccprintf(ss, "["); 72813759Sgiacomo.gabrielli@arm.com ss << imm; 72913759Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 73013759Sgiacomo.gabrielli@arm.com return ss.str(); 73113759Sgiacomo.gabrielli@arm.com} 73213759Sgiacomo.gabrielli@arm.com 73313759Sgiacomo.gabrielli@arm.comstd::string 73413759Sgiacomo.gabrielli@arm.comSveUnarySca2VecUnpredOp::generateDisassembly(Addr pc, 73513759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 73613759Sgiacomo.gabrielli@arm.com{ 73713759Sgiacomo.gabrielli@arm.com std::stringstream ss; 73813759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 73913759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 74013759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 74113759Sgiacomo.gabrielli@arm.com if (simdFp) { 74213759Sgiacomo.gabrielli@arm.com printFloatReg(ss, op1); 74313759Sgiacomo.gabrielli@arm.com } else { 74413759Sgiacomo.gabrielli@arm.com printIntReg(ss, op1); 74513759Sgiacomo.gabrielli@arm.com } 74613759Sgiacomo.gabrielli@arm.com return ss.str(); 74713759Sgiacomo.gabrielli@arm.com} 74813759Sgiacomo.gabrielli@arm.com 74913759Sgiacomo.gabrielli@arm.comstd::string 75013759Sgiacomo.gabrielli@arm.comSveDotProdIdxOp::generateDisassembly(Addr pc, 75113759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 75213759Sgiacomo.gabrielli@arm.com{ 75313759Sgiacomo.gabrielli@arm.com std::stringstream ss; 75413759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 75513759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 75613759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 75713759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 75813759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 75913759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 76013759Sgiacomo.gabrielli@arm.com ccprintf(ss, "["); 76113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "%lu", imm); 76213759Sgiacomo.gabrielli@arm.com ccprintf(ss, "]"); 76313759Sgiacomo.gabrielli@arm.com return ss.str(); 76413759Sgiacomo.gabrielli@arm.com} 76513759Sgiacomo.gabrielli@arm.com 76613759Sgiacomo.gabrielli@arm.comstd::string 76713759Sgiacomo.gabrielli@arm.comSveDotProdOp::generateDisassembly(Addr pc, 76813759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 76913759Sgiacomo.gabrielli@arm.com{ 77013759Sgiacomo.gabrielli@arm.com std::stringstream ss; 77113759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 77213759Sgiacomo.gabrielli@arm.com printVecReg(ss, dest, true); 77313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 77413759Sgiacomo.gabrielli@arm.com printVecReg(ss, op1, true); 77513759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 77613759Sgiacomo.gabrielli@arm.com printVecReg(ss, op2, true); 77713759Sgiacomo.gabrielli@arm.com return ss.str(); 77813759Sgiacomo.gabrielli@arm.com} 77913759Sgiacomo.gabrielli@arm.com 78013759Sgiacomo.gabrielli@arm.comstd::string 78113759Sgiacomo.gabrielli@arm.comSveComplexOp::generateDisassembly(Addr pc, 78213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 78313759Sgiacomo.gabrielli@arm.com{ 78413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 78513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 78613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 78713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 78813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, gp); 78913759Sgiacomo.gabrielli@arm.com ccprintf(ss, "/m, "); 79013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 79113759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 79213759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op2); 79313759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", #"); 79413759Sgiacomo.gabrielli@arm.com const char* rotstr[4] = {"0", "90", "180", "270"}; 79513759Sgiacomo.gabrielli@arm.com ccprintf(ss, rotstr[rot]); 79613759Sgiacomo.gabrielli@arm.com 79713759Sgiacomo.gabrielli@arm.com return ss.str(); 79813759Sgiacomo.gabrielli@arm.com} 79913759Sgiacomo.gabrielli@arm.com 80013759Sgiacomo.gabrielli@arm.comstd::string 80113759Sgiacomo.gabrielli@arm.comSveComplexIdxOp::generateDisassembly(Addr pc, 80213759Sgiacomo.gabrielli@arm.com const SymbolTable *symtab) const 80313759Sgiacomo.gabrielli@arm.com{ 80413759Sgiacomo.gabrielli@arm.com std::stringstream ss; 80513759Sgiacomo.gabrielli@arm.com printMnemonic(ss, "", false); 80613759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, dest); 80713759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 80813759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op1); 80913759Sgiacomo.gabrielli@arm.com ccprintf(ss, ", "); 81013759Sgiacomo.gabrielli@arm.com printVecPredReg(ss, op2); 81113759Sgiacomo.gabrielli@arm.com ccprintf(ss, "["); 81213759Sgiacomo.gabrielli@arm.com ss << imm; 81313759Sgiacomo.gabrielli@arm.com ccprintf(ss, "], #"); 81413759Sgiacomo.gabrielli@arm.com const char* rotstr[4] = {"0", "90", "180", "270"}; 81513759Sgiacomo.gabrielli@arm.com ccprintf(ss, rotstr[rot]); 81613759Sgiacomo.gabrielli@arm.com return ss.str(); 81713759Sgiacomo.gabrielli@arm.com} 81813759Sgiacomo.gabrielli@arm.com 81913759Sgiacomo.gabrielli@arm.comstd::string 82013759Sgiacomo.gabrielli@arm.comsveDisasmPredCountImm(uint8_t imm) 82113759Sgiacomo.gabrielli@arm.com{ 82213759Sgiacomo.gabrielli@arm.com switch (imm) { 82313759Sgiacomo.gabrielli@arm.com case 0x0: 82413759Sgiacomo.gabrielli@arm.com return "POW2"; 82513759Sgiacomo.gabrielli@arm.com case 0x1: 82613759Sgiacomo.gabrielli@arm.com case 0x2: 82713759Sgiacomo.gabrielli@arm.com case 0x3: 82813759Sgiacomo.gabrielli@arm.com case 0x4: 82913759Sgiacomo.gabrielli@arm.com case 0x5: 83013759Sgiacomo.gabrielli@arm.com case 0x6: 83113759Sgiacomo.gabrielli@arm.com case 0x7: 83213759Sgiacomo.gabrielli@arm.com return "VL" + std::to_string(imm); 83313759Sgiacomo.gabrielli@arm.com case 0x8: 83413759Sgiacomo.gabrielli@arm.com case 0x9: 83513759Sgiacomo.gabrielli@arm.com case 0xa: 83613759Sgiacomo.gabrielli@arm.com case 0xb: 83713759Sgiacomo.gabrielli@arm.com case 0xc: 83813759Sgiacomo.gabrielli@arm.com case 0xd: 83913759Sgiacomo.gabrielli@arm.com return "VL" + std::to_string(1 << ((imm & 0x7) + 3)); 84013759Sgiacomo.gabrielli@arm.com case 0x1d: 84113759Sgiacomo.gabrielli@arm.com return "MUL4"; 84213759Sgiacomo.gabrielli@arm.com case 0x1e: 84313759Sgiacomo.gabrielli@arm.com return "MUL3"; 84413759Sgiacomo.gabrielli@arm.com case 0x1f: 84513759Sgiacomo.gabrielli@arm.com return "ALL"; 84613759Sgiacomo.gabrielli@arm.com default: 84713759Sgiacomo.gabrielli@arm.com return "#" + std::to_string(imm); 84813759Sgiacomo.gabrielli@arm.com } 84913759Sgiacomo.gabrielli@arm.com} 85013759Sgiacomo.gabrielli@arm.com 85113759Sgiacomo.gabrielli@arm.comunsigned int 85213759Sgiacomo.gabrielli@arm.comsveDecodePredCount(uint8_t imm, unsigned int num_elems) 85313759Sgiacomo.gabrielli@arm.com{ 85413759Sgiacomo.gabrielli@arm.com assert(num_elems > 0); 85513759Sgiacomo.gabrielli@arm.com 85613759Sgiacomo.gabrielli@arm.com switch (imm) { 85713759Sgiacomo.gabrielli@arm.com case 0x0: 85813759Sgiacomo.gabrielli@arm.com // POW2 85913759Sgiacomo.gabrielli@arm.com return 1 << (31 - __builtin_clz((uint32_t) num_elems)); 86013759Sgiacomo.gabrielli@arm.com case 0x1: 86113759Sgiacomo.gabrielli@arm.com case 0x2: 86213759Sgiacomo.gabrielli@arm.com case 0x3: 86313759Sgiacomo.gabrielli@arm.com case 0x4: 86413759Sgiacomo.gabrielli@arm.com case 0x5: 86513759Sgiacomo.gabrielli@arm.com case 0x6: 86613759Sgiacomo.gabrielli@arm.com case 0x7: 86713759Sgiacomo.gabrielli@arm.com // VL1, VL2, VL3, VL4, VL5, VL6, VL7 86813759Sgiacomo.gabrielli@arm.com return (num_elems >= imm) ? imm : 0; 86913759Sgiacomo.gabrielli@arm.com case 0x8: 87013759Sgiacomo.gabrielli@arm.com case 0x9: 87113759Sgiacomo.gabrielli@arm.com case 0xa: 87213759Sgiacomo.gabrielli@arm.com case 0xb: 87313759Sgiacomo.gabrielli@arm.com case 0xc: 87413759Sgiacomo.gabrielli@arm.com case 0xd: 87513759Sgiacomo.gabrielli@arm.com // VL8, VL16, VL32, VL64, VL128, VL256 87613759Sgiacomo.gabrielli@arm.com { 87713759Sgiacomo.gabrielli@arm.com unsigned int pcount = 1 << ((imm & 0x7) + 3); 87813759Sgiacomo.gabrielli@arm.com return (num_elems >= pcount) ? pcount : 0; 87913759Sgiacomo.gabrielli@arm.com } 88013759Sgiacomo.gabrielli@arm.com case 0x1d: 88113759Sgiacomo.gabrielli@arm.com // MUL4 88213759Sgiacomo.gabrielli@arm.com return num_elems - (num_elems % 4); 88313759Sgiacomo.gabrielli@arm.com case 0x1e: 88413759Sgiacomo.gabrielli@arm.com // MUL3 88513759Sgiacomo.gabrielli@arm.com return num_elems - (num_elems % 3); 88613759Sgiacomo.gabrielli@arm.com case 0x1f: 88713759Sgiacomo.gabrielli@arm.com // ALL 88813759Sgiacomo.gabrielli@arm.com return num_elems; 88913759Sgiacomo.gabrielli@arm.com default: 89013759Sgiacomo.gabrielli@arm.com return 0; 89113759Sgiacomo.gabrielli@arm.com } 89213759Sgiacomo.gabrielli@arm.com} 89313759Sgiacomo.gabrielli@arm.com 89413759Sgiacomo.gabrielli@arm.comuint64_t 89513759Sgiacomo.gabrielli@arm.comsveExpandFpImmAddSub(uint8_t imm, uint8_t size) 89613759Sgiacomo.gabrielli@arm.com{ 89713759Sgiacomo.gabrielli@arm.com static constexpr uint16_t fpOne16 = 0x3c00; 89813759Sgiacomo.gabrielli@arm.com static constexpr uint16_t fpPointFive16 = 0x3800; 89913759Sgiacomo.gabrielli@arm.com static constexpr uint32_t fpOne32 = 0x3f800000; 90013759Sgiacomo.gabrielli@arm.com static constexpr uint32_t fpPointFive32 = 0x3f000000; 90113759Sgiacomo.gabrielli@arm.com static constexpr uint64_t fpOne64 = 0x3ff0000000000000; 90213759Sgiacomo.gabrielli@arm.com static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000; 90313759Sgiacomo.gabrielli@arm.com 90413759Sgiacomo.gabrielli@arm.com switch (size) { 90513759Sgiacomo.gabrielli@arm.com case 0x1: 90613759Sgiacomo.gabrielli@arm.com return imm ? fpOne16 : fpPointFive16; 90713759Sgiacomo.gabrielli@arm.com case 0x2: 90813759Sgiacomo.gabrielli@arm.com return imm ? fpOne32 : fpPointFive32; 90913759Sgiacomo.gabrielli@arm.com case 0x3: 91013759Sgiacomo.gabrielli@arm.com return imm ? fpOne64 : fpPointFive64; 91113759Sgiacomo.gabrielli@arm.com default: 91213759Sgiacomo.gabrielli@arm.com panic("Unsupported size"); 91313759Sgiacomo.gabrielli@arm.com } 91413759Sgiacomo.gabrielli@arm.com} 91513759Sgiacomo.gabrielli@arm.com 91613759Sgiacomo.gabrielli@arm.comuint64_t 91713759Sgiacomo.gabrielli@arm.comsveExpandFpImmMaxMin(uint8_t imm, uint8_t size) 91813759Sgiacomo.gabrielli@arm.com{ 91913759Sgiacomo.gabrielli@arm.com static constexpr uint16_t fpOne16 = 0x3c00; 92013759Sgiacomo.gabrielli@arm.com static constexpr uint32_t fpOne32 = 0x3f800000; 92113759Sgiacomo.gabrielli@arm.com static constexpr uint64_t fpOne64 = 0x3ff0000000000000; 92213759Sgiacomo.gabrielli@arm.com 92313759Sgiacomo.gabrielli@arm.com switch (size) { 92413759Sgiacomo.gabrielli@arm.com case 0x1: 92513759Sgiacomo.gabrielli@arm.com return imm ? fpOne16 : 0x0; 92613759Sgiacomo.gabrielli@arm.com case 0x2: 92713759Sgiacomo.gabrielli@arm.com return imm ? fpOne32 : 0x0; 92813759Sgiacomo.gabrielli@arm.com case 0x3: 92913759Sgiacomo.gabrielli@arm.com return imm ? fpOne64 : 0x0; 93013759Sgiacomo.gabrielli@arm.com default: 93113759Sgiacomo.gabrielli@arm.com panic("Unsupported size"); 93213759Sgiacomo.gabrielli@arm.com } 93313759Sgiacomo.gabrielli@arm.com} 93413759Sgiacomo.gabrielli@arm.com 93513759Sgiacomo.gabrielli@arm.comuint64_t 93613759Sgiacomo.gabrielli@arm.comsveExpandFpImmMul(uint8_t imm, uint8_t size) 93713759Sgiacomo.gabrielli@arm.com{ 93813759Sgiacomo.gabrielli@arm.com static constexpr uint16_t fpTwo16 = 0x4000; 93913759Sgiacomo.gabrielli@arm.com static constexpr uint16_t fpPointFive16 = 0x3800; 94013759Sgiacomo.gabrielli@arm.com static constexpr uint32_t fpTwo32 = 0x40000000; 94113759Sgiacomo.gabrielli@arm.com static constexpr uint32_t fpPointFive32 = 0x3f000000; 94213759Sgiacomo.gabrielli@arm.com static constexpr uint64_t fpTwo64 = 0x4000000000000000; 94313759Sgiacomo.gabrielli@arm.com static constexpr uint64_t fpPointFive64 = 0x3fe0000000000000; 94413759Sgiacomo.gabrielli@arm.com 94513759Sgiacomo.gabrielli@arm.com switch (size) { 94613759Sgiacomo.gabrielli@arm.com case 0x1: 94713759Sgiacomo.gabrielli@arm.com return imm ? fpTwo16 : fpPointFive16; 94813759Sgiacomo.gabrielli@arm.com case 0x2: 94913759Sgiacomo.gabrielli@arm.com return imm ? fpTwo32 : fpPointFive32; 95013759Sgiacomo.gabrielli@arm.com case 0x3: 95113759Sgiacomo.gabrielli@arm.com return imm ? fpTwo64 : fpPointFive64; 95213759Sgiacomo.gabrielli@arm.com default: 95313759Sgiacomo.gabrielli@arm.com panic("Unsupported size"); 95413759Sgiacomo.gabrielli@arm.com } 95513759Sgiacomo.gabrielli@arm.com} 95613759Sgiacomo.gabrielli@arm.com 95713759Sgiacomo.gabrielli@arm.com} // namespace ArmISA 958