History log of /gem5/src/arch/arm/insts/branch.hh
Revision Date Author Comments
# 12640:02188fc84bae 27-Mar-2018 Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Fix AArch32 branch instructions disassemble

This patch adds the generateDisassembly method for BranchReg, BranchImm
and BranchRegReg Base classes used by AArch32 branch instructions.

Change-Id: I6de015cc213335556d5187df3d4fcd765876262c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>


# 8909:7fa0a081f12f 21-Mar-2012 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Clean up condCodes in IT blocks.


# 8146:18368caa8489 17-Mar-2011 Ali Saidi <Ali.Saidi@ARM.com>

ARM: Identify branches as conditional or unconditional and direct or indirect.


# 7153:6ce0bf0ddaf3 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Eliminate the old style branch instructions.


# 7149:97666c2fc7a5 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Implement new base classes for branches.


# 7144:097e00bcf084 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Get rid of the unused Jump format.


# 7099:1949ba4db2cf 02-Jun-2010 Gabe Black <gblack@eecs.umich.edu>

ARM: Make sure ExtMachInst is used consistently instead of regular MachInst.


# 6253:988a001820f8 21-Jun-2009 Gabe Black <gblack@eecs.umich.edu>

ARM: Simplify the ISA desc by pulling some classes out of it.