112640Sgiacomo.travaglini@arm.com/* 212640Sgiacomo.travaglini@arm.com * Copyright (c) 2018 ARM Limited 312640Sgiacomo.travaglini@arm.com * All rights reserved 412640Sgiacomo.travaglini@arm.com * 512640Sgiacomo.travaglini@arm.com * The license below extends only to copyright in the software and shall 612640Sgiacomo.travaglini@arm.com * not be construed as granting a license to any other intellectual 712640Sgiacomo.travaglini@arm.com * property including but not limited to intellectual property relating 812640Sgiacomo.travaglini@arm.com * to a hardware implementation of the functionality of the software 912640Sgiacomo.travaglini@arm.com * licensed hereunder. You may use the software subject to the license 1012640Sgiacomo.travaglini@arm.com * terms below provided that you ensure that this notice is replicated 1112640Sgiacomo.travaglini@arm.com * unmodified and in its entirety in all distributions of the software, 1212640Sgiacomo.travaglini@arm.com * modified or unmodified, in source code or in binary form. 1312640Sgiacomo.travaglini@arm.com * 1412640Sgiacomo.travaglini@arm.com * Redistribution and use in source and binary forms, with or without 1512640Sgiacomo.travaglini@arm.com * modification, are permitted provided that the following conditions are 1612640Sgiacomo.travaglini@arm.com * met: redistributions of source code must retain the above copyright 1712640Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer; 1812640Sgiacomo.travaglini@arm.com * redistributions in binary form must reproduce the above copyright 1912640Sgiacomo.travaglini@arm.com * notice, this list of conditions and the following disclaimer in the 2012640Sgiacomo.travaglini@arm.com * documentation and/or other materials provided with the distribution; 2112640Sgiacomo.travaglini@arm.com * neither the name of the copyright holders nor the names of its 2212640Sgiacomo.travaglini@arm.com * contributors may be used to endorse or promote products derived from 2312640Sgiacomo.travaglini@arm.com * this software without specific prior written permission. 2412640Sgiacomo.travaglini@arm.com * 2512640Sgiacomo.travaglini@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2612640Sgiacomo.travaglini@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2712640Sgiacomo.travaglini@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2812640Sgiacomo.travaglini@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2912640Sgiacomo.travaglini@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3012640Sgiacomo.travaglini@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3112640Sgiacomo.travaglini@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3212640Sgiacomo.travaglini@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3312640Sgiacomo.travaglini@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3412640Sgiacomo.travaglini@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3512640Sgiacomo.travaglini@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3612640Sgiacomo.travaglini@arm.com * 3712640Sgiacomo.travaglini@arm.com * Authors: Giacomo Travaglini 3812640Sgiacomo.travaglini@arm.com */ 3912640Sgiacomo.travaglini@arm.com 4012640Sgiacomo.travaglini@arm.com#include "arch/arm/insts/branch.hh" 4112640Sgiacomo.travaglini@arm.com 4212640Sgiacomo.travaglini@arm.com#include "base/cprintf.hh" 4312640Sgiacomo.travaglini@arm.com 4412640Sgiacomo.travaglini@arm.comnamespace ArmISA { 4512640Sgiacomo.travaglini@arm.com 4612640Sgiacomo.travaglini@arm.comstd::string 4712640Sgiacomo.travaglini@arm.comBranchReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const 4812640Sgiacomo.travaglini@arm.com{ 4912640Sgiacomo.travaglini@arm.com std::stringstream ss; 5012640Sgiacomo.travaglini@arm.com printMnemonic(ss, "", false); 5112640Sgiacomo.travaglini@arm.com printIntReg(ss, op1); 5212640Sgiacomo.travaglini@arm.com return ss.str(); 5312640Sgiacomo.travaglini@arm.com} 5412640Sgiacomo.travaglini@arm.com 5512640Sgiacomo.travaglini@arm.comstd::string 5612640Sgiacomo.travaglini@arm.comBranchImm::generateDisassembly(Addr pc, const SymbolTable *symtab) const 5712640Sgiacomo.travaglini@arm.com{ 5812640Sgiacomo.travaglini@arm.com std::stringstream ss; 5912640Sgiacomo.travaglini@arm.com printMnemonic(ss, "", false); 6012640Sgiacomo.travaglini@arm.com printTarget(ss, pc + imm, symtab); 6112640Sgiacomo.travaglini@arm.com return ss.str(); 6212640Sgiacomo.travaglini@arm.com} 6312640Sgiacomo.travaglini@arm.com 6412640Sgiacomo.travaglini@arm.comstd::string 6512640Sgiacomo.travaglini@arm.comBranchRegReg::generateDisassembly(Addr pc, const SymbolTable *symtab) const 6612640Sgiacomo.travaglini@arm.com{ 6712640Sgiacomo.travaglini@arm.com std::stringstream ss; 6812640Sgiacomo.travaglini@arm.com printMnemonic(ss, "", false); 6912640Sgiacomo.travaglini@arm.com printIntReg(ss, op1); 7012640Sgiacomo.travaglini@arm.com ccprintf(ss, ", "); 7112640Sgiacomo.travaglini@arm.com printIntReg(ss, op2); 7212640Sgiacomo.travaglini@arm.com return ss.str(); 7312640Sgiacomo.travaglini@arm.com} 7412640Sgiacomo.travaglini@arm.com 7512640Sgiacomo.travaglini@arm.com} // namespace ArmISA 76