1/*
2 * Copyright (c) 2011-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "arch/arm/insts/data64.hh"
41
42namespace ArmISA
43{
44
45std::string
46DataXImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
47{
48    std::stringstream ss;
49    printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
50                  INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
51    return ss.str();
52}
53
54std::string
55DataXImmOnlyOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
56{
57    std::stringstream ss;
58    printMnemonic(ss, "", false);
59    printIntReg(ss, dest);
60    ccprintf(ss, ", #%d", imm);
61    return ss.str();
62}
63
64std::string
65DataXSRegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
66{
67    std::stringstream ss;
68    printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
69                  op2, INTREG_ZERO, shiftAmt, shiftType, 0);
70    return ss.str();
71}
72
73std::string
74DataXERegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
75{
76    std::stringstream ss;
77    printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
78                  op2, INTREG_ZERO, shiftAmt, LSL, 0);
79    return ss.str();
80}
81
82std::string
83DataX1RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
84{
85    std::stringstream ss;
86    printMnemonic(ss, "", false);
87    printIntReg(ss, dest);
88    ccprintf(ss, ", ");
89    printIntReg(ss, op1);
90    return ss.str();
91}
92
93std::string
94DataX1RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
95{
96    std::stringstream ss;
97    printMnemonic(ss, "", false);
98    printIntReg(ss, dest);
99    ccprintf(ss, ", ");
100    printIntReg(ss, op1);
101    ccprintf(ss, ", #%d", imm);
102    return ss.str();
103}
104
105std::string
106DataX1Reg2ImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
107{
108    std::stringstream ss;
109    printMnemonic(ss, "", false);
110    printIntReg(ss, dest);
111    ccprintf(ss, ", ");
112    printIntReg(ss, op1);
113    ccprintf(ss, ", #%d, #%d", imm1, imm2);
114    return ss.str();
115}
116
117std::string
118DataX2RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
119{
120    std::stringstream ss;
121    printMnemonic(ss, "", false);
122    printIntReg(ss, dest);
123    ccprintf(ss, ", ");
124    printIntReg(ss, op1);
125    ccprintf(ss, ", ");
126    printIntReg(ss, op2);
127    return ss.str();
128}
129
130std::string
131DataX2RegImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
132{
133    std::stringstream ss;
134    printMnemonic(ss, "", false);
135    printIntReg(ss, dest);
136    ccprintf(ss, ", ");
137    printIntReg(ss, op1);
138    ccprintf(ss, ", ");
139    printIntReg(ss, op2);
140    ccprintf(ss, ", #%d", imm);
141    return ss.str();
142}
143
144std::string
145DataX3RegOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
146{
147    std::stringstream ss;
148    printMnemonic(ss, "", false);
149    printIntReg(ss, dest);
150    ccprintf(ss, ", ");
151    printIntReg(ss, op1);
152    ccprintf(ss, ", ");
153    printIntReg(ss, op2);
154    ccprintf(ss, ", ");
155    printIntReg(ss, op3);
156    return ss.str();
157}
158
159std::string
160DataXCondCompImmOp::generateDisassembly(
161        Addr pc, const SymbolTable *symtab) const
162{
163    std::stringstream ss;
164    printMnemonic(ss, "", false);
165    printIntReg(ss, op1);
166    ccprintf(ss, ", #%d, #%d", imm, defCc);
167    ccprintf(ss, ", ");
168    printCondition(ss, condCode, true);
169    return ss.str();
170}
171
172std::string
173DataXCondCompRegOp::generateDisassembly(
174        Addr pc, const SymbolTable *symtab) const
175{
176    std::stringstream ss;
177    printMnemonic(ss, "", false);
178    printIntReg(ss, op1);
179    ccprintf(ss, ", ");
180    printIntReg(ss, op2);
181    ccprintf(ss, ", #%d", defCc);
182    ccprintf(ss, ", ");
183    printCondition(ss, condCode, true);
184    return ss.str();
185}
186
187std::string
188DataXCondSelOp::generateDisassembly(
189        Addr pc, const SymbolTable *symtab) const
190{
191    std::stringstream ss;
192    printMnemonic(ss, "", false);
193    printIntReg(ss, dest);
194    ccprintf(ss, ", ");
195    printIntReg(ss, op1);
196    ccprintf(ss, ", ");
197    printIntReg(ss, op2);
198    ccprintf(ss, ", ");
199    printCondition(ss, condCode, true);
200    return ss.str();
201}
202
203}
204