/gem5/src/cpu/pred/ |
H A D | multiperspective_perceptron_tage_8KB.cc | 122 const StaticInstPtr &inst, bool taken, 125 int brtype = inst->isDirectCtrl() ? 0 : 2; 126 if (! inst->isUncondCtrl()) { 135 sh->updateHistoryStack(corrTarget, taken, inst->isCall(), 136 inst->isReturn()); 138 StatisticalCorrector::scHistoryUpdate(branch_pc, inst, taken, bi, 121 scHistoryUpdate(Addr branch_pc, const StaticInstPtr &inst, bool taken, StatisticalCorrector::BranchInfo *bi, Addr corrTarget) argument
|
H A D | ltage.hh | 71 bool squashed, const StaticInstPtr & inst,
|
H A D | tage.hh | 90 bool squashed, const StaticInstPtr & inst,
|
/gem5/src/arch/x86/ |
H A D | faults.cc | 55 void X86FaultBase::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument 58 FaultBase::invoke(tc, inst); 109 void X86Trap::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument 121 void X86Abort::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument 127 InvalidOpcode::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument 130 X86Fault::invoke(tc, inst); 133 inst->machInst); 137 void PageFault::invoke(ThreadContext * tc, const StaticInstPtr &inst) argument 167 if (!inst) { 172 inst 186 invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 304 invoke(ThreadContext *tc, const StaticInstPtr &inst) argument [all...] |
H A D | utility.hh | 90 advancePC(PCState &pc, const StaticInstPtr &inst) argument 92 inst->advancePC(pc);
|
H A D | faults.hh | 88 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 123 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 136 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 158 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 252 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 335 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 404 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 415 void invoke(ThreadContext * tc, const StaticInstPtr &inst =
|
/gem5/src/cpu/minor/ |
H A D | func_unit.hh | 201 MinorDynInstPtr inst; member in class:Minor::QueuedInst 205 inst(inst_) 211 bool isBubble() const { return inst->isBubble(); } 217 /** Functional units have pipelines which stall when an inst gets to 260 MinorFUTiming *findTiming(const StaticInstPtr &inst);
|
H A D | exec_context.hh | 86 MinorDynInstPtr inst; member in class:Minor::ExecContext 95 inst(inst_) 97 DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", inst->pc); 98 pcState(inst->pc); 99 setPredicate(inst->readPredicate()); 100 setMemAccPredicate(inst->readMemAccPredicate()); 109 inst->setPredicate(readPredicate()); 110 inst->setMemAccPredicate(readMemAccPredicate()); 119 return execute.getLSQ().pushRequest(inst, true /* load */, nullptr, 130 return execute.getLSQ().pushRequest(inst, fals [all...] |
H A D | pipe_data.hh | 89 /* Suspend fetching for this thread (inst->id.threadId). 124 MinorDynInstPtr inst; member in class:Minor::BranchData 130 inst(MinorDynInst::bubble()) 145 inst(inst_) 185 /** PC of the first requested inst within this line */ 277 /** Copy the inst array only as far as numInsts */
|
/gem5/src/cpu/simple/probes/ |
H A D | simpoint.cc | 81 const StaticInstPtr &inst = p.second; local 83 if (inst->isMicroop() && !inst->isLastMicroop()) 92 // If inst is control inst, assume end of basic block. 93 if (inst->isControl()) { 113 // Reached end of interval if the sum of the current inst count 114 // (intervalCount) and the excessive inst count from the previous
|
/gem5/src/arch/arm/ |
H A D | stacktrace.cc | 119 StackTrace::StackTrace(ThreadContext *_tc, const StaticInstPtr &inst) argument 122 trace(_tc, inst); 141 StackTrace::decodeStack(MachInst inst, int &disp) argument 147 StackTrace::decodeSave(MachInst inst, int ®, int &disp) argument
|
H A D | decoder.hh | 147 * @param inst Raw instruction data. 149 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
|
/gem5/src/cpu/o3/ |
H A D | iew.hh | 181 void wakeDependents(const DynInstPtr &inst); 186 void rescheduleMemInst(const DynInstPtr &inst); 189 void replayMemInst(const DynInstPtr &inst); 192 void blockMemInst(const DynInstPtr &inst); 198 void instToCommit(const DynInstPtr &inst); 236 void checkMisprediction(const DynInstPtr &inst); 242 void squashDueToBranch(const DynInstPtr &inst, ThreadID tid); 247 void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid); 301 void updateExeInstStats(const DynInstPtr &inst);
|
H A D | inst_queue.hh | 102 DynInstPtr inst; member in class:InstructionQueue::FUCompletion 209 void recordProducer(const DynInstPtr &inst) argument 210 { addToProducers(inst); } 213 void processFUCompletion(const DynInstPtr &inst, int fu_idx); 222 void scheduleNonSpec(const InstSeqNum &inst); 228 void commit(const InstSeqNum &inst, ThreadID tid = 0); 460 void addIfReady(const DynInstPtr &inst);
|
H A D | lsq_unit.hh | 99 DynInstPtr inst; member in class:LSQUnit::LSQEntry 109 : inst(nullptr), req(nullptr), _size(0), _valid(false) 115 inst = nullptr; 125 inst = nullptr; 135 set(const DynInstPtr& inst) argument 138 this->inst = inst; 150 const DynInstPtr& instruction() const { return inst; } 185 set(const DynInstPtr& inst) argument 187 LSQEntry::set(inst); 452 DynInstPtr inst; member in class:LSQUnit::WritebackEvent [all...] |
H A D | lsq_impl.hh | 250 LSQ<Impl>::executeLoad(const DynInstPtr &inst) argument 252 ThreadID tid = inst->threadNumber; 254 return thread[tid].executeLoad(inst); 259 LSQ<Impl>::executeStore(const DynInstPtr &inst) argument 261 ThreadID tid = inst->threadNumber; 263 return thread[tid].executeStore(inst); 344 // specifically inst->completeAcc) in completeDataAccess overwrites 688 LSQ<Impl>::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data, argument 698 ThreadID tid = cpu->contextToThread(inst->contextId()); 711 if (inst [all...] |
/gem5/src/arch/sparc/ |
H A D | utility.hh | 89 advancePC(PCState &pc, const StaticInstPtr &inst) argument 91 inst->advancePC(pc);
|
/gem5/src/arch/alpha/ |
H A D | faults.cc | 117 AlphaFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 141 ArithmeticFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 150 DtbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 163 MachInst machInst = inst->machInst; 179 ItbFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 191 ItbPageFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 210 NDtbMissFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 213 DtbFault::invoke(tc, inst);
|
H A D | ev5.hh | 105 inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; } argument 106 inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; } argument
|
/gem5/src/systemc/tlm_core/2/generic_payload/ |
H A D | phase.cc | 41 static tlm_phase_registry inst; local 42 return inst;
|
/gem5/src/cpu/ |
H A D | exetrace.cc | 72 Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) argument 106 if (inst->isMicroop()) { 119 outs << inst->disassemble(cur_pc, debugSymbolTable); 125 outs << Enums::OpClassStrings[inst->opClass()] << " : "; 178 inst->printFlags(outs, "|");
|
H A D | exetrace.hh | 57 void traceInst(const StaticInstPtr &inst, bool ran);
|
/gem5/src/arch/arm/tracers/ |
H A D | tarmac_parser.hh | 84 const StaticInstPtr inst; member in struct:Trace::TarmacParserRecord::TarmacParserRecordEvent 101 parent(_parent), thread(_thread), inst(_inst), pc(_pc), 132 static void printMismatchHeader(const StaticInstPtr inst, 154 * in one of {inst/reg/mem}_record.
|
/gem5/src/arch/power/ |
H A D | utility.hh | 76 advancePC(PCState &pc, const StaticInstPtr &inst) argument
|
/gem5/src/arch/mips/ |
H A D | faults.cc | 135 MipsFaultBase::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 147 ResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 164 SoftResetFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument 170 NonMaskableInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst) argument
|