1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Dam Sunwoo
38 *          Curtis Dunham
39 */
40
41#include "cpu/simple/probes/simpoint.hh"
42
43#include "base/output.hh"
44
45SimPoint::SimPoint(const SimPointParams *p)
46    : ProbeListenerObject(p),
47      intervalSize(p->interval),
48      intervalCount(0),
49      intervalDrift(0),
50      simpointStream(NULL),
51      currentBBV(0, 0),
52      currentBBVInstCount(0)
53{
54    simpointStream = simout.create(p->profile_file, false);
55    if (!simpointStream)
56        fatal("unable to open SimPoint profile_file");
57}
58
59SimPoint::~SimPoint()
60{
61    simout.close(simpointStream);
62}
63
64void
65SimPoint::init()
66{}
67
68void
69SimPoint::regProbeListeners()
70{
71    typedef ProbeListenerArg<SimPoint, std::pair<SimpleThread*,StaticInstPtr>>
72        SimPointListener;
73    listeners.push_back(new SimPointListener(this, "Commit",
74                                             &SimPoint::profile));
75}
76
77void
78SimPoint::profile(const std::pair<SimpleThread*, StaticInstPtr>& p)
79{
80    SimpleThread* thread = p.first;
81    const StaticInstPtr &inst = p.second;
82
83    if (inst->isMicroop() && !inst->isLastMicroop())
84        return;
85
86    if (!currentBBVInstCount)
87        currentBBV.first = thread->pcState().instAddr();
88
89    ++intervalCount;
90    ++currentBBVInstCount;
91
92    // If inst is control inst, assume end of basic block.
93    if (inst->isControl()) {
94        currentBBV.second = thread->pcState().instAddr();
95
96        auto map_itr = bbMap.find(currentBBV);
97        if (map_itr == bbMap.end()){
98            // If a new (previously unseen) basic block is found,
99            // add a new unique id, record num of insts and insert into bbMap.
100            BBInfo info;
101            info.id = bbMap.size() + 1;
102            info.insts = currentBBVInstCount;
103            info.count = currentBBVInstCount;
104            bbMap.insert(std::make_pair(currentBBV, info));
105        } else {
106            // If basic block is seen before, just increment the count by the
107            // number of insts in basic block.
108            BBInfo& info = map_itr->second;
109            info.count += currentBBVInstCount;
110        }
111        currentBBVInstCount = 0;
112
113        // Reached end of interval if the sum of the current inst count
114        // (intervalCount) and the excessive inst count from the previous
115        // interval (intervalDrift) is greater than/equal to the interval size.
116        if (intervalCount + intervalDrift >= intervalSize) {
117            // summarize interval and display BBV info
118            std::vector<std::pair<uint64_t, uint64_t> > counts;
119            for (auto map_itr = bbMap.begin(); map_itr != bbMap.end();
120                    ++map_itr) {
121                BBInfo& info = map_itr->second;
122                if (info.count != 0) {
123                    counts.push_back(std::make_pair(info.id, info.count));
124                    info.count = 0;
125                }
126            }
127            std::sort(counts.begin(), counts.end());
128
129            // Print output BBV info
130            *simpointStream->stream() << "T";
131            for (auto cnt_itr = counts.begin(); cnt_itr != counts.end();
132                    ++cnt_itr) {
133                *simpointStream->stream() << ":" << cnt_itr->first
134                                << ":" << cnt_itr->second << " ";
135            }
136            *simpointStream->stream() << "\n";
137
138            intervalDrift = (intervalCount + intervalDrift) - intervalSize;
139            intervalCount = 0;
140        }
141    }
142}
143
144/** SimPoint SimObject */
145SimPoint*
146SimPointParams::create()
147{
148    return new SimPoint(this);
149}
150