12SN/A/* 213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2017 ARM Limited 313759Sgiacomo.gabrielli@arm.com * All rights reserved 413759Sgiacomo.gabrielli@arm.com * 513759Sgiacomo.gabrielli@arm.com * The license below extends only to copyright in the software and shall 613759Sgiacomo.gabrielli@arm.com * not be construed as granting a license to any other intellectual 713759Sgiacomo.gabrielli@arm.com * property including but not limited to intellectual property relating 813759Sgiacomo.gabrielli@arm.com * to a hardware implementation of the functionality of the software 913759Sgiacomo.gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 1013759Sgiacomo.gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 1113759Sgiacomo.gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 1213759Sgiacomo.gabrielli@arm.com * modified or unmodified, in source code or in binary form. 1313759Sgiacomo.gabrielli@arm.com * 141762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272SN/A * 282SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Steve Reinhardt 412665Ssaidi@eecs.umich.edu * Lisa Hsu 422665Ssaidi@eecs.umich.edu * Nathan Binkert 432665Ssaidi@eecs.umich.edu * Steve Raasch 442SN/A */ 452SN/A 4611793Sbrandon.potter@amd.com#include "cpu/exetrace.hh" 4711793Sbrandon.potter@amd.com 482SN/A#include <iomanip> 492SN/A 507349SAli.Saidi@ARM.com#include "arch/isa_traits.hh" 517680Sgblack@eecs.umich.edu#include "arch/utility.hh" 5256SN/A#include "base/loader/symtab.hh" 538229Snate@binkert.org#include "config/the_isa.hh" 541717SN/A#include "cpu/base.hh" 5556SN/A#include "cpu/static_inst.hh" 564776Sgblack@eecs.umich.edu#include "cpu/thread_context.hh" 578232Snate@binkert.org#include "debug/ExecAll.hh" 584762Snate@binkert.org#include "enums/OpClass.hh" 593065Sgblack@eecs.umich.edu 602SN/Ausing namespace std; 612973Sgblack@eecs.umich.eduusing namespace TheISA; 622SN/A 633506Ssaidi@eecs.umich.edunamespace Trace { 644054Sbinkertn@umich.edu 654054Sbinkertn@umich.eduvoid 665866Sksewell@umich.eduExeTracerRecord::dumpTicks(ostream &outs) 675866Sksewell@umich.edu{ 685866Sksewell@umich.edu ccprintf(outs, "%7d: ", when); 695866Sksewell@umich.edu} 705866Sksewell@umich.edu 715866Sksewell@umich.eduvoid 7210417Sandreas.hansson@arm.comTrace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran) 734054Sbinkertn@umich.edu{ 744776Sgblack@eecs.umich.edu ostream &outs = Trace::output(); 754054Sbinkertn@umich.edu 768300Schander.sudanthi@arm.com if (!Debug::ExecUser || !Debug::ExecKernel) { 778300Schander.sudanthi@arm.com bool in_user_mode = TheISA::inUserMode(thread); 788300Schander.sudanthi@arm.com if (in_user_mode && !Debug::ExecUser) return; 798300Schander.sudanthi@arm.com if (!in_user_mode && !Debug::ExecKernel) return; 808300Schander.sudanthi@arm.com } 818300Schander.sudanthi@arm.com 828232Snate@binkert.org if (Debug::ExecTicks) 835866Sksewell@umich.edu dumpTicks(outs); 844054Sbinkertn@umich.edu 854776Sgblack@eecs.umich.edu outs << thread->getCpuPtr()->name() << " "; 864054Sbinkertn@umich.edu 878300Schander.sudanthi@arm.com if (Debug::ExecAsid) 888300Schander.sudanthi@arm.com outs << "A" << dec << TheISA::getExecutingAsid(thread) << " "; 898300Schander.sudanthi@arm.com 908232Snate@binkert.org if (Debug::ExecThread) 915715Shsul@eecs.umich.edu outs << "T" << thread->threadId() << " : "; 924776Sgblack@eecs.umich.edu 934776Sgblack@eecs.umich.edu std::string sym_str; 944776Sgblack@eecs.umich.edu Addr sym_addr; 957720Sgblack@eecs.umich.edu Addr cur_pc = pc.instAddr(); 969809Sumesh.b2006@gmail.com if (debugSymbolTable && Debug::ExecSymbol && 979809Sumesh.b2006@gmail.com (!FullSystem || !inUserMode(thread)) && 989809Sumesh.b2006@gmail.com debugSymbolTable->findNearestSymbol(cur_pc, sym_str, sym_addr)) { 997349SAli.Saidi@ARM.com if (cur_pc != sym_addr) 1007349SAli.Saidi@ARM.com sym_str += csprintf("+%d",cur_pc - sym_addr); 1015784Sgblack@eecs.umich.edu outs << "@" << sym_str; 1027720Sgblack@eecs.umich.edu } else { 1037349SAli.Saidi@ARM.com outs << "0x" << hex << cur_pc; 1044776Sgblack@eecs.umich.edu } 1054776Sgblack@eecs.umich.edu 1065784Sgblack@eecs.umich.edu if (inst->isMicroop()) { 1077720Sgblack@eecs.umich.edu outs << "." << setw(2) << dec << pc.microPC(); 1085784Sgblack@eecs.umich.edu } else { 1095784Sgblack@eecs.umich.edu outs << " "; 1105784Sgblack@eecs.umich.edu } 1115784Sgblack@eecs.umich.edu 1125784Sgblack@eecs.umich.edu outs << " : "; 1135784Sgblack@eecs.umich.edu 1144776Sgblack@eecs.umich.edu // 1154776Sgblack@eecs.umich.edu // Print decoded instruction 1164776Sgblack@eecs.umich.edu // 1174776Sgblack@eecs.umich.edu 1184776Sgblack@eecs.umich.edu outs << setw(26) << left; 1197349SAli.Saidi@ARM.com outs << inst->disassemble(cur_pc, debugSymbolTable); 1204776Sgblack@eecs.umich.edu 1215784Sgblack@eecs.umich.edu if (ran) { 1225784Sgblack@eecs.umich.edu outs << " : "; 1235784Sgblack@eecs.umich.edu 1248232Snate@binkert.org if (Debug::ExecOpClass) { 1255784Sgblack@eecs.umich.edu outs << Enums::OpClassStrings[inst->opClass()] << " : "; 1265784Sgblack@eecs.umich.edu } 1275784Sgblack@eecs.umich.edu 12810231Ssteve.reinhardt@amd.com if (Debug::ExecResult && !predicate) { 1297600Sminkyu.jeong@arm.com outs << "Predicated False"; 1307600Sminkyu.jeong@arm.com } 1317600Sminkyu.jeong@arm.com 1328232Snate@binkert.org if (Debug::ExecResult && data_status != DataInvalid) { 13313759Sgiacomo.gabrielli@arm.com switch (data_status) { 13413759Sgiacomo.gabrielli@arm.com case DataVec: 13513759Sgiacomo.gabrielli@arm.com { 13613759Sgiacomo.gabrielli@arm.com ccprintf(outs, " D=0x["); 13713759Sgiacomo.gabrielli@arm.com auto dv = data.as_vec->as<uint32_t>(); 13813759Sgiacomo.gabrielli@arm.com for (int i = TheISA::VecRegSizeBytes / 4 - 1; i >= 0; 13913759Sgiacomo.gabrielli@arm.com i--) { 14013759Sgiacomo.gabrielli@arm.com ccprintf(outs, "%08x", dv[i]); 14113759Sgiacomo.gabrielli@arm.com if (i != 0) { 14213759Sgiacomo.gabrielli@arm.com ccprintf(outs, "_"); 14313759Sgiacomo.gabrielli@arm.com } 14413759Sgiacomo.gabrielli@arm.com } 14513759Sgiacomo.gabrielli@arm.com ccprintf(outs, "]"); 14613759Sgiacomo.gabrielli@arm.com } 14713759Sgiacomo.gabrielli@arm.com break; 14813759Sgiacomo.gabrielli@arm.com case DataVecPred: 14913759Sgiacomo.gabrielli@arm.com { 15013759Sgiacomo.gabrielli@arm.com ccprintf(outs, " D=0b["); 15113759Sgiacomo.gabrielli@arm.com auto pv = data.as_pred->as<uint8_t>(); 15213759Sgiacomo.gabrielli@arm.com for (int i = TheISA::VecPredRegSizeBits - 1; i >= 0; i--) { 15313759Sgiacomo.gabrielli@arm.com ccprintf(outs, pv[i] ? "1" : "0"); 15413759Sgiacomo.gabrielli@arm.com if (i != 0 && i % 4 == 0) { 15513759Sgiacomo.gabrielli@arm.com ccprintf(outs, "_"); 15613759Sgiacomo.gabrielli@arm.com } 15713759Sgiacomo.gabrielli@arm.com } 15813759Sgiacomo.gabrielli@arm.com ccprintf(outs, "]"); 15913759Sgiacomo.gabrielli@arm.com } 16013759Sgiacomo.gabrielli@arm.com break; 16113759Sgiacomo.gabrielli@arm.com default: 16213759Sgiacomo.gabrielli@arm.com ccprintf(outs, " D=%#018x", data.as_int); 16313759Sgiacomo.gabrielli@arm.com break; 16413759Sgiacomo.gabrielli@arm.com } 1655784Sgblack@eecs.umich.edu } 1665784Sgblack@eecs.umich.edu 16710665SAli.Saidi@ARM.com if (Debug::ExecEffAddr && getMemValid()) 1685784Sgblack@eecs.umich.edu outs << " A=0x" << hex << addr; 1695784Sgblack@eecs.umich.edu 1708232Snate@binkert.org if (Debug::ExecFetchSeq && fetch_seq_valid) 1715784Sgblack@eecs.umich.edu outs << " FetchSeq=" << dec << fetch_seq; 1725784Sgblack@eecs.umich.edu 1738232Snate@binkert.org if (Debug::ExecCPSeq && cp_seq_valid) 1745784Sgblack@eecs.umich.edu outs << " CPSeq=" << dec << cp_seq; 17510383Smitch.hayenga@arm.com 17610383Smitch.hayenga@arm.com if (Debug::ExecFlags) { 17710383Smitch.hayenga@arm.com outs << " flags=("; 17810383Smitch.hayenga@arm.com inst->printFlags(outs, "|"); 17910383Smitch.hayenga@arm.com outs << ")"; 18010383Smitch.hayenga@arm.com } 1814776Sgblack@eecs.umich.edu } 1824776Sgblack@eecs.umich.edu 1834776Sgblack@eecs.umich.edu // 1844776Sgblack@eecs.umich.edu // End of line... 1854776Sgblack@eecs.umich.edu // 1864776Sgblack@eecs.umich.edu outs << endl; 1873506Ssaidi@eecs.umich.edu} 1883506Ssaidi@eecs.umich.edu 1895784Sgblack@eecs.umich.eduvoid 1905784Sgblack@eecs.umich.eduTrace::ExeTracerRecord::dump() 1915784Sgblack@eecs.umich.edu{ 1925784Sgblack@eecs.umich.edu /* 1935784Sgblack@eecs.umich.edu * The behavior this check tries to achieve is that if ExecMacro is on, 1945784Sgblack@eecs.umich.edu * the macroop will be printed. If it's on and microops are also on, it's 1955784Sgblack@eecs.umich.edu * printed before the microops start printing to give context. If the 1965784Sgblack@eecs.umich.edu * microops aren't printed, then it's printed only when the final microop 1975784Sgblack@eecs.umich.edu * finishes. Macroops then behave like regular instructions and don't 1985784Sgblack@eecs.umich.edu * complete/print when they fault. 1995784Sgblack@eecs.umich.edu */ 2008232Snate@binkert.org if (Debug::ExecMacro && staticInst->isMicroop() && 2018232Snate@binkert.org ((Debug::ExecMicro && 2028232Snate@binkert.org macroStaticInst && staticInst->isFirstMicroop()) || 2038232Snate@binkert.org (!Debug::ExecMicro && 2045791Srstrong@cs.ucsd.edu macroStaticInst && staticInst->isLastMicroop()))) { 2055784Sgblack@eecs.umich.edu traceInst(macroStaticInst, false); 2065784Sgblack@eecs.umich.edu } 2078232Snate@binkert.org if (Debug::ExecMicro || !staticInst->isMicroop()) { 2085784Sgblack@eecs.umich.edu traceInst(staticInst, true); 2095784Sgblack@eecs.umich.edu } 2105784Sgblack@eecs.umich.edu} 2115784Sgblack@eecs.umich.edu 2127811Ssteve.reinhardt@amd.com} // namespace Trace 2134776Sgblack@eecs.umich.edu 2142SN/A//////////////////////////////////////////////////////////////////////// 2152SN/A// 2164776Sgblack@eecs.umich.edu// ExeTracer Simulation Object 2172SN/A// 2184776Sgblack@eecs.umich.eduTrace::ExeTracer * 2194776Sgblack@eecs.umich.eduExeTracerParams::create() 2203748Sgblack@eecs.umich.edu{ 2215034Smilesck@eecs.umich.edu return new Trace::ExeTracer(this); 2228902Sandreas.hansson@arm.com} 223