misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

x86: Invalidating TLB entry on page fault

As per the x86 architecture specification, matching TLB entries need to be
invalidated on a page fault. For instance, after a page fault due to inadequate
protection bits on a TLB hit, the TLB entry needs to be invalidated. This
behavior is clearly specified in the x86 architecture manuals from both AMD and
Intel. This invalidation is missing currently in gem5, due to which linux
kernel versions 3.8 and up cannot be simulated efficiently. This is exposed by
a linux optimisation in commit e4a1cc56e4d728eb87072c71c07581524e5160b1, which
removes a tlb flush on updating page table entries in x86.

Testing: Linux kernel versions 3.8 onwards were booting very slowly in FS mode,
due to repeated page faults (~300000 before the first print statement in a
bash file). Ensured that page fault rate drops drastically and observed
reduction in boot time from order of hours to minutes for linux kernel v3.8
and v3.11

x86: change divide-by-zero fault to divide-error
Same exception is raised whether division with zero is performed or the
quotient is greater than the maximum value that the provided space can hold.
Divide-by-Zero is the AMD terminology, while Divide-Error is Intel's.

sim: Move the BaseTLB to src/arch/generic/

The TLB-related code is generally architecture dependent and should
live in the arch directory to signify that.

arch: Use const StaticInstPtr references where possible

This patch optimises the passing of StaticInstPtr by avoiding copying
the reference-counting pointer. This avoids first incrementing and
then decrementing the reference-counting pointer.

x86: Expose the interrupt vector in faults

This patch allows a hardware virtualized CPU to discover which interrupt
to deliver to the guest.

gcc: Clean-up of non-C++0x compliant code, first steps

This patch cleans up a number of minor issues aiming to get closer to
compliance with the C++0x standard as interpreted by gcc and clang
(compile with std=c++0x and -pedantic-errors). In particular, the
patch cleans up enums where the last item was succeded by a comma,
namespaces closed by a curcly brace followed by a semi-colon, and the
use of the GNU-extension typeof (replaced by templated functions). It
does not address variable-length arrays, zero-size arrays, anonymous
structs, range expressions in switch statements, and the use of long
long. The generated CPU code also has a large number of issues that
remain to be fixed, mainly related to overflows in implicit constant
conversion (due to shifts).

X86: Remove FULL_SYSTEM from the x86 faults.

Faults: Replace calls to genMachineCheckFault with M5PanicFault.

includes: sort all includes

X86: Implement genMachineCheckFault.

Even though this shouldn't ever be used, it might get called speculatively and
shouldn't panic.

X86: Make unrecognized instructions behave better in x86.

Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.

X86: Make the TLB fault instead of panic when something is unmapped in SE mode.

The fault object, if invoked, would then panic. This is a bit less direct, but
it means speculative execution won't panic the simulator.

copyright: Change HP copyright on x86 code to be more friendly

X86: Implement the STARTUP IPI.

X86: Implement the INIT IPI.

tlb: More fixing of unified TLB

build: fix compiler warnings in g++ 3.4

X86: Add a trace flag for tracing faults.

X86: Make the X86 TLB take advantage of delayed translations, and get rid of the fake TLB miss faults.

X86: Pass whether an access was a read/write/fetch so faults can behave accordingly.

X86: All x86 fault classes now attempt to do something useful.

X86: Make the fault classes handle error codes better.

X86: Keep track of the vector for all exceptions/faults.

X86: Panic when an unimplemented fault is invoked, rather than spinning forever

X86: Make the x86 interrupt fault kick off the interrupt microcode.

X86: Make the local APIC process interrupts and send them to the CPU.

X86: Make the local APIC handle interrupt messages from the IO APIC.

X86: Make the bases for x86 fault class public.

X86: Work on the page table walker, TLB, and related faults.

X86: Make faults maintain an error code which gets pushed on the stack.

X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.

X86: Add classes for the actual x86 faults.

Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.

Make the "name" function const.

Fix up the base x86 fault object and create a fault to be generated by unimplemented instructions in their microcode. This is useful if certain variations of an instruction are implemented, but, for instance, it's memory based versions aren't.

Added fault generation functions. I would still like to see these go away. The page table fault should be moved into sim/faults.hh because it's a "fake" m5 fault for se mode and shouldn't vary between architectures.

Added a missing include.

Stub x86 Fault class which just panics.

Add build hooks for x86.