faults.hh revision 10687:276da6265ab8
1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_X86_FAULTS_HH__ 41#define __ARCH_X86_FAULTS_HH__ 42 43#include <string> 44 45#include "arch/generic/tlb.hh" 46#include "base/bitunion.hh" 47#include "base/misc.hh" 48#include "sim/faults.hh" 49 50namespace X86ISA 51{ 52 // Base class for all x86 "faults" where faults is in the m5 sense 53 class X86FaultBase : public FaultBase 54 { 55 protected: 56 const char * faultName; 57 const char * mnem; 58 uint8_t vector; 59 uint64_t errorCode; 60 61 X86FaultBase(const char * _faultName, const char * _mnem, 62 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1) 63 : faultName(_faultName), mnem(_mnem), 64 vector(_vector), errorCode(_errorCode) 65 { 66 } 67 68 const char * name() const 69 { 70 return faultName; 71 } 72 73 virtual bool isBenign() 74 { 75 return true; 76 } 77 78 virtual const char * mnemonic() const 79 { 80 return mnem; 81 } 82 83 virtual bool isSoft() 84 { 85 return false; 86 } 87 88 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 89 StaticInst::nullStaticInstPtr); 90 91 virtual std::string describe() const; 92 93 public: 94 /** 95 * Get the vector of an interrupt. 96 * 97 * @return interrupt vector number. 98 */ 99 virtual uint8_t getVector() const { return vector; } 100 }; 101 102 // Base class for x86 faults which behave as if the underlying instruction 103 // didn't happen. 104 class X86Fault : public X86FaultBase 105 { 106 protected: 107 X86Fault(const char * name, const char * mnem, 108 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 109 : X86FaultBase(name, mnem, vector, _errorCode) 110 {} 111 }; 112 113 // Base class for x86 traps which behave as if the underlying instruction 114 // completed. 115 class X86Trap : public X86FaultBase 116 { 117 protected: 118 X86Trap(const char * name, const char * mnem, 119 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 120 : X86FaultBase(name, mnem, vector, _errorCode) 121 {} 122 123 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 124 StaticInst::nullStaticInstPtr); 125 }; 126 127 // Base class for x86 aborts which seem to be catastrophic failures. 128 class X86Abort : public X86FaultBase 129 { 130 protected: 131 X86Abort(const char * name, const char * mnem, 132 const uint8_t vector, uint64_t _errorCode = (uint64_t)-1) 133 : X86FaultBase(name, mnem, vector, _errorCode) 134 {} 135 136 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 137 StaticInst::nullStaticInstPtr); 138 }; 139 140 // Base class for x86 interrupts. 141 class X86Interrupt : public X86FaultBase 142 { 143 protected: 144 X86Interrupt(const char * name, const char * mnem, 145 const uint8_t _vector, uint64_t _errorCode = (uint64_t)-1) 146 : X86FaultBase(name, mnem, _vector, _errorCode) 147 {} 148 }; 149 150 class UnimpInstFault : public FaultBase 151 { 152 public: 153 const char * name() const 154 { 155 return "unimplemented_micro"; 156 } 157 158 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 159 StaticInst::nullStaticInstPtr) 160 { 161 panic("Unimplemented instruction!"); 162 } 163 }; 164 165 // Below is a summary of the interrupt/exception information in the 166 // architecture manuals. 167 168 // Class | Type | vector | Cause | mnem 169 //------------------------------------------------------------------------ 170 //Contrib Fault 0 Divide-by-Zero-Error #DE 171 //Benign Either 1 Debug #DB 172 //Benign Interrupt 2 Non-Maskable-Interrupt #NMI 173 //Benign Trap 3 Breakpoint #BP 174 //Benign Trap 4 Overflow #OF 175 //Benign Fault 5 Bound-Range #BR 176 //Benign Fault 6 Invalid-Opcode #UD 177 //Benign Fault 7 Device-Not-Available #NM 178 //Benign Abort 8 Double-Fault #DF 179 // 9 Coprocessor-Segment-Overrun 180 //Contrib Fault 10 Invalid-TSS #TS 181 //Contrib Fault 11 Segment-Not-Present #NP 182 //Contrib Fault 12 Stack #SS 183 //Contrib Fault 13 General-Protection #GP 184 //Either Fault 14 Page-Fault #PF 185 // 15 Reserved 186 //Benign Fault 16 x87 Floating-Point Exception Pending #MF 187 //Benign Fault 17 Alignment-Check #AC 188 //Benign Abort 18 Machine-Check #MC 189 //Benign Fault 19 SIMD Floating-Point #XF 190 // 20-29 Reserved 191 //Contrib ? 30 Security Exception #SX 192 // 31 Reserved 193 //Benign Interrupt 0-255 External Interrupts #INTR 194 //Benign Interrupt 0-255 Software Interrupts INTn 195 196 class DivideByZero : public X86Fault 197 { 198 public: 199 DivideByZero() : 200 X86Fault("Divide-by-Zero-Error", "#DE", 0) 201 {} 202 }; 203 204 class DebugException : public X86FaultBase 205 { 206 public: 207 DebugException() : 208 X86FaultBase("Debug", "#DB", 1) 209 {} 210 }; 211 212 class NonMaskableInterrupt : public X86Interrupt 213 { 214 public: 215 NonMaskableInterrupt(uint8_t _vector) : 216 X86Interrupt("Non Maskable Interrupt", "#NMI", 2, _vector) 217 {} 218 }; 219 220 class Breakpoint : public X86Trap 221 { 222 public: 223 Breakpoint() : 224 X86Trap("Breakpoint", "#BP", 3) 225 {} 226 }; 227 228 class OverflowTrap : public X86Trap 229 { 230 public: 231 OverflowTrap() : 232 X86Trap("Overflow", "#OF", 4) 233 {} 234 }; 235 236 class BoundRange : public X86Fault 237 { 238 public: 239 BoundRange() : 240 X86Fault("Bound-Range", "#BR", 5) 241 {} 242 }; 243 244 class InvalidOpcode : public X86Fault 245 { 246 public: 247 InvalidOpcode() : 248 X86Fault("Invalid-Opcode", "#UD", 6) 249 {} 250 251 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 252 StaticInst::nullStaticInstPtr); 253 }; 254 255 class DeviceNotAvailable : public X86Fault 256 { 257 public: 258 DeviceNotAvailable() : 259 X86Fault("Device-Not-Available", "#NM", 7) 260 {} 261 }; 262 263 class DoubleFault : public X86Abort 264 { 265 public: 266 DoubleFault() : 267 X86Abort("Double-Fault", "#DF", 8, 0) 268 {} 269 }; 270 271 class InvalidTSS : public X86Fault 272 { 273 public: 274 InvalidTSS(uint32_t _errorCode) : 275 X86Fault("Invalid-TSS", "#TS", 10, _errorCode) 276 {} 277 }; 278 279 class SegmentNotPresent : public X86Fault 280 { 281 public: 282 SegmentNotPresent(uint32_t _errorCode) : 283 X86Fault("Segment-Not-Present", "#NP", 11, _errorCode) 284 {} 285 }; 286 287 class StackFault : public X86Fault 288 { 289 public: 290 StackFault(uint32_t _errorCode) : 291 X86Fault("Stack", "#SS", 12, _errorCode) 292 {} 293 }; 294 295 class GeneralProtection : public X86Fault 296 { 297 public: 298 GeneralProtection(uint32_t _errorCode) : 299 X86Fault("General-Protection", "#GP", 13, _errorCode) 300 {} 301 }; 302 303 class PageFault : public X86Fault 304 { 305 protected: 306 BitUnion32(PageFaultErrorCode) 307 Bitfield<0> present; 308 Bitfield<1> write; 309 Bitfield<2> user; 310 Bitfield<3> reserved; 311 Bitfield<4> fetch; 312 EndBitUnion(PageFaultErrorCode) 313 314 Addr addr; 315 316 public: 317 PageFault(Addr _addr, uint32_t _errorCode) : 318 X86Fault("Page-Fault", "#PF", 14, _errorCode), addr(_addr) 319 {} 320 321 PageFault(Addr _addr, bool present, BaseTLB::Mode mode, 322 bool user, bool reserved) : 323 X86Fault("Page-Fault", "#PF", 14, 0), addr(_addr) 324 { 325 PageFaultErrorCode code = 0; 326 code.present = present; 327 code.write = (mode == BaseTLB::Write); 328 code.user = user; 329 code.reserved = reserved; 330 code.fetch = (mode == BaseTLB::Execute); 331 errorCode = code; 332 } 333 334 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 335 StaticInst::nullStaticInstPtr); 336 337 virtual std::string describe() const; 338 }; 339 340 class X87FpExceptionPending : public X86Fault 341 { 342 public: 343 X87FpExceptionPending() : 344 X86Fault("x87 Floating-Point Exception Pending", "#MF", 16) 345 {} 346 }; 347 348 class AlignmentCheck : public X86Fault 349 { 350 public: 351 AlignmentCheck() : 352 X86Fault("Alignment-Check", "#AC", 17, 0) 353 {} 354 }; 355 356 class MachineCheck : public X86Abort 357 { 358 public: 359 MachineCheck() : 360 X86Abort("Machine-Check", "#MC", 18) 361 {} 362 }; 363 364 class SIMDFloatingPointFault : public X86Fault 365 { 366 public: 367 SIMDFloatingPointFault() : 368 X86Fault("SIMD Floating-Point", "#XF", 19) 369 {} 370 }; 371 372 class SecurityException : public X86FaultBase 373 { 374 public: 375 SecurityException() : 376 X86FaultBase("Security Exception", "#SX", 30) 377 {} 378 }; 379 380 class ExternalInterrupt : public X86Interrupt 381 { 382 public: 383 ExternalInterrupt(uint8_t _vector) : 384 X86Interrupt("External Interrupt", "#INTR", _vector) 385 {} 386 }; 387 388 class SystemManagementInterrupt : public X86Interrupt 389 { 390 public: 391 SystemManagementInterrupt() : 392 X86Interrupt("System Management Interrupt", "#SMI", 0) 393 {} 394 }; 395 396 class InitInterrupt : public X86Interrupt 397 { 398 public: 399 InitInterrupt(uint8_t _vector) : 400 X86Interrupt("INIT Interrupt", "#INIT", _vector) 401 {} 402 403 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 404 StaticInst::nullStaticInstPtr); 405 }; 406 407 class StartupInterrupt : public X86Interrupt 408 { 409 public: 410 StartupInterrupt(uint8_t _vector) : 411 X86Interrupt("Startup Interrupt", "#SIPI", _vector) 412 {} 413 414 void invoke(ThreadContext * tc, const StaticInstPtr &inst = 415 StaticInst::nullStaticInstPtr); 416 }; 417 418 class SoftwareInterrupt : public X86Interrupt 419 { 420 public: 421 SoftwareInterrupt(uint8_t _vector) : 422 X86Interrupt("Software Interrupt", "#INTR", _vector) 423 {} 424 425 bool isSoft() 426 { 427 return true; 428 } 429 }; 430} 431 432#endif // __ARCH_X86_FAULTS_HH__ 433