112855Sgabeblack@google.com/* 212855Sgabeblack@google.com * Copyright (c) 2013-2014 ARM Limited 312855Sgabeblack@google.com * All rights reserved 412855Sgabeblack@google.com * 512855Sgabeblack@google.com * The license below extends only to copyright in the software and shall 612855Sgabeblack@google.com * not be construed as granting a license to any other intellectual 712855Sgabeblack@google.com * property including but not limited to intellectual property relating 812855Sgabeblack@google.com * to a hardware implementation of the functionality of the software 912855Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1012855Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1112855Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1212855Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1312855Sgabeblack@google.com * 1412855Sgabeblack@google.com * Copyright (c) 2012 Google 1512855Sgabeblack@google.com * All rights reserved. 1612855Sgabeblack@google.com * 1712855Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1812855Sgabeblack@google.com * modification, are permitted provided that the following conditions are 1912855Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2012855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2112855Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2212855Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2312855Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2412855Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2512855Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2612855Sgabeblack@google.com * this software without specific prior written permission. 2712855Sgabeblack@google.com * 2812855Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912855Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012855Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112855Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212855Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312855Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412855Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512855Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612855Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3712855Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3812855Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3912855Sgabeblack@google.com * 4012855Sgabeblack@google.com * Authors: Gabe Black 4112855Sgabeblack@google.com */ 4212855Sgabeblack@google.com 4312855Sgabeblack@google.com#ifndef __ARCH_ARM_DECODER_HH__ 4412855Sgabeblack@google.com#define __ARCH_ARM_DECODER_HH__ 4512855Sgabeblack@google.com 4612855Sgabeblack@google.com#include <cassert> 4712855Sgabeblack@google.com 4812855Sgabeblack@google.com#include "arch/arm/miscregs.hh" 4912855Sgabeblack@google.com#include "arch/arm/types.hh" 5012855Sgabeblack@google.com#include "arch/generic/decode_cache.hh" 5112855Sgabeblack@google.com#include "base/types.hh" 5212855Sgabeblack@google.com#include "cpu/static_inst.hh" 5312855Sgabeblack@google.com#include "enums/DecoderFlavour.hh" 5412855Sgabeblack@google.com 5512855Sgabeblack@google.comnamespace ArmISA 5612855Sgabeblack@google.com{ 5712855Sgabeblack@google.com 5812855Sgabeblack@google.comclass ISA; 5912855Sgabeblack@google.comclass Decoder 6012855Sgabeblack@google.com{ 6112855Sgabeblack@google.com protected: 6212855Sgabeblack@google.com //The extended machine instruction being generated 6312855Sgabeblack@google.com ExtMachInst emi; 6412855Sgabeblack@google.com MachInst data; 6512855Sgabeblack@google.com bool bigThumb; 6612855Sgabeblack@google.com bool instDone; 6712855Sgabeblack@google.com bool outOfBytes; 6812855Sgabeblack@google.com int offset; 6912855Sgabeblack@google.com bool foundIt; 7012855Sgabeblack@google.com ITSTATE itBits; 7112855Sgabeblack@google.com 7212855Sgabeblack@google.com int fpscrLen; 7312855Sgabeblack@google.com int fpscrStride; 7412855Sgabeblack@google.com 7512855Sgabeblack@google.com /** 7612855Sgabeblack@google.com * SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN 7712855Sgabeblack@google.com * bitfields. 7812855Sgabeblack@google.com */ 7912855Sgabeblack@google.com int sveLen; 8012855Sgabeblack@google.com 8112855Sgabeblack@google.com Enums::DecoderFlavour decoderFlavour; 8212855Sgabeblack@google.com 8312855Sgabeblack@google.com /// A cache of decoded instruction objects. 8412855Sgabeblack@google.com static GenericISA::BasicDecodeCache defaultCache; 8512855Sgabeblack@google.com 8612855Sgabeblack@google.com /** 8712855Sgabeblack@google.com * Pre-decode an instruction from the current state of the 8812855Sgabeblack@google.com * decoder. 8912855Sgabeblack@google.com */ 9012855Sgabeblack@google.com void process(); 9112855Sgabeblack@google.com 9212855Sgabeblack@google.com /** 93 * Consume bytes by moving the offset into the data word and 94 * sanity check the results. 95 */ 96 void consumeBytes(int numBytes); 97 98 public: // Decoder API 99 Decoder(ISA* isa = nullptr); 100 101 /** Reset the decoders internal state. */ 102 void reset(); 103 104 /** 105 * Can the decoder accept more data? 106 * 107 * A CPU model uses this method to determine if the decoder can 108 * accept more data. Note that an instruction can be ready (see 109 * instReady() even if this method returns true. 110 */ 111 bool needMoreBytes() const { return outOfBytes; } 112 113 /** 114 * Is an instruction ready to be decoded? 115 * 116 * CPU models call this method to determine if decode() will 117 * return a new instruction on the next call. It typically only 118 * returns false if the decoder hasn't received enough data to 119 * decode a full instruction. 120 */ 121 bool instReady() const { return instDone; } 122 123 /** 124 * Feed data to the decoder. 125 * 126 * A CPU model uses this interface to load instruction data into 127 * the decoder. Once enough data has been loaded (check with 128 * instReady()), a decoded instruction can be retrieved using 129 * decode(ArmISA::PCState). 130 * 131 * This method is intended to support both fixed-length and 132 * variable-length instructions. Instruction data is fetch in 133 * MachInst blocks (which correspond to the size of a typical 134 * insturction). The method might need to be called multiple times 135 * if the instruction spans multiple blocks, in that case 136 * needMoreBytes() will return true and instReady() will return 137 * false. 138 * 139 * The fetchPC parameter is used to indicate where in memory the 140 * instruction was fetched from. This is should be the same 141 * address as the pc. If fetching multiple blocks, it indicates 142 * where subsequent blocks are fetched from (pc + n * 143 * sizeof(MachInst)). 144 * 145 * @param pc Instruction pointer that we are decoding. 146 * @param fetchPC The address this chunk was fetched from. 147 * @param inst Raw instruction data. 148 */ 149 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); 150 151 /** 152 * Decode an instruction or fetch it from the code cache. 153 * 154 * This method decodes the currently pending pre-decoded 155 * instruction. Data must be fed to the decoder using moreBytes() 156 * until instReady() is true before calling this method. 157 * 158 * @param pc Instruction pointer that we are decoding. 159 * @return A pointer to a static instruction or NULL if the 160 * decoder isn't ready (see instReady()). 161 */ 162 StaticInstPtr decode(ArmISA::PCState &pc); 163 164 /** 165 * Decode a pre-decoded machine instruction. 166 * 167 * @warn This method takes a pre-decoded instruction as its 168 * argument. It should typically not be called directly. 169 * 170 * @param mach_inst A pre-decoded instruction 171 * @retval A pointer to the corresponding StaticInst object. 172 */ 173 StaticInstPtr decode(ExtMachInst mach_inst, Addr addr) 174 { 175 return defaultCache.decode(this, mach_inst, addr); 176 } 177 178 /** 179 * Decode a machine instruction without calling the cache. 180 * 181 * @note The implementation of this method is generated by the ISA 182 * parser script. 183 * 184 * @warn This method takes a pre-decoded instruction as its 185 * argument. It should typically not be called directly. 186 * 187 * @param mach_inst The binary instruction to decode. 188 * @retval A pointer to the corresponding StaticInst object. 189 */ 190 StaticInstPtr decodeInst(ExtMachInst mach_inst); 191 192 /** 193 * Take over the state from an old decoder when switching CPUs. 194 * 195 * @param old Decoder used in old CPU 196 */ 197 void takeOverFrom(Decoder *old) {} 198 199 200 public: // ARM-specific decoder state manipulation 201 void setContext(FPSCR fpscr) 202 { 203 fpscrLen = fpscr.len; 204 fpscrStride = fpscr.stride; 205 } 206 207 void setSveLen(uint8_t len) 208 { 209 sveLen = len; 210 } 211}; 212 213} // namespace ArmISA 214 215#endif // __ARCH_ARM_DECODER_HH__ 216