11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2011-2012, 2014 ARM Limited 39920Syasuko.eckert@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47944SGiacomo.Gabrielli@arm.com * All rights reserved. 57944SGiacomo.Gabrielli@arm.com * 67944SGiacomo.Gabrielli@arm.com * The license below extends only to copyright in the software and shall 77944SGiacomo.Gabrielli@arm.com * not be construed as granting a license to any other intellectual 87944SGiacomo.Gabrielli@arm.com * property including but not limited to intellectual property relating 97944SGiacomo.Gabrielli@arm.com * to a hardware implementation of the functionality of the software 107944SGiacomo.Gabrielli@arm.com * licensed hereunder. You may use the software subject to the license 117944SGiacomo.Gabrielli@arm.com * terms below provided that you ensure that this notice is replicated 127944SGiacomo.Gabrielli@arm.com * unmodified and in its entirety in all distributions of the software, 137944SGiacomo.Gabrielli@arm.com * modified or unmodified, in source code or in binary form. 147944SGiacomo.Gabrielli@arm.com * 152326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 161689SN/A * All rights reserved. 171689SN/A * 181689SN/A * Redistribution and use in source and binary forms, with or without 191689SN/A * modification, are permitted provided that the following conditions are 201689SN/A * met: redistributions of source code must retain the above copyright 211689SN/A * notice, this list of conditions and the following disclaimer; 221689SN/A * redistributions in binary form must reproduce the above copyright 231689SN/A * notice, this list of conditions and the following disclaimer in the 241689SN/A * documentation and/or other materials provided with the distribution; 251689SN/A * neither the name of the copyright holders nor the names of its 261689SN/A * contributors may be used to endorse or promote products derived from 271689SN/A * this software without specific prior written permission. 281689SN/A * 291689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 402665Ssaidi@eecs.umich.edu * 412665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 421689SN/A */ 431689SN/A 442292SN/A#ifndef __CPU_O3_INST_QUEUE_HH__ 452292SN/A#define __CPU_O3_INST_QUEUE_HH__ 461060SN/A 471060SN/A#include <list> 481061SN/A#include <map> 491060SN/A#include <queue> 501061SN/A#include <vector> 511060SN/A 521062SN/A#include "base/statistics.hh" 538229Snate@binkert.org#include "base/types.hh" 548229Snate@binkert.org#include "cpu/o3/dep_graph.hh" 558229Snate@binkert.org#include "cpu/inst_seq.hh" 568229Snate@binkert.org#include "cpu/op_class.hh" 577813Ssteve.reinhardt@amd.com#include "cpu/timebuf.hh" 5813561Snikos.nikoleris@arm.com#include "enums/SMTQueuePolicy.hh" 595529Snate@binkert.org#include "sim/eventq.hh" 601060SN/A 618737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 622292SN/Aclass FUPool; 632292SN/Aclass MemInterface; 642292SN/A 651060SN/A/** 661689SN/A * A standard instruction queue class. It holds ready instructions, in 671689SN/A * order, in seperate priority queues to facilitate the scheduling of 681689SN/A * instructions. The IQ uses a separate linked list to track dependencies. 691689SN/A * Similar to the rename map and the free list, it expects that 701060SN/A * floating point registers have their indices start after the integer 711060SN/A * registers (ie with 96 int and 96 fp registers, regs 0-95 are integer 721060SN/A * and 96-191 are fp). This remains true even for both logical and 732292SN/A * physical register indices. The IQ depends on the memory dependence unit to 742292SN/A * track when memory operations are ready in terms of ordering; register 752292SN/A * dependencies are tracked normally. Right now the IQ also handles the 762292SN/A * execution timing; this is mainly to allow back-to-back scheduling without 772292SN/A * requiring IEW to be able to peek into the IQ. At the end of the execution 782292SN/A * latency, the instruction is put into the queue to execute, where it will 792292SN/A * have the execute() function called on it. 802292SN/A * @todo: Make IQ able to handle multiple FU pools. 811060SN/A */ 821061SN/Atemplate <class Impl> 831060SN/Aclass InstructionQueue 841060SN/A{ 851060SN/A public: 861060SN/A //Typedefs from the Impl. 872733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 881061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 891060SN/A 902292SN/A typedef typename Impl::CPUPol::IEW IEW; 911061SN/A typedef typename Impl::CPUPol::MemDepUnit MemDepUnit; 921061SN/A typedef typename Impl::CPUPol::IssueStruct IssueStruct; 931061SN/A typedef typename Impl::CPUPol::TimeStruct TimeStruct; 941060SN/A 952292SN/A // Typedef of iterator through the list of instructions. 961061SN/A typedef typename std::list<DynInstPtr>::iterator ListIt; 971060SN/A 982292SN/A /** FU completion event class. */ 992292SN/A class FUCompletion : public Event { 1002292SN/A private: 1012292SN/A /** Executing instruction. */ 1022292SN/A DynInstPtr inst; 1032292SN/A 1042292SN/A /** Index of the FU used for executing. */ 1052292SN/A int fuIdx; 1062292SN/A 1072292SN/A /** Pointer back to the instruction queue. */ 1082292SN/A InstructionQueue<Impl> *iqPtr; 1092292SN/A 1102348SN/A /** Should the FU be added to the list to be freed upon 1112348SN/A * completing this event. 1122348SN/A */ 1132326SN/A bool freeFU; 1142326SN/A 1152292SN/A public: 1162292SN/A /** Construct a FU completion event. */ 11713429Srekai.gonzalezalberquilla@arm.com FUCompletion(const DynInstPtr &_inst, int fu_idx, 1182292SN/A InstructionQueue<Impl> *iq_ptr); 1192292SN/A 1202292SN/A virtual void process(); 1215336Shines@cs.fsu.edu virtual const char *description() const; 1222326SN/A void setFreeFU() { freeFU = true; } 1231060SN/A }; 1241060SN/A 1252292SN/A /** Constructs an IQ. */ 1265529Snate@binkert.org InstructionQueue(O3CPU *cpu_ptr, IEW *iew_ptr, DerivO3CPUParams *params); 1271061SN/A 1282292SN/A /** Destructs the IQ. */ 1292292SN/A ~InstructionQueue(); 1301061SN/A 1312292SN/A /** Returns the name of the IQ. */ 1322292SN/A std::string name() const; 1331060SN/A 1342292SN/A /** Registers statistics. */ 1351062SN/A void regStats(); 1361062SN/A 1372348SN/A /** Resets all instruction queue state. */ 1382307SN/A void resetState(); 1391060SN/A 1402292SN/A /** Sets active threads list. */ 1416221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1422292SN/A 1432292SN/A /** Sets the timer buffer between issue and execute. */ 1441060SN/A void setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2eQueue); 1451060SN/A 1462292SN/A /** Sets the global time buffer. */ 1471060SN/A void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1481060SN/A 14910510Smitch.hayenga@arm.com /** Determine if we are drained. */ 15010510Smitch.hayenga@arm.com bool isDrained() const; 15110510Smitch.hayenga@arm.com 1529444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1539444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1542307SN/A 1552348SN/A /** Takes over execution from another CPU's thread. */ 1562307SN/A void takeOverFrom(); 1572307SN/A 1582292SN/A /** Number of entries needed for given amount of threads. */ 1596221Snate@binkert.org int entryAmount(ThreadID num_threads); 1602292SN/A 1612292SN/A /** Resets max entries for all threads. */ 1622292SN/A void resetEntries(); 1632292SN/A 1642292SN/A /** Returns total number of free entries. */ 1651060SN/A unsigned numFreeEntries(); 1661060SN/A 1672292SN/A /** Returns number of free entries for a thread. */ 1686221Snate@binkert.org unsigned numFreeEntries(ThreadID tid); 1692292SN/A 1702292SN/A /** Returns whether or not the IQ is full. */ 1711060SN/A bool isFull(); 1721060SN/A 1732292SN/A /** Returns whether or not the IQ is full for a specific thread. */ 1746221Snate@binkert.org bool isFull(ThreadID tid); 1752292SN/A 1762292SN/A /** Returns if there are any ready instructions in the IQ. */ 1772292SN/A bool hasReadyInsts(); 1782292SN/A 1792292SN/A /** Inserts a new instruction into the IQ. */ 18013429Srekai.gonzalezalberquilla@arm.com void insert(const DynInstPtr &new_inst); 1811060SN/A 1822292SN/A /** Inserts a new, non-speculative instruction into the IQ. */ 18313429Srekai.gonzalezalberquilla@arm.com void insertNonSpec(const DynInstPtr &new_inst); 1841061SN/A 1852292SN/A /** Inserts a memory or write barrier into the IQ to make sure 1862292SN/A * loads and stores are ordered properly. 1872292SN/A */ 18813429Srekai.gonzalezalberquilla@arm.com void insertBarrier(const DynInstPtr &barr_inst); 1891060SN/A 1902348SN/A /** Returns the oldest scheduled instruction, and removes it from 1912348SN/A * the list of instructions waiting to execute. 1922348SN/A */ 1932333SN/A DynInstPtr getInstToExecute(); 1942333SN/A 19510333Smitch.hayenga@arm.com /** Gets a memory instruction that was referred due to a delayed DTB 19610333Smitch.hayenga@arm.com * translation if it is now ready to execute. NULL if none available. 1977944SGiacomo.Gabrielli@arm.com */ 1987944SGiacomo.Gabrielli@arm.com DynInstPtr getDeferredMemInstToExecute(); 1997944SGiacomo.Gabrielli@arm.com 20010333Smitch.hayenga@arm.com /** Gets a memory instruction that was blocked on the cache. NULL if none 20110333Smitch.hayenga@arm.com * available. 20210333Smitch.hayenga@arm.com */ 20310333Smitch.hayenga@arm.com DynInstPtr getBlockedMemInstToExecute(); 20410333Smitch.hayenga@arm.com 2052292SN/A /** 2062326SN/A * Records the instruction as the producer of a register without 2072326SN/A * adding it to the rest of the IQ. 2082292SN/A */ 20913429Srekai.gonzalezalberquilla@arm.com void recordProducer(const DynInstPtr &inst) 2102326SN/A { addToProducers(inst); } 2111755SN/A 2122292SN/A /** Process FU completion event. */ 21313429Srekai.gonzalezalberquilla@arm.com void processFUCompletion(const DynInstPtr &inst, int fu_idx); 2142292SN/A 2152292SN/A /** 2162292SN/A * Schedules ready instructions, adding the ready ones (oldest first) to 2172292SN/A * the queue to execute. 2182292SN/A */ 2191060SN/A void scheduleReadyInsts(); 2201060SN/A 2212292SN/A /** Schedules a single specific non-speculative instruction. */ 2221061SN/A void scheduleNonSpec(const InstSeqNum &inst); 2231061SN/A 2242292SN/A /** 2252292SN/A * Commits all instructions up to and including the given sequence number, 2262292SN/A * for a specific thread. 2272292SN/A */ 2286221Snate@binkert.org void commit(const InstSeqNum &inst, ThreadID tid = 0); 2291061SN/A 2302292SN/A /** Wakes all dependents of a completed instruction. */ 23113429Srekai.gonzalezalberquilla@arm.com int wakeDependents(const DynInstPtr &completed_inst); 2321755SN/A 2332292SN/A /** Adds a ready memory instruction to the ready list. */ 23413429Srekai.gonzalezalberquilla@arm.com void addReadyMemInst(const DynInstPtr &ready_inst); 2352292SN/A 2362292SN/A /** 2372292SN/A * Reschedules a memory instruction. It will be ready to issue once 2382292SN/A * replayMemInst() is called. 2392292SN/A */ 24013429Srekai.gonzalezalberquilla@arm.com void rescheduleMemInst(const DynInstPtr &resched_inst); 2412292SN/A 2422292SN/A /** Replays a memory instruction. It must be rescheduled first. */ 24313429Srekai.gonzalezalberquilla@arm.com void replayMemInst(const DynInstPtr &replay_inst); 2442292SN/A 2452292SN/A /** Completes a memory operation. */ 24613429Srekai.gonzalezalberquilla@arm.com void completeMemInst(const DynInstPtr &completed_inst); 2472292SN/A 2487944SGiacomo.Gabrielli@arm.com /** 2497944SGiacomo.Gabrielli@arm.com * Defers a memory instruction when its DTB translation incurs a hw 2507944SGiacomo.Gabrielli@arm.com * page table walk. 2517944SGiacomo.Gabrielli@arm.com */ 25213429Srekai.gonzalezalberquilla@arm.com void deferMemInst(const DynInstPtr &deferred_inst); 2537944SGiacomo.Gabrielli@arm.com 25410333Smitch.hayenga@arm.com /** Defers a memory instruction when it is cache blocked. */ 25513429Srekai.gonzalezalberquilla@arm.com void blockMemInst(const DynInstPtr &blocked_inst); 25610333Smitch.hayenga@arm.com 25710333Smitch.hayenga@arm.com /** Notify instruction queue that a previous blockage has resolved */ 25810333Smitch.hayenga@arm.com void cacheUnblocked(); 25910333Smitch.hayenga@arm.com 2602292SN/A /** Indicates an ordering violation between a store and a load. */ 26113429Srekai.gonzalezalberquilla@arm.com void violation(const DynInstPtr &store, const DynInstPtr &faulting_load); 2621061SN/A 2632292SN/A /** 2642292SN/A * Squashes instructions for a thread. Squashing information is obtained 2652292SN/A * from the time buffer. 2662292SN/A */ 2676221Snate@binkert.org void squash(ThreadID tid); 2681060SN/A 2692292SN/A /** Returns the number of used entries for a thread. */ 2706221Snate@binkert.org unsigned getCount(ThreadID tid) { return count[tid]; }; 2711060SN/A 2722292SN/A /** Debug function to print all instructions. */ 2732292SN/A void printInsts(); 2741060SN/A 2751060SN/A private: 2762292SN/A /** Does the actual squashing. */ 2776221Snate@binkert.org void doSquash(ThreadID tid); 2782292SN/A 2792292SN/A ///////////////////////// 2802292SN/A // Various pointers 2812292SN/A ///////////////////////// 2822292SN/A 2831060SN/A /** Pointer to the CPU. */ 2842733Sktlim@umich.edu O3CPU *cpu; 2851060SN/A 2862292SN/A /** Cache interface. */ 2872292SN/A MemInterface *dcacheInterface; 2882292SN/A 2892292SN/A /** Pointer to IEW stage. */ 2902292SN/A IEW *iewStage; 2912292SN/A 2921061SN/A /** The memory dependence unit, which tracks/predicts memory dependences 2931061SN/A * between instructions. 2941061SN/A */ 2952292SN/A MemDepUnit memDepUnit[Impl::MaxThreads]; 2961061SN/A 2971060SN/A /** The queue to the execute stage. Issued instructions will be written 2981060SN/A * into it. 2991060SN/A */ 3001060SN/A TimeBuffer<IssueStruct> *issueToExecuteQueue; 3011060SN/A 3021060SN/A /** The backwards time buffer. */ 3031060SN/A TimeBuffer<TimeStruct> *timeBuffer; 3041060SN/A 3051060SN/A /** Wire to read information from timebuffer. */ 3061060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3071060SN/A 3082292SN/A /** Function unit pool. */ 3092292SN/A FUPool *fuPool; 3102292SN/A 3112292SN/A ////////////////////////////////////// 3122292SN/A // Instruction lists, ready queues, and ordering 3132292SN/A ////////////////////////////////////// 3142292SN/A 3152292SN/A /** List of all the instructions in the IQ (some of which may be issued). */ 3162292SN/A std::list<DynInstPtr> instList[Impl::MaxThreads]; 3172292SN/A 3182348SN/A /** List of instructions that are ready to be executed. */ 3192333SN/A std::list<DynInstPtr> instsToExecute; 3202333SN/A 3217944SGiacomo.Gabrielli@arm.com /** List of instructions waiting for their DTB translation to 3227944SGiacomo.Gabrielli@arm.com * complete (hw page table walk in progress). 3237944SGiacomo.Gabrielli@arm.com */ 3247944SGiacomo.Gabrielli@arm.com std::list<DynInstPtr> deferredMemInsts; 3257944SGiacomo.Gabrielli@arm.com 32610333Smitch.hayenga@arm.com /** List of instructions that have been cache blocked. */ 32710333Smitch.hayenga@arm.com std::list<DynInstPtr> blockedMemInsts; 32810333Smitch.hayenga@arm.com 32910333Smitch.hayenga@arm.com /** List of instructions that were cache blocked, but a retry has been seen 33010333Smitch.hayenga@arm.com * since, so they can now be retried. May fail again go on the blocked list. 33110333Smitch.hayenga@arm.com */ 33210333Smitch.hayenga@arm.com std::list<DynInstPtr> retryMemInsts; 33310333Smitch.hayenga@arm.com 3342292SN/A /** 3352348SN/A * Struct for comparing entries to be added to the priority queue. 3362348SN/A * This gives reverse ordering to the instructions in terms of 3372348SN/A * sequence numbers: the instructions with smaller sequence 3382348SN/A * numbers (and hence are older) will be at the top of the 3392348SN/A * priority queue. 3402292SN/A */ 3412292SN/A struct pqCompare { 3422292SN/A bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const 3432292SN/A { 3442292SN/A return lhs->seqNum > rhs->seqNum; 3452292SN/A } 3461060SN/A }; 3471060SN/A 3482292SN/A typedef std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> 3492292SN/A ReadyInstQueue; 3501755SN/A 3512292SN/A /** List of ready instructions, per op class. They are separated by op 3522292SN/A * class to allow for easy mapping to FUs. 3531061SN/A */ 3542292SN/A ReadyInstQueue readyInsts[Num_OpClasses]; 3551061SN/A 3561061SN/A /** List of non-speculative instructions that will be scheduled 3571061SN/A * once the IQ gets a signal from commit. While it's redundant to 3581061SN/A * have the key be a part of the value (the sequence number is stored 3591061SN/A * inside of DynInst), when these instructions are woken up only 3601681SN/A * the sequence number will be available. Thus it is most efficient to be 3611061SN/A * able to search by the sequence number alone. 3621061SN/A */ 3631061SN/A std::map<InstSeqNum, DynInstPtr> nonSpecInsts; 3641061SN/A 3652292SN/A typedef typename std::map<InstSeqNum, DynInstPtr>::iterator NonSpecMapIt; 3662292SN/A 3672292SN/A /** Entry for the list age ordering by op class. */ 3682292SN/A struct ListOrderEntry { 3692292SN/A OpClass queueType; 3702292SN/A InstSeqNum oldestInst; 3712292SN/A }; 3722292SN/A 3732292SN/A /** List that contains the age order of the oldest instruction of each 3742292SN/A * ready queue. Used to select the oldest instruction available 3752292SN/A * among op classes. 3762326SN/A * @todo: Might be better to just move these entries around instead 3772326SN/A * of creating new ones every time the position changes due to an 3782326SN/A * instruction issuing. Not sure std::list supports this. 3792292SN/A */ 3802292SN/A std::list<ListOrderEntry> listOrder; 3812292SN/A 3822292SN/A typedef typename std::list<ListOrderEntry>::iterator ListOrderIt; 3832292SN/A 3842292SN/A /** Tracks if each ready queue is on the age order list. */ 3852292SN/A bool queueOnList[Num_OpClasses]; 3862292SN/A 3872292SN/A /** Iterators of each ready queue. Points to their spot in the age order 3882292SN/A * list. 3892292SN/A */ 3902292SN/A ListOrderIt readyIt[Num_OpClasses]; 3912292SN/A 3922292SN/A /** Add an op class to the age order list. */ 3932292SN/A void addToOrderList(OpClass op_class); 3942292SN/A 3952292SN/A /** 3962292SN/A * Called when the oldest instruction has been removed from a ready queue; 3972292SN/A * this places that ready queue into the proper spot in the age order list. 3982292SN/A */ 3992292SN/A void moveToYoungerInst(ListOrderIt age_order_it); 4002292SN/A 4012326SN/A DependencyGraph<DynInstPtr> dependGraph; 4022326SN/A 4032292SN/A ////////////////////////////////////// 4042292SN/A // Various parameters 4052292SN/A ////////////////////////////////////// 4062292SN/A 4072292SN/A /** IQ sharing policy for SMT. */ 40813561Snikos.nikoleris@arm.com SMTQueuePolicy iqPolicy; 4092292SN/A 4102292SN/A /** Number of Total Threads*/ 4116221Snate@binkert.org ThreadID numThreads; 4122292SN/A 4132292SN/A /** Pointer to list of active threads. */ 4146221Snate@binkert.org std::list<ThreadID> *activeThreads; 4152292SN/A 4162292SN/A /** Per Thread IQ count */ 4172292SN/A unsigned count[Impl::MaxThreads]; 4182292SN/A 4192292SN/A /** Max IQ Entries Per Thread */ 4202292SN/A unsigned maxEntries[Impl::MaxThreads]; 4211060SN/A 4221060SN/A /** Number of free IQ entries left. */ 4231060SN/A unsigned freeEntries; 4241060SN/A 4251060SN/A /** The number of entries in the instruction queue. */ 4261060SN/A unsigned numEntries; 4271060SN/A 4281060SN/A /** The total number of instructions that can be issued in one cycle. */ 4291060SN/A unsigned totalWidth; 4301060SN/A 4312292SN/A /** The number of physical registers in the CPU. */ 4321060SN/A unsigned numPhysRegs; 4331060SN/A 43410511Smitch.hayenga@arm.com /** Number of instructions currently in flight to FUs */ 43510511Smitch.hayenga@arm.com int wbOutstanding; 43610511Smitch.hayenga@arm.com 4371060SN/A /** Delay between commit stage and the IQ. 4381060SN/A * @todo: Make there be a distinction between the delays within IEW. 4391060SN/A */ 4409184Sandreas.hansson@arm.com Cycles commitToIEWDelay; 4411060SN/A 4421060SN/A /** The sequence number of the squashed instruction. */ 4432292SN/A InstSeqNum squashedSeqNum[Impl::MaxThreads]; 4441060SN/A 4451060SN/A /** A cache of the recently woken registers. It is 1 if the register 4461060SN/A * has been woken up recently, and 0 if the register has been added 4471060SN/A * to the dependency graph and has not yet received its value. It 4481060SN/A * is basically a secondary scoreboard, and should pretty much mirror 4491060SN/A * the scoreboard that exists in the rename map. 4501060SN/A */ 4512292SN/A std::vector<bool> regScoreboard; 4521060SN/A 4532326SN/A /** Adds an instruction to the dependency graph, as a consumer. */ 45413429Srekai.gonzalezalberquilla@arm.com bool addToDependents(const DynInstPtr &new_inst); 4551684SN/A 4562326SN/A /** Adds an instruction to the dependency graph, as a producer. */ 45713429Srekai.gonzalezalberquilla@arm.com void addToProducers(const DynInstPtr &new_inst); 4581755SN/A 4592292SN/A /** Moves an instruction to the ready queue if it is ready. */ 46013429Srekai.gonzalezalberquilla@arm.com void addIfReady(const DynInstPtr &inst); 4611684SN/A 4621684SN/A /** Debugging function to count how many entries are in the IQ. It does 4631684SN/A * a linear walk through the instructions, so do not call this function 4641684SN/A * during normal execution. 4651684SN/A */ 4661684SN/A int countInsts(); 4671684SN/A 4681684SN/A /** Debugging function to dump all the list sizes, as well as print 4691684SN/A * out the list of nonspeculative instructions. Should not be used 4701684SN/A * in any other capacity, but it has no harmful sideaffects. 4711684SN/A */ 4721684SN/A void dumpLists(); 4731062SN/A 4742292SN/A /** Debugging function to dump out all instructions that are in the 4752292SN/A * IQ. 4762292SN/A */ 4772292SN/A void dumpInsts(); 4782292SN/A 4792292SN/A /** Stat for number of instructions added. */ 4805999Snate@binkert.org Stats::Scalar iqInstsAdded; 4812292SN/A /** Stat for number of non-speculative instructions added. */ 4825999Snate@binkert.org Stats::Scalar iqNonSpecInstsAdded; 4832326SN/A 4845999Snate@binkert.org Stats::Scalar iqInstsIssued; 4852292SN/A /** Stat for number of integer instructions issued. */ 4865999Snate@binkert.org Stats::Scalar iqIntInstsIssued; 4872292SN/A /** Stat for number of floating point instructions issued. */ 4885999Snate@binkert.org Stats::Scalar iqFloatInstsIssued; 4892292SN/A /** Stat for number of branch instructions issued. */ 4905999Snate@binkert.org Stats::Scalar iqBranchInstsIssued; 4912292SN/A /** Stat for number of memory instructions issued. */ 4925999Snate@binkert.org Stats::Scalar iqMemInstsIssued; 4932292SN/A /** Stat for number of miscellaneous instructions issued. */ 4945999Snate@binkert.org Stats::Scalar iqMiscInstsIssued; 4952292SN/A /** Stat for number of squashed instructions that were ready to issue. */ 4965999Snate@binkert.org Stats::Scalar iqSquashedInstsIssued; 4972292SN/A /** Stat for number of squashed instructions examined when squashing. */ 4985999Snate@binkert.org Stats::Scalar iqSquashedInstsExamined; 4992292SN/A /** Stat for number of squashed instruction operands examined when 5002292SN/A * squashing. 5012292SN/A */ 5025999Snate@binkert.org Stats::Scalar iqSquashedOperandsExamined; 5032292SN/A /** Stat for number of non-speculative instructions removed due to a squash. 5042292SN/A */ 5055999Snate@binkert.org Stats::Scalar iqSquashedNonSpecRemoved; 5062727Sktlim@umich.edu // Also include number of instructions rescheduled and replayed. 5071062SN/A 5082727Sktlim@umich.edu /** Distribution of number of instructions in the queue. 5092727Sktlim@umich.edu * @todo: Need to create struct to track the entry time for each 5102727Sktlim@umich.edu * instruction. */ 5115999Snate@binkert.org// Stats::VectorDistribution queueResDist; 5122348SN/A /** Distribution of the number of instructions issued. */ 5135999Snate@binkert.org Stats::Distribution numIssuedDist; 5142727Sktlim@umich.edu /** Distribution of the cycles it takes to issue an instruction. 5152727Sktlim@umich.edu * @todo: Need to create struct to track the ready time for each 5162727Sktlim@umich.edu * instruction. */ 5175999Snate@binkert.org// Stats::VectorDistribution issueDelayDist; 5182301SN/A 5192348SN/A /** Number of times an instruction could not be issued because a 5202348SN/A * FU was busy. 5212348SN/A */ 5225999Snate@binkert.org Stats::Vector statFuBusy; 5235999Snate@binkert.org// Stats::Vector dist_unissued; 5242348SN/A /** Stat for total number issued for each instruction type. */ 5255999Snate@binkert.org Stats::Vector2d statIssuedInstType; 5262301SN/A 5272348SN/A /** Number of instructions issued per cycle. */ 5282326SN/A Stats::Formula issueRate; 5292727Sktlim@umich.edu 5302348SN/A /** Number of times the FU was busy. */ 5315999Snate@binkert.org Stats::Vector fuBusy; 5322348SN/A /** Number of times the FU was busy per instruction issued. */ 5332326SN/A Stats::Formula fuBusyRate; 5347897Shestness@cs.utexas.edu public: 5357897Shestness@cs.utexas.edu Stats::Scalar intInstQueueReads; 5367897Shestness@cs.utexas.edu Stats::Scalar intInstQueueWrites; 5377897Shestness@cs.utexas.edu Stats::Scalar intInstQueueWakeupAccesses; 5387897Shestness@cs.utexas.edu Stats::Scalar fpInstQueueReads; 5397897Shestness@cs.utexas.edu Stats::Scalar fpInstQueueWrites; 54012110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar fpInstQueueWakeupAccesses; 54112110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecInstQueueReads; 54212110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecInstQueueWrites; 54312110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecInstQueueWakeupAccesses; 5447897Shestness@cs.utexas.edu 5457897Shestness@cs.utexas.edu Stats::Scalar intAluAccesses; 5467897Shestness@cs.utexas.edu Stats::Scalar fpAluAccesses; 54712110SRekai.GonzalezAlberquilla@arm.com Stats::Scalar vecAluAccesses; 5481060SN/A}; 5491060SN/A 5502292SN/A#endif //__CPU_O3_INST_QUEUE_HH__ 551