1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 *          Nathan Binkert
30 *          Ali Saidi
31 */
32
33#ifndef __ARCH_ALPHA_EV5_HH__
34#define __ARCH_ALPHA_EV5_HH__
35
36#include "arch/alpha/isa_traits.hh"
37
38class ThreadContext;
39
40namespace AlphaISA {
41
42const uint64_t AsnMask = ULL(0xff);
43const int VAddrImplBits = 43;
44const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
45const Addr VAddrUnImplMask = ~VAddrImplMask;
46inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
47inline Addr VAddrVPN(Addr a) { return a >> PageShift; }
48inline Addr VAddrOffset(Addr a) { return a & PageOffset; }
49inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
50inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
51
52inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
53const int PAddrImplBits = 44; // for Tsunami
54const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
55const Addr PAddrUncachedBit39 = ULL(0x8000000000);
56const Addr PAddrUncachedBit40 = ULL(0x10000000000);
57const Addr PAddrUncachedBit43 = ULL(0x80000000000);
58const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
59
60inline Addr
61Phys2K0Seg(Addr addr)
62{
63    if (addr & PAddrUncachedBit43) {
64        addr &= PAddrUncachedMask;
65        addr |= PAddrUncachedBit40;
66    }
67    return addr | K0SegBase;
68}
69
70inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
71inline Addr DTB_PTE_PPN(uint64_t reg)
72{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
73inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
74inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
75inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
76inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
77inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
78inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
79
80inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
81inline Addr ITB_PTE_PPN(uint64_t reg)
82{ return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
83inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
84inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
85inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
86inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
87inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
88
89inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
90
91inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
92inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
93inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
94
95inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
96inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
97inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
98
99const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
100const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
101const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
102const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
103const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
104const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
105inline int Opcode(MachInst inst) { return inst >> 26 & 0x3f; }
106inline int Ra(MachInst inst) { return inst >> 21 & 0x1f; }
107
108const Addr PalBase = 0x4000;
109const Addr PalMax = 0x10000;
110
111void copyIprs(ThreadContext *src, ThreadContext *dest);
112
113} // namespace AlphaISA
114
115#endif // __ARCH_ALPHA_EV5_HH__
116