110259SAndrew.Bardsley@arm.com/* 210259SAndrew.Bardsley@arm.com * Copyright (c) 2013-2014 ARM Limited 310259SAndrew.Bardsley@arm.com * All rights reserved 410259SAndrew.Bardsley@arm.com * 510259SAndrew.Bardsley@arm.com * The license below extends only to copyright in the software and shall 610259SAndrew.Bardsley@arm.com * not be construed as granting a license to any other intellectual 710259SAndrew.Bardsley@arm.com * property including but not limited to intellectual property relating 810259SAndrew.Bardsley@arm.com * to a hardware implementation of the functionality of the software 910259SAndrew.Bardsley@arm.com * licensed hereunder. You may use the software subject to the license 1010259SAndrew.Bardsley@arm.com * terms below provided that you ensure that this notice is replicated 1110259SAndrew.Bardsley@arm.com * unmodified and in its entirety in all distributions of the software, 1210259SAndrew.Bardsley@arm.com * modified or unmodified, in source code or in binary form. 1310259SAndrew.Bardsley@arm.com * 1410259SAndrew.Bardsley@arm.com * Redistribution and use in source and binary forms, with or without 1510259SAndrew.Bardsley@arm.com * modification, are permitted provided that the following conditions are 1610259SAndrew.Bardsley@arm.com * met: redistributions of source code must retain the above copyright 1710259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer; 1810259SAndrew.Bardsley@arm.com * redistributions in binary form must reproduce the above copyright 1910259SAndrew.Bardsley@arm.com * notice, this list of conditions and the following disclaimer in the 2010259SAndrew.Bardsley@arm.com * documentation and/or other materials provided with the distribution; 2110259SAndrew.Bardsley@arm.com * neither the name of the copyright holders nor the names of its 2210259SAndrew.Bardsley@arm.com * contributors may be used to endorse or promote products derived from 2310259SAndrew.Bardsley@arm.com * this software without specific prior written permission. 2410259SAndrew.Bardsley@arm.com * 2510259SAndrew.Bardsley@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610259SAndrew.Bardsley@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710259SAndrew.Bardsley@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810259SAndrew.Bardsley@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910259SAndrew.Bardsley@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010259SAndrew.Bardsley@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110259SAndrew.Bardsley@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210259SAndrew.Bardsley@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310259SAndrew.Bardsley@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410259SAndrew.Bardsley@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510259SAndrew.Bardsley@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610259SAndrew.Bardsley@arm.com * 3710259SAndrew.Bardsley@arm.com * Authors: Andrew Bardsley 3810259SAndrew.Bardsley@arm.com */ 3910259SAndrew.Bardsley@arm.com 4010259SAndrew.Bardsley@arm.com/** 4110259SAndrew.Bardsley@arm.com * @file 4210259SAndrew.Bardsley@arm.com * 4310259SAndrew.Bardsley@arm.com * Execute function unit descriptions and pipeline implementations. 4410259SAndrew.Bardsley@arm.com */ 4510259SAndrew.Bardsley@arm.com 4610259SAndrew.Bardsley@arm.com#ifndef __CPU_MINOR_FUNC_UNIT_HH__ 4710259SAndrew.Bardsley@arm.com#define __CPU_MINOR_FUNC_UNIT_HH__ 4810259SAndrew.Bardsley@arm.com 4910259SAndrew.Bardsley@arm.com#include "cpu/minor/buffers.hh" 5010259SAndrew.Bardsley@arm.com#include "cpu/minor/dyn_inst.hh" 5110259SAndrew.Bardsley@arm.com#include "cpu/func_unit.hh" 5210259SAndrew.Bardsley@arm.com#include "cpu/timing_expr.hh" 5310259SAndrew.Bardsley@arm.com#include "params/MinorFU.hh" 5410259SAndrew.Bardsley@arm.com#include "params/MinorFUPool.hh" 5510259SAndrew.Bardsley@arm.com#include "params/MinorOpClass.hh" 5610259SAndrew.Bardsley@arm.com#include "params/MinorOpClassSet.hh" 5710259SAndrew.Bardsley@arm.com#include "sim/clocked_object.hh" 5810259SAndrew.Bardsley@arm.com 5910259SAndrew.Bardsley@arm.com/** Boxing for MinorOpClass to get around a build problem with C++11 but 6010259SAndrew.Bardsley@arm.com * also allow for future additions to op class checking */ 6110259SAndrew.Bardsley@arm.comclass MinorOpClass : public SimObject 6210259SAndrew.Bardsley@arm.com{ 6310259SAndrew.Bardsley@arm.com public: 6410259SAndrew.Bardsley@arm.com OpClass opClass; 6510259SAndrew.Bardsley@arm.com 6610259SAndrew.Bardsley@arm.com public: 6710259SAndrew.Bardsley@arm.com MinorOpClass(const MinorOpClassParams *params) : 6810259SAndrew.Bardsley@arm.com SimObject(params), 6910259SAndrew.Bardsley@arm.com opClass(params->opClass) 7010259SAndrew.Bardsley@arm.com { } 7110259SAndrew.Bardsley@arm.com}; 7210259SAndrew.Bardsley@arm.com 7310259SAndrew.Bardsley@arm.com/** Wrapper for a matchable set of op classes */ 7410259SAndrew.Bardsley@arm.comclass MinorOpClassSet : public SimObject 7510259SAndrew.Bardsley@arm.com{ 7610259SAndrew.Bardsley@arm.com public: 7710259SAndrew.Bardsley@arm.com std::vector<MinorOpClass *> opClasses; 7810259SAndrew.Bardsley@arm.com 7910259SAndrew.Bardsley@arm.com /** Convenience packing of opClasses into a bit vector for easier 8010259SAndrew.Bardsley@arm.com * testing */ 8110259SAndrew.Bardsley@arm.com std::vector<bool> capabilityList; 8210259SAndrew.Bardsley@arm.com 8310259SAndrew.Bardsley@arm.com public: 8410259SAndrew.Bardsley@arm.com MinorOpClassSet(const MinorOpClassSetParams *params); 8510259SAndrew.Bardsley@arm.com 8610259SAndrew.Bardsley@arm.com public: 8710259SAndrew.Bardsley@arm.com /** Does this set support the given op class */ 8810259SAndrew.Bardsley@arm.com bool provides(OpClass op_class) { return capabilityList[op_class]; } 8910259SAndrew.Bardsley@arm.com}; 9010259SAndrew.Bardsley@arm.com 9110259SAndrew.Bardsley@arm.com/** Extra timing capability to allow individual ops to have their source 9210259SAndrew.Bardsley@arm.com * register dependency latencies tweaked based on the ExtMachInst of the 9310259SAndrew.Bardsley@arm.com * source instruction. 9410259SAndrew.Bardsley@arm.com */ 9510259SAndrew.Bardsley@arm.comclass MinorFUTiming: public SimObject 9610259SAndrew.Bardsley@arm.com{ 9710259SAndrew.Bardsley@arm.com public: 9810259SAndrew.Bardsley@arm.com /** Mask off the ExtMachInst of an instruction before comparing with 9910259SAndrew.Bardsley@arm.com * match */ 10010259SAndrew.Bardsley@arm.com uint64_t mask; 10110259SAndrew.Bardsley@arm.com uint64_t match; 10210259SAndrew.Bardsley@arm.com 10310259SAndrew.Bardsley@arm.com /** Textual description of the decode's purpose */ 10410259SAndrew.Bardsley@arm.com std::string description; 10510259SAndrew.Bardsley@arm.com 10610259SAndrew.Bardsley@arm.com /** If true, instructions matching this mask/match should *not* be 10710259SAndrew.Bardsley@arm.com * issued in this FU */ 10810259SAndrew.Bardsley@arm.com bool suppress; 10910259SAndrew.Bardsley@arm.com 11010259SAndrew.Bardsley@arm.com /** Extra latency that the instruction should spend at the end of 11110259SAndrew.Bardsley@arm.com * the pipeline */ 11210259SAndrew.Bardsley@arm.com Cycles extraCommitLat; 11310259SAndrew.Bardsley@arm.com TimingExpr *extraCommitLatExpr; 11410259SAndrew.Bardsley@arm.com 11510259SAndrew.Bardsley@arm.com /** Extra delay that results should show in the scoreboard after 11610259SAndrew.Bardsley@arm.com * leaving the pipeline. If set to Cycles(0) for memory references, 11710259SAndrew.Bardsley@arm.com * an 'unpredictable' return time will be set in the scoreboard 11810259SAndrew.Bardsley@arm.com * blocking following dependent instructions from issuing */ 11910259SAndrew.Bardsley@arm.com Cycles extraAssumedLat; 12010259SAndrew.Bardsley@arm.com 12110259SAndrew.Bardsley@arm.com /** Cycle offsets from the scoreboard delivery times of register values 12210259SAndrew.Bardsley@arm.com * for each of this instruction's source registers (in srcRegs order). 12310259SAndrew.Bardsley@arm.com * The offsets are subtracted from the scoreboard returnCycle times. 12410259SAndrew.Bardsley@arm.com * For example, for an instruction type with 3 source registers, 12510259SAndrew.Bardsley@arm.com * [2, 1, 2] will allow the instruction to issue upto 2 cycles early 12610259SAndrew.Bardsley@arm.com * for dependencies on the 1st and 3rd register and upto 1 cycle early 12710259SAndrew.Bardsley@arm.com * on the 2nd. */ 12810259SAndrew.Bardsley@arm.com std::vector<Cycles> srcRegsRelativeLats; 12910259SAndrew.Bardsley@arm.com 13010259SAndrew.Bardsley@arm.com /** Extra opClasses check (after the FU one) */ 13110259SAndrew.Bardsley@arm.com MinorOpClassSet *opClasses; 13210259SAndrew.Bardsley@arm.com 13310259SAndrew.Bardsley@arm.com public: 13410259SAndrew.Bardsley@arm.com MinorFUTiming(const MinorFUTimingParams *params); 13510259SAndrew.Bardsley@arm.com 13610259SAndrew.Bardsley@arm.com public: 13710259SAndrew.Bardsley@arm.com /** Does the extra decode in this object support the given op class */ 13810259SAndrew.Bardsley@arm.com bool provides(OpClass op_class) { return opClasses->provides(op_class); } 13910259SAndrew.Bardsley@arm.com}; 14010259SAndrew.Bardsley@arm.com 14110259SAndrew.Bardsley@arm.com/** A functional unit that can execute any of opClasses operations with a 14210259SAndrew.Bardsley@arm.com * single op(eration)Lat(ency) and issueLat(ency) associated with the unit 14310259SAndrew.Bardsley@arm.com * rather than each operation (as in src/FuncUnit). 14410259SAndrew.Bardsley@arm.com * 14510259SAndrew.Bardsley@arm.com * This is very similar to cpu/func_unit but replicated here to allow 14610259SAndrew.Bardsley@arm.com * the Minor functional units to change without having to disturb the common 14710259SAndrew.Bardsley@arm.com * definition. 14810259SAndrew.Bardsley@arm.com */ 14910259SAndrew.Bardsley@arm.comclass MinorFU : public SimObject 15010259SAndrew.Bardsley@arm.com{ 15110259SAndrew.Bardsley@arm.com public: 15210259SAndrew.Bardsley@arm.com MinorOpClassSet *opClasses; 15310259SAndrew.Bardsley@arm.com 15410259SAndrew.Bardsley@arm.com /** Delay from issuing the operation, to it reaching the 15510259SAndrew.Bardsley@arm.com * end of the associated pipeline */ 15610259SAndrew.Bardsley@arm.com Cycles opLat; 15710259SAndrew.Bardsley@arm.com 15810259SAndrew.Bardsley@arm.com /** Delay after issuing an operation before the next 15910259SAndrew.Bardsley@arm.com * operation can be issued */ 16010259SAndrew.Bardsley@arm.com Cycles issueLat; 16110259SAndrew.Bardsley@arm.com 16210259SAndrew.Bardsley@arm.com /** FUs which this pipeline can't receive a forwarded (i.e. relative 16310259SAndrew.Bardsley@arm.com * latency != 0) result from */ 16410259SAndrew.Bardsley@arm.com std::vector<unsigned int> cantForwardFromFUIndices; 16510259SAndrew.Bardsley@arm.com 16610259SAndrew.Bardsley@arm.com /** Extra timing info to give timings to individual ops */ 16710259SAndrew.Bardsley@arm.com std::vector<MinorFUTiming *> timings; 16810259SAndrew.Bardsley@arm.com 16910259SAndrew.Bardsley@arm.com public: 17010259SAndrew.Bardsley@arm.com MinorFU(const MinorFUParams *params) : 17110259SAndrew.Bardsley@arm.com SimObject(params), 17210259SAndrew.Bardsley@arm.com opClasses(params->opClasses), 17310259SAndrew.Bardsley@arm.com opLat(params->opLat), 17410259SAndrew.Bardsley@arm.com issueLat(params->issueLat), 17510259SAndrew.Bardsley@arm.com cantForwardFromFUIndices(params->cantForwardFromFUIndices), 17610259SAndrew.Bardsley@arm.com timings(params->timings) 17710259SAndrew.Bardsley@arm.com { } 17810259SAndrew.Bardsley@arm.com}; 17910259SAndrew.Bardsley@arm.com 18010259SAndrew.Bardsley@arm.com/** A collection of MinorFUs */ 18110259SAndrew.Bardsley@arm.comclass MinorFUPool : public SimObject 18210259SAndrew.Bardsley@arm.com{ 18310259SAndrew.Bardsley@arm.com public: 18410259SAndrew.Bardsley@arm.com std::vector<MinorFU *> funcUnits; 18510259SAndrew.Bardsley@arm.com 18610259SAndrew.Bardsley@arm.com public: 18710259SAndrew.Bardsley@arm.com MinorFUPool(const MinorFUPoolParams *params) : 18810259SAndrew.Bardsley@arm.com SimObject(params), 18910259SAndrew.Bardsley@arm.com funcUnits(params->funcUnits) 19010259SAndrew.Bardsley@arm.com { } 19110259SAndrew.Bardsley@arm.com}; 19210259SAndrew.Bardsley@arm.com 19310259SAndrew.Bardsley@arm.comnamespace Minor 19410259SAndrew.Bardsley@arm.com{ 19510259SAndrew.Bardsley@arm.com 19610259SAndrew.Bardsley@arm.com/** Container class to box instructions in the FUs to make those 19710259SAndrew.Bardsley@arm.com * queues have correct bubble behaviour when stepped */ 19810259SAndrew.Bardsley@arm.comclass QueuedInst 19910259SAndrew.Bardsley@arm.com{ 20010259SAndrew.Bardsley@arm.com public: 20110259SAndrew.Bardsley@arm.com MinorDynInstPtr inst; 20210259SAndrew.Bardsley@arm.com 20310259SAndrew.Bardsley@arm.com public: 20410259SAndrew.Bardsley@arm.com QueuedInst(MinorDynInstPtr inst_ = MinorDynInst::bubble()) : 20510259SAndrew.Bardsley@arm.com inst(inst_) 20610259SAndrew.Bardsley@arm.com { } 20710259SAndrew.Bardsley@arm.com 20810259SAndrew.Bardsley@arm.com public: 20910259SAndrew.Bardsley@arm.com /** Report and bubble interfaces */ 21010259SAndrew.Bardsley@arm.com void reportData(std::ostream &os) const; 21110259SAndrew.Bardsley@arm.com bool isBubble() const { return inst->isBubble(); } 21210259SAndrew.Bardsley@arm.com 21310259SAndrew.Bardsley@arm.com static QueuedInst bubble() 21410259SAndrew.Bardsley@arm.com { return QueuedInst(MinorDynInst::bubble()); } 21510259SAndrew.Bardsley@arm.com}; 21610259SAndrew.Bardsley@arm.com 21710259SAndrew.Bardsley@arm.com/** Functional units have pipelines which stall when an inst gets to 21810259SAndrew.Bardsley@arm.com * their ends allowing Execute::commit to pick up timing-completed insts 21910259SAndrew.Bardsley@arm.com * when it feels like it */ 22010259SAndrew.Bardsley@arm.comtypedef SelfStallingPipeline<QueuedInst, 22110259SAndrew.Bardsley@arm.com ReportTraitsAdaptor<QueuedInst> > FUPipelineBase; 22210259SAndrew.Bardsley@arm.com 22310259SAndrew.Bardsley@arm.com/** A functional unit configured from a MinorFU object */ 22410259SAndrew.Bardsley@arm.comclass FUPipeline : public FUPipelineBase, public FuncUnit 22510259SAndrew.Bardsley@arm.com{ 22610259SAndrew.Bardsley@arm.com public: 22710259SAndrew.Bardsley@arm.com /** Functional unit description that this pipeline implements */ 22810259SAndrew.Bardsley@arm.com const MinorFU &description; 22910259SAndrew.Bardsley@arm.com 23010259SAndrew.Bardsley@arm.com /** An FUPipeline needs access to curCycle, use this timing source */ 23110259SAndrew.Bardsley@arm.com ClockedObject &timeSource; 23210259SAndrew.Bardsley@arm.com 23310259SAndrew.Bardsley@arm.com /** Set of operation classes supported by this FU */ 23410259SAndrew.Bardsley@arm.com std::bitset<Num_OpClasses> capabilityList; 23510259SAndrew.Bardsley@arm.com 23610259SAndrew.Bardsley@arm.com /** FUs which this pipeline can't receive a forwarded (i.e. relative 23710259SAndrew.Bardsley@arm.com * latency != 0) result from */ 23810259SAndrew.Bardsley@arm.com std::vector<bool> cantForwardFromFUIndices; 23910259SAndrew.Bardsley@arm.com 24010259SAndrew.Bardsley@arm.com public: 24110259SAndrew.Bardsley@arm.com /** When can a new instruction be inserted into the pipeline? This is 24210259SAndrew.Bardsley@arm.com * an absolute cycle time unless it is 0 in which case the an 24310259SAndrew.Bardsley@arm.com * instruction can be pushed straightaway */ 24410259SAndrew.Bardsley@arm.com Cycles nextInsertCycle; 24510259SAndrew.Bardsley@arm.com 24610259SAndrew.Bardsley@arm.com public: 24710259SAndrew.Bardsley@arm.com FUPipeline(const std::string &name, const MinorFU &description_, 24810259SAndrew.Bardsley@arm.com ClockedObject &timeSource_); 24910259SAndrew.Bardsley@arm.com 25010259SAndrew.Bardsley@arm.com public: 25110259SAndrew.Bardsley@arm.com /** How many cycles must from curCycle before insertion into the 25210259SAndrew.Bardsley@arm.com * pipeline is allowed */ 25310259SAndrew.Bardsley@arm.com Cycles cyclesBeforeInsert(); 25410259SAndrew.Bardsley@arm.com 25510259SAndrew.Bardsley@arm.com /** Can an instruction be inserted now? */ 25610259SAndrew.Bardsley@arm.com bool canInsert() const; 25710259SAndrew.Bardsley@arm.com 25810259SAndrew.Bardsley@arm.com /** Find the extra timing information for this instruction. Returns 25910259SAndrew.Bardsley@arm.com * NULL if no decode info. is found */ 26010417Sandreas.hansson@arm.com MinorFUTiming *findTiming(const StaticInstPtr &inst); 26110259SAndrew.Bardsley@arm.com 26210259SAndrew.Bardsley@arm.com /** Step the pipeline. Allow multiple steps? */ 26310259SAndrew.Bardsley@arm.com void advance(); 26410259SAndrew.Bardsley@arm.com}; 26510259SAndrew.Bardsley@arm.com 26610259SAndrew.Bardsley@arm.com} 26710259SAndrew.Bardsley@arm.com 26810259SAndrew.Bardsley@arm.com#endif /* __CPU_MINOR_FUNC_UNIT_HH__ */ 269