11689SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2010-2012, 2014 ARM Limited 37782Sminkyu.jeong@arm.com * All rights reserved 47782Sminkyu.jeong@arm.com * 57782Sminkyu.jeong@arm.com * The license below extends only to copyright in the software and shall 67782Sminkyu.jeong@arm.com * not be construed as granting a license to any other intellectual 77782Sminkyu.jeong@arm.com * property including but not limited to intellectual property relating 87782Sminkyu.jeong@arm.com * to a hardware implementation of the functionality of the software 97782Sminkyu.jeong@arm.com * licensed hereunder. You may use the software subject to the license 107782Sminkyu.jeong@arm.com * terms below provided that you ensure that this notice is replicated 117782Sminkyu.jeong@arm.com * unmodified and in its entirety in all distributions of the software, 127782Sminkyu.jeong@arm.com * modified or unmodified, in source code or in binary form. 137782Sminkyu.jeong@arm.com * 142326SN/A * Copyright (c) 2004-2006 The Regents of The University of Michigan 151689SN/A * All rights reserved. 161689SN/A * 171689SN/A * Redistribution and use in source and binary forms, with or without 181689SN/A * modification, are permitted provided that the following conditions are 191689SN/A * met: redistributions of source code must retain the above copyright 201689SN/A * notice, this list of conditions and the following disclaimer; 211689SN/A * redistributions in binary form must reproduce the above copyright 221689SN/A * notice, this list of conditions and the following disclaimer in the 231689SN/A * documentation and/or other materials provided with the distribution; 241689SN/A * neither the name of the copyright holders nor the names of its 251689SN/A * contributors may be used to endorse or promote products derived from 261689SN/A * this software without specific prior written permission. 271689SN/A * 281689SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 291689SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 301689SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 311689SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 321689SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 331689SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 341689SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 351689SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 361689SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 371689SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 381689SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665Ssaidi@eecs.umich.edu * 402665Ssaidi@eecs.umich.edu * Authors: Kevin Lim 411689SN/A */ 421689SN/A 432292SN/A#ifndef __CPU_O3_IEW_HH__ 442292SN/A#define __CPU_O3_IEW_HH__ 451060SN/A 461060SN/A#include <queue> 478230Snate@binkert.org#include <set> 481060SN/A 491461SN/A#include "base/statistics.hh" 501717SN/A#include "cpu/o3/comm.hh" 518229Snate@binkert.org#include "cpu/o3/lsq.hh" 522292SN/A#include "cpu/o3/scoreboard.hh" 538229Snate@binkert.org#include "cpu/timebuf.hh" 548232Snate@binkert.org#include "debug/IEW.hh" 5510023Smatt.horsnell@ARM.com#include "sim/probe/probe.hh" 561060SN/A 578737Skoansin.tan@gmail.comstruct DerivO3CPUParams; 582292SN/Aclass FUPool; 592292SN/A 602292SN/A/** 612326SN/A * DefaultIEW handles both single threaded and SMT IEW 622326SN/A * (issue/execute/writeback). It handles the dispatching of 632326SN/A * instructions to the LSQ/IQ as part of the issue stage, and has the 642326SN/A * IQ try to issue instructions each cycle. The execute latency is 652326SN/A * actually tied into the issue latency to allow the IQ to be able to 662292SN/A * do back-to-back scheduling without having to speculatively schedule 672326SN/A * instructions. This happens by having the IQ have access to the 682326SN/A * functional units, and the IQ gets the execution latencies from the 692326SN/A * FUs when it issues instructions. Instructions reach the execute 702326SN/A * stage on the last cycle of their execution, which is when the IQ 712326SN/A * knows to wake up any dependent instructions, allowing back to back 722326SN/A * scheduling. The execute portion of IEW separates memory 732326SN/A * instructions from non-memory instructions, either telling the LSQ 742326SN/A * to execute the instruction, or executing the instruction directly. 752326SN/A * The writeback portion of IEW completes the instructions by waking 762326SN/A * up any dependents, and marking the register ready on the 772326SN/A * scoreboard. 782292SN/A */ 791681SN/Atemplate<class Impl> 802292SN/Aclass DefaultIEW 811060SN/A{ 821060SN/A private: 831060SN/A //Typedefs from Impl 841061SN/A typedef typename Impl::CPUPol CPUPol; 851061SN/A typedef typename Impl::DynInstPtr DynInstPtr; 862733Sktlim@umich.edu typedef typename Impl::O3CPU O3CPU; 871060SN/A 881681SN/A typedef typename CPUPol::IQ IQ; 891061SN/A typedef typename CPUPol::RenameMap RenameMap; 902292SN/A typedef typename CPUPol::LSQ LSQ; 911060SN/A 921061SN/A typedef typename CPUPol::TimeStruct TimeStruct; 931061SN/A typedef typename CPUPol::IEWStruct IEWStruct; 941061SN/A typedef typename CPUPol::RenameStruct RenameStruct; 951061SN/A typedef typename CPUPol::IssueStruct IssueStruct; 961060SN/A 971060SN/A public: 982292SN/A /** Overall IEW stage status. Used to determine if the CPU can 992292SN/A * deschedule itself due to a lack of activity. 1002292SN/A */ 1011060SN/A enum Status { 1022292SN/A Active, 1032292SN/A Inactive 1042292SN/A }; 1052292SN/A 1062292SN/A /** Status for Issue, Execute, and Writeback stages. */ 1072292SN/A enum StageStatus { 1081060SN/A Running, 1091060SN/A Blocked, 1101060SN/A Idle, 1112292SN/A StartSquash, 1121060SN/A Squashing, 1131060SN/A Unblocking 1141060SN/A }; 1151060SN/A 1161060SN/A private: 1172292SN/A /** Overall stage status. */ 1181060SN/A Status _status; 1192292SN/A /** Dispatch status. */ 1202292SN/A StageStatus dispatchStatus[Impl::MaxThreads]; 1212292SN/A /** Execute status. */ 1222292SN/A StageStatus exeStatus; 1232292SN/A /** Writeback status. */ 1242292SN/A StageStatus wbStatus; 1251060SN/A 12610023Smatt.horsnell@ARM.com /** Probe points. */ 12710023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppMispredict; 12810023Smatt.horsnell@ARM.com ProbePointArg<DynInstPtr> *ppDispatch; 12911246Sradhika.jagtap@ARM.com /** To probe when instruction execution begins. */ 13011246Sradhika.jagtap@ARM.com ProbePointArg<DynInstPtr> *ppExecute; 13111246Sradhika.jagtap@ARM.com /** To probe when instruction execution is complete. */ 13211246Sradhika.jagtap@ARM.com ProbePointArg<DynInstPtr> *ppToCommit; 13310023Smatt.horsnell@ARM.com 1341060SN/A public: 1352292SN/A /** Constructs a DefaultIEW with the given parameters. */ 1365529Snate@binkert.org DefaultIEW(O3CPU *_cpu, DerivO3CPUParams *params); 1371060SN/A 1382292SN/A /** Returns the name of the DefaultIEW stage. */ 1392292SN/A std::string name() const; 1401062SN/A 1412292SN/A /** Registers statistics. */ 1422632Sstever@eecs.umich.edu void regStats(); 1432632Sstever@eecs.umich.edu 14410023Smatt.horsnell@ARM.com /** Registers probes. */ 14510023Smatt.horsnell@ARM.com void regProbePoints(); 14610023Smatt.horsnell@ARM.com 1472292SN/A /** Initializes stage; sends back the number of free IQ and LSQ entries. */ 1489427SAndreas.Sandberg@ARM.com void startupStage(); 1492292SN/A 15013641Sqtt2@cornell.edu /** Clear all thread-specific states */ 15113641Sqtt2@cornell.edu void clearStates(ThreadID tid); 15213641Sqtt2@cornell.edu 1532292SN/A /** Sets main time buffer used for backwards communication. */ 1542632Sstever@eecs.umich.edu void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr); 1552632Sstever@eecs.umich.edu 1562292SN/A /** Sets time buffer for getting instructions coming from rename. */ 1572632Sstever@eecs.umich.edu void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr); 1582632Sstever@eecs.umich.edu 1592292SN/A /** Sets time buffer to pass on instructions to commit. */ 1602632Sstever@eecs.umich.edu void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr); 1612632Sstever@eecs.umich.edu 1622292SN/A /** Sets pointer to list of active threads. */ 1636221Snate@binkert.org void setActiveThreads(std::list<ThreadID> *at_ptr); 1642632Sstever@eecs.umich.edu 1652292SN/A /** Sets pointer to the scoreboard. */ 1662292SN/A void setScoreboard(Scoreboard *sb_ptr); 1672632Sstever@eecs.umich.edu 1689444SAndreas.Sandberg@ARM.com /** Perform sanity checks after a drain. */ 1699444SAndreas.Sandberg@ARM.com void drainSanityCheck() const; 1702843Sktlim@umich.edu 1719444SAndreas.Sandberg@ARM.com /** Has the stage drained? */ 1729444SAndreas.Sandberg@ARM.com bool isDrained() const; 1732632Sstever@eecs.umich.edu 1742348SN/A /** Takes over from another CPU's thread. */ 1752307SN/A void takeOverFrom(); 1762632Sstever@eecs.umich.edu 1772292SN/A /** Squashes instructions in IEW for a specific thread. */ 1786221Snate@binkert.org void squash(ThreadID tid); 1792107SN/A 1802292SN/A /** Wakes all dependents of a completed instruction. */ 18113429Srekai.gonzalezalberquilla@arm.com void wakeDependents(const DynInstPtr &inst); 1822632Sstever@eecs.umich.edu 1832292SN/A /** Tells memory dependence unit that a memory instruction needs to be 1842292SN/A * rescheduled. It will re-execute once replayMemInst() is called. 1852292SN/A */ 18613429Srekai.gonzalezalberquilla@arm.com void rescheduleMemInst(const DynInstPtr &inst); 1872292SN/A 1882292SN/A /** Re-executes all rescheduled memory instructions. */ 18913429Srekai.gonzalezalberquilla@arm.com void replayMemInst(const DynInstPtr &inst); 1902292SN/A 19110333Smitch.hayenga@arm.com /** Moves memory instruction onto the list of cache blocked instructions */ 19213429Srekai.gonzalezalberquilla@arm.com void blockMemInst(const DynInstPtr &inst); 19310333Smitch.hayenga@arm.com 19410333Smitch.hayenga@arm.com /** Notifies that the cache has become unblocked */ 19510333Smitch.hayenga@arm.com void cacheUnblocked(); 19610333Smitch.hayenga@arm.com 1972292SN/A /** Sends an instruction to commit through the time buffer. */ 19813429Srekai.gonzalezalberquilla@arm.com void instToCommit(const DynInstPtr &inst); 1992632Sstever@eecs.umich.edu 2002292SN/A /** Inserts unused instructions of a thread into the skid buffer. */ 2016221Snate@binkert.org void skidInsert(ThreadID tid); 2022292SN/A 2032292SN/A /** Returns the max of the number of entries in all of the skid buffers. */ 2042292SN/A int skidCount(); 2052292SN/A 2062292SN/A /** Returns if all of the skid buffers are empty. */ 2072292SN/A bool skidsEmpty(); 2082292SN/A 2092292SN/A /** Updates overall IEW status based on all of the stages' statuses. */ 2102292SN/A void updateStatus(); 2112292SN/A 2122292SN/A /** Resets entries of the IQ and the LSQ. */ 2132292SN/A void resetEntries(); 2142292SN/A 2152292SN/A /** Tells the CPU to wakeup if it has descheduled itself due to no 2162292SN/A * activity. Used mainly by the LdWritebackEvent. 2172292SN/A */ 2182292SN/A void wakeCPU(); 2192292SN/A 2202292SN/A /** Reports to the CPU that there is activity this cycle. */ 2212292SN/A void activityThisCycle(); 2222292SN/A 2232292SN/A /** Tells CPU that the IEW stage is active and running. */ 2242292SN/A inline void activateStage(); 2252292SN/A 2262292SN/A /** Tells CPU that the IEW stage is inactive and idle. */ 2272292SN/A inline void deactivateStage(); 2282292SN/A 2292292SN/A /** Returns if the LSQ has any stores to writeback. */ 2302292SN/A bool hasStoresToWB() { return ldstQueue.hasStoresToWB(); } 2312292SN/A 2325557Sktlim@umich.edu /** Returns if the LSQ has any stores to writeback. */ 2336221Snate@binkert.org bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); } 2345557Sktlim@umich.edu 2357598Sminkyu.jeong@arm.com /** Check misprediction */ 23613429Srekai.gonzalezalberquilla@arm.com void checkMisprediction(const DynInstPtr &inst); 2377598Sminkyu.jeong@arm.com 2382632Sstever@eecs.umich.edu private: 2392292SN/A /** Sends commit proper information for a squash due to a branch 2402292SN/A * mispredict. 2412292SN/A */ 24213429Srekai.gonzalezalberquilla@arm.com void squashDueToBranch(const DynInstPtr &inst, ThreadID tid); 2432632Sstever@eecs.umich.edu 2442292SN/A /** Sends commit proper information for a squash due to a memory order 2452292SN/A * violation. 2462292SN/A */ 24713429Srekai.gonzalezalberquilla@arm.com void squashDueToMemOrder(const DynInstPtr &inst, ThreadID tid); 2482292SN/A 2492292SN/A /** Sets Dispatch to blocked, and signals back to other stages to block. */ 2506221Snate@binkert.org void block(ThreadID tid); 2512292SN/A 2522292SN/A /** Unblocks Dispatch if the skid buffer is empty, and signals back to 2532292SN/A * other stages to unblock. 2542292SN/A */ 2556221Snate@binkert.org void unblock(ThreadID tid); 2562292SN/A 2572292SN/A /** Determines proper actions to take given Dispatch's status. */ 2586221Snate@binkert.org void dispatch(ThreadID tid); 2592292SN/A 2602292SN/A /** Dispatches instructions to IQ and LSQ. */ 2616221Snate@binkert.org void dispatchInsts(ThreadID tid); 2622292SN/A 2632292SN/A /** Executes instructions. In the case of memory operations, it informs the 2642292SN/A * LSQ to execute the instructions. Also handles any redirects that occur 2652292SN/A * due to the executed instructions. 2662292SN/A */ 2672632Sstever@eecs.umich.edu void executeInsts(); 2682632Sstever@eecs.umich.edu 2692292SN/A /** Writebacks instructions. In our model, the instruction's execute() 2702292SN/A * function atomically reads registers, executes, and writes registers. 2712292SN/A * Thus this writeback only wakes up dependent instructions, and informs 2722292SN/A * the scoreboard of registers becoming ready. 2732292SN/A */ 2742292SN/A void writebackInsts(); 2752292SN/A 2762292SN/A /** Returns the number of valid, non-squashed instructions coming from 2772292SN/A * rename to dispatch. 2782292SN/A */ 2792292SN/A unsigned validInstsFromRename(); 2802292SN/A 2812292SN/A /** Checks if any of the stall conditions are currently true. */ 2826221Snate@binkert.org bool checkStall(ThreadID tid); 2832292SN/A 2842292SN/A /** Processes inputs and changes state accordingly. */ 2856221Snate@binkert.org void checkSignalsAndUpdate(ThreadID tid); 2862292SN/A 2872702Sktlim@umich.edu /** Removes instructions from rename from a thread's instruction list. */ 2886221Snate@binkert.org void emptyRenameInsts(ThreadID tid); 2892702Sktlim@umich.edu 2902292SN/A /** Sorts instructions coming from rename into lists separated by thread. */ 2912292SN/A void sortInsts(); 2921060SN/A 2931060SN/A public: 2942292SN/A /** Ticks IEW stage, causing Dispatch, the IQ, the LSQ, Execute, and 2952292SN/A * Writeback to run for one cycle. 2962292SN/A */ 2972632Sstever@eecs.umich.edu void tick(); 2981060SN/A 2991060SN/A private: 3002348SN/A /** Updates execution stats based on the instruction. */ 30113429Srekai.gonzalezalberquilla@arm.com void updateExeInstStats(const DynInstPtr &inst); 3021062SN/A 3032292SN/A /** Pointer to main time buffer used for backwards communication. */ 3042632Sstever@eecs.umich.edu TimeBuffer<TimeStruct> *timeBuffer; 3051062SN/A 3062292SN/A /** Wire to write information heading to previous stages. */ 3072292SN/A typename TimeBuffer<TimeStruct>::wire toFetch; 3081060SN/A 3091060SN/A /** Wire to get commit's output from backwards time buffer. */ 3101060SN/A typename TimeBuffer<TimeStruct>::wire fromCommit; 3111060SN/A 3121060SN/A /** Wire to write information heading to previous stages. */ 3131060SN/A typename TimeBuffer<TimeStruct>::wire toRename; 3141060SN/A 3151060SN/A /** Rename instruction queue interface. */ 3161060SN/A TimeBuffer<RenameStruct> *renameQueue; 3171060SN/A 3181060SN/A /** Wire to get rename's output from rename queue. */ 3191060SN/A typename TimeBuffer<RenameStruct>::wire fromRename; 3201060SN/A 3211060SN/A /** Issue stage queue. */ 3221060SN/A TimeBuffer<IssueStruct> issueToExecQueue; 3231060SN/A 3241060SN/A /** Wire to read information from the issue stage time queue. */ 3251060SN/A typename TimeBuffer<IssueStruct>::wire fromIssue; 3261060SN/A 3271060SN/A /** 3281060SN/A * IEW stage time buffer. Holds ROB indices of instructions that 3291060SN/A * can be marked as completed. 3301060SN/A */ 3311060SN/A TimeBuffer<IEWStruct> *iewQueue; 3321060SN/A 3331060SN/A /** Wire to write infromation heading to commit. */ 3341060SN/A typename TimeBuffer<IEWStruct>::wire toCommit; 3351060SN/A 3362292SN/A /** Queue of all instructions coming from rename this cycle. */ 3372292SN/A std::queue<DynInstPtr> insts[Impl::MaxThreads]; 3382292SN/A 3391060SN/A /** Skid buffer between rename and IEW. */ 3402292SN/A std::queue<DynInstPtr> skidBuffer[Impl::MaxThreads]; 3411060SN/A 3422292SN/A /** Scoreboard pointer. */ 3432292SN/A Scoreboard* scoreboard; 3442292SN/A 3451681SN/A private: 3462292SN/A /** CPU pointer. */ 3472733Sktlim@umich.edu O3CPU *cpu; 3481060SN/A 3492292SN/A /** Records if IEW has written to the time buffer this cycle, so that the 3502292SN/A * CPU can deschedule itself if there is no activity. 3512292SN/A */ 3522292SN/A bool wroteToTimeBuffer; 3532292SN/A 3542292SN/A /** Debug function to print instructions that are issued this cycle. */ 3552292SN/A void printAvailableInsts(); 3562292SN/A 3572292SN/A public: 3584329Sktlim@umich.edu /** Instruction queue. */ 3594329Sktlim@umich.edu IQ instQueue; 3604329Sktlim@umich.edu 3614329Sktlim@umich.edu /** Load / store queue. */ 3624329Sktlim@umich.edu LSQ ldstQueue; 3634329Sktlim@umich.edu 3644329Sktlim@umich.edu /** Pointer to the functional unit pool. */ 3654329Sktlim@umich.edu FUPool *fuPool; 3662292SN/A /** Records if the LSQ needs to be updated on the next cycle, so that 3672292SN/A * IEW knows if there will be activity on the next cycle. 3682292SN/A */ 3692292SN/A bool updateLSQNextCycle; 3702292SN/A 3711060SN/A private: 3722292SN/A /** Records if there is a fetch redirect on this cycle for each thread. */ 3732292SN/A bool fetchRedirect[Impl::MaxThreads]; 3742292SN/A 3752292SN/A /** Records if the queues have been changed (inserted or issued insts), 3762292SN/A * so that IEW knows to broadcast the updated amount of free entries. 3772292SN/A */ 3782292SN/A bool updatedQueues; 3792292SN/A 3809184Sandreas.hansson@arm.com /** Commit to IEW delay. */ 3819184Sandreas.hansson@arm.com Cycles commitToIEWDelay; 3821060SN/A 3839184Sandreas.hansson@arm.com /** Rename to IEW delay. */ 3849184Sandreas.hansson@arm.com Cycles renameToIEWDelay; 3851060SN/A 3861060SN/A /** 3879184Sandreas.hansson@arm.com * Issue to execute delay. What this actually represents is 3881060SN/A * the amount of time it takes for an instruction to wake up, be 3891060SN/A * scheduled, and sent to a FU for execution. 3901060SN/A */ 3919184Sandreas.hansson@arm.com Cycles issueToExecuteDelay; 3921060SN/A 3932820Sktlim@umich.edu /** Width of dispatch, in instructions. */ 3942820Sktlim@umich.edu unsigned dispatchWidth; 3951060SN/A 3961060SN/A /** Width of issue, in instructions. */ 3971060SN/A unsigned issueWidth; 3981060SN/A 3992292SN/A /** Index into queue of instructions being written back. */ 4002292SN/A unsigned wbNumInst; 4012292SN/A 4022292SN/A /** Cycle number within the queue of instructions being written back. 4032292SN/A * Used in case there are too many instructions writing back at the current 4042292SN/A * cycle and writesbacks need to be scheduled for the future. See comments 4052292SN/A * in instToCommit(). 4061060SN/A */ 4072292SN/A unsigned wbCycle; 4081060SN/A 4092820Sktlim@umich.edu /** Writeback width. */ 4102820Sktlim@umich.edu unsigned wbWidth; 4112820Sktlim@umich.edu 4122292SN/A /** Number of active threads. */ 4136221Snate@binkert.org ThreadID numThreads; 4142292SN/A 4152292SN/A /** Pointer to list of active threads. */ 4166221Snate@binkert.org std::list<ThreadID> *activeThreads; 4172292SN/A 4182292SN/A /** Maximum size of the skid buffer. */ 4192292SN/A unsigned skidBufferMax; 4202292SN/A 4212292SN/A /** Stat for total number of idle cycles. */ 4225999Snate@binkert.org Stats::Scalar iewIdleCycles; 4232292SN/A /** Stat for total number of squashing cycles. */ 4245999Snate@binkert.org Stats::Scalar iewSquashCycles; 4252292SN/A /** Stat for total number of blocking cycles. */ 4265999Snate@binkert.org Stats::Scalar iewBlockCycles; 4272292SN/A /** Stat for total number of unblocking cycles. */ 4285999Snate@binkert.org Stats::Scalar iewUnblockCycles; 4292292SN/A /** Stat for total number of instructions dispatched. */ 4305999Snate@binkert.org Stats::Scalar iewDispatchedInsts; 4312292SN/A /** Stat for total number of squashed instructions dispatch skips. */ 4325999Snate@binkert.org Stats::Scalar iewDispSquashedInsts; 4332292SN/A /** Stat for total number of dispatched load instructions. */ 4345999Snate@binkert.org Stats::Scalar iewDispLoadInsts; 4352292SN/A /** Stat for total number of dispatched store instructions. */ 4365999Snate@binkert.org Stats::Scalar iewDispStoreInsts; 4372292SN/A /** Stat for total number of dispatched non speculative instructions. */ 4385999Snate@binkert.org Stats::Scalar iewDispNonSpecInsts; 4392292SN/A /** Stat for number of times the IQ becomes full. */ 4405999Snate@binkert.org Stats::Scalar iewIQFullEvents; 4412292SN/A /** Stat for number of times the LSQ becomes full. */ 4425999Snate@binkert.org Stats::Scalar iewLSQFullEvents; 4432292SN/A /** Stat for total number of memory ordering violation events. */ 4445999Snate@binkert.org Stats::Scalar memOrderViolationEvents; 4452292SN/A /** Stat for total number of incorrect predicted taken branches. */ 4465999Snate@binkert.org Stats::Scalar predictedTakenIncorrect; 4472292SN/A /** Stat for total number of incorrect predicted not taken branches. */ 4485999Snate@binkert.org Stats::Scalar predictedNotTakenIncorrect; 4492292SN/A /** Stat for total number of mispredicted branches detected at execute. */ 4502292SN/A Stats::Formula branchMispredicts; 4512301SN/A 4522727Sktlim@umich.edu /** Stat for total number of executed instructions. */ 4535999Snate@binkert.org Stats::Scalar iewExecutedInsts; 4542727Sktlim@umich.edu /** Stat for total number of executed load instructions. */ 4555999Snate@binkert.org Stats::Vector iewExecLoadInsts; 4562353SN/A /** Stat for total number of executed store instructions. */ 4575999Snate@binkert.org// Stats::Scalar iewExecStoreInsts; 4582727Sktlim@umich.edu /** Stat for total number of squashed instructions skipped at execute. */ 4595999Snate@binkert.org Stats::Scalar iewExecSquashedInsts; 4602348SN/A /** Number of executed software prefetches. */ 4615999Snate@binkert.org Stats::Vector iewExecutedSwp; 4622348SN/A /** Number of executed nops. */ 4635999Snate@binkert.org Stats::Vector iewExecutedNop; 4642348SN/A /** Number of executed meomory references. */ 4655999Snate@binkert.org Stats::Vector iewExecutedRefs; 4662348SN/A /** Number of executed branches. */ 4675999Snate@binkert.org Stats::Vector iewExecutedBranches; 4682348SN/A /** Number of executed store instructions. */ 4692301SN/A Stats::Formula iewExecStoreInsts; 4702727Sktlim@umich.edu /** Number of instructions executed per cycle. */ 4712727Sktlim@umich.edu Stats::Formula iewExecRate; 4722727Sktlim@umich.edu 4732348SN/A /** Number of instructions sent to commit. */ 4745999Snate@binkert.org Stats::Vector iewInstsToCommit; 4752348SN/A /** Number of instructions that writeback. */ 4765999Snate@binkert.org Stats::Vector writebackCount; 4772348SN/A /** Number of instructions that wake consumers. */ 4785999Snate@binkert.org Stats::Vector producerInst; 4792348SN/A /** Number of instructions that wake up from producers. */ 4805999Snate@binkert.org Stats::Vector consumerInst; 4812348SN/A /** Number of instructions per cycle written back. */ 4822326SN/A Stats::Formula wbRate; 4832348SN/A /** Average number of woken instructions per writeback. */ 4842326SN/A Stats::Formula wbFanout; 4851060SN/A}; 4861060SN/A 4872292SN/A#endif // __CPU_O3_IEW_HH__ 488