| /gem5/src/cpu/o3/ |
| H A D | dyn_inst_impl.hh | 73 Tick fetch = this->fetchTick; local
75 if (fetch != -1) {
78 DPRINTFR(O3PipeView, "O3PipeView:fetch:%llu:0x%08llx:%d:%llu:%s\n",
79 fetch,
85 val = (this->decodeTick == -1) ? 0 : fetch + this->decodeTick;
87 val = (this->renameTick == -1) ? 0 : fetch + this->renameTick;
89 val = (this->dispatchTick == -1) ? 0 : fetch + this->dispatchTick;
91 val = (this->issueTick == -1) ? 0 : fetch + this->issueTick;
93 val = (this->completeTick == -1) ? 0 : fetch + this->completeTick;
95 val = (this->commitTick == -1) ? 0 : fetch
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| H A D | fetch.hh | 66 * DefaultFetch class handles both single threaded and SMT fetch. Its
67 * width is specified by the parameters; each cycle it tries to fetch
91 * IcachePort class for instruction fetch.
96 /** Pointer to fetch. */
97 DefaultFetch<Impl> *fetch; member in class:DefaultFetch::IcachePort
102 : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
107 /** Timing version of receive. Handles setting fetch to the
111 /** Handles doing a retry of a failed fetch. */
118 DefaultFetch<Impl> *fetch; member in class:DefaultFetch::FetchTranslation
122 : fetch(_fetc
146 DefaultFetch<Impl> *fetch; member in class:DefaultFetch::FinishTranslationEvent
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| H A D | cpu.cc | 106 fetch(this, params),
153 checker->setIcachePort(&this->fetch.getInstPort());
169 fetch.setActiveThreads(&activeThreads);
176 fetch.setTimeBuffer(&timeBuffer);
183 fetch.setFetchQueue(&fetchQueue);
390 fetch.regProbePoints();
461 this->fetch.regStats();
543 fetch.tick();
624 fetch.startupStage();
666 fetch
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| H A D | cpu.hh | 93 * FullO3CPU class, has each of the stages (fetch through commit)
559 /** The fetch stage. */
560 typename CPUPolicy::Fetch fetch; member in class:FullO3CPU
636 /** The fetch stage's instruction queue. */
737 /** Used by the fetch unit to get a hold of the instruction port. */
741 return this->fetch.getInstPort();
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| H A D | thread_context.hh | 98 return cpu->fetch.decoder[thread->threadId()];
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| H A D | fetch_impl.hh | 64 #include "cpu/o3/fetch.hh"
113 fatal("fetch buffer size (%u bytes) is greater than the cache "
117 "fetch buffer (%u bytes)\n", cacheBlkSize, fetchBufferSize);
119 // Figure out fetch policy
156 return cpu->name() + ".fetch";
175 .desc("Number of cycles fetch is stalled on an Icache miss")
180 .desc("Number of instructions fetch has processed")
185 .desc("Number of branches that fetch encountered")
190 .desc("Number of branches that fetch has predicted taken")
195 .desc("Number of cycles fetch ha
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| /gem5/src/cpu/minor/ |
| H A D | fetch1.hh | 64 /** Exposable fetch port */
69 Fetch1 &fetch; member in class:Minor::Fetch1::IcachePort
73 MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
78 { return fetch.recvTimingResp(pkt); }
80 void recvReqRetry() { fetch.recvReqRetry(); }
106 /** Owning fetch unit */
107 Fetch1 &fetch; member in class:Minor::Fetch1::FetchRequest
132 /** The underlying request that this fetch represents */
138 /** Fill in a fault if one happens during fetch, check this by
172 fetch(fetch
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| H A D | fetch1.cc | 132 panic("Unknown fetch policy");
155 /* Use a lower, sizeof(MachInst) aligned address for the fetch */
167 DPRINTF(Fetch, "Inserting fetch into the fetch queue "
246 fetch.handleTLBResponse(this);
249 fetch.cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
317 DPRINTF(Fetch, "Not advancing line fetch\n");
345 DPRINTF(Fetch, "Issued fetch request to memory: %s\n",
351 DPRINTF(Fetch, "Line fetch needs to retry: %s\n",
396 /** Print the appropriate MinorLine line for a fetch respons
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| /gem5/src/gpu-compute/ |
| H A D | fetch_unit.hh | 63 void fetch(PacketPtr pkt, Wavefront *wavefront);
73 // the fetch queue for instruction fetching.
82 // Stores the fetch status of all waves dispatched to this SIMD.
83 // TRUE implies the wave is ready to fetch and is already
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| H A D | fetch_stage.hh | 45 // Instruction fetch stage.
47 // need to fetch instructions. From the fetch eligible waves,
48 // one wave is selected from each SIMD and fetch is initiated
62 void fetch(PacketPtr pkt, Wavefront *wave);
73 // List of fetch units. A fetch unit is
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| H A D | fetch_stage.cc | 93 FetchStage::fetch(PacketPtr pkt, Wavefront *wavefront) function in class:FetchStage
95 fetchUnit[wavefront->simdId].fetch(pkt, wavefront);
104 .desc("For each instruction fetch request recieved record how many "
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| H A D | fetch_unit.cc | 84 // re-evaluate waves which are marked as not ready for fetch
118 // calculate the virtual address to fetch from the SQC
132 DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Initiating fetch translation: %#x\n",
201 // fetch the instructions from the SQC when we operate in
203 fetch(pkt, wavefront);
208 FetchUnit::fetch(PacketPtr pkt, Wavefront *wavefront) function in class:FetchUnit
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| H A D | compute_unit.hh | 257 void fetch(PacketPtr pkt, Wavefront *wavefront);
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| H A D | compute_unit.cc | 1342 // pkt is reused in fetch(), don't delete it here. However, we must
1348 computeUnit->fetchStage.fetch(pkt, wavefront);
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| /gem5/src/mem/cache/prefetch/ |
| H A D | base.cc | 129 bool fetch = pkt->req->isInstFetch(); local
134 if (fetch && !onInst) return false;
135 if (!fetch && !onData) return false;
136 if (!fetch && read && !onRead) return false;
137 if (!fetch && !read && !onWrite) return false;
138 if (!fetch && !read && inv) return false;
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| /gem5/src/systemc/tests/systemc/misc/sim_tests/simple_cpu/ |
| H A D | simple_cpu.cpp | 189 SC_MODULE( fetch )
191 SC_HAS_PROCESS( fetch );
198 fetch( sc_module_name NAME, function
230 void fetch::entry()
245 fetch F("F", pc, instr);
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| /gem5/ext/systemc/src/sysc/utils/ |
| H A D | sc_pvector.h | 108 T& fetch( int i ) function in class:sc_core::sc_pvector
111 const T& fetch( int i ) const function in class:sc_core::sc_pvector
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| /gem5/src/arch/x86/ |
| H A D | faults.hh | 312 Bitfield<4> fetch; member in class:X86ISA::PageFault
331 code.fetch = (mode == BaseTLB::Execute);
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| H A D | faults.cc | 159 if (code.fetch)
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| /gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
| H A D | ma_fetch.S | 7 # Test misaligned fetch trap.
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| /gem5/configs/example/ |
| H A D | hmctest.py | 31 instruction fetch traces using elastic trace\
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| /gem5/src/cpu/simple/ |
| H A D | timing.hh | 298 void fetch();
348 * <li>A fetch event is scheduled. Normally this would never be the
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| H A D | timing.cc | 82 fetchEvent([this]{ fetch(); }, name())
110 // The fetch event can become descheduled if a drain didn't
219 // kick things off by initiating the fetch of the next instruction
654 TimingSimpleCPU::fetch()
701 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
718 // fetch fault: advance directly to next instruction (fault handler)
742 // If the _status is not Idle, schedule an event to fetch the next
747 DPRINTF(SimpleCPU, "Scheduling fetch event after the Fault\n");
765 // kick off fetch of next instruction... callback from icache
768 fetch();
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