cpu/minor/fetch1.hh

64     /** Exposable fetch port */
69         Fetch1 &fetch;
73             MinorCPU::MinorCPUPort(name, cpu), fetch(fetch_)
78         { return fetch.recvTimingResp(pkt); }
80         void recvReqRetry() { fetch.recvReqRetry(); }
106         /** Owning fetch unit */
107         Fetch1 &fetch;
132         /** The underlying request that this fetch represents */
138         /** Fill in a fault if one happens during fetch, check this by
172             fetch(fetch_),
213     /** Maximum fetch width in bytes.  Setting this (and lineSnap) to the
225     /** State of memory access for head instruction fetch */
233         FetchRunning /* Try to fetch, when possible */
261          *  prediction targets from Fetch2 and by incrementing it as we fetch
266          *  used to tag instructions by the fetch stream to which they belong.
271          *  or Fetch2 ask for a change of fetch address and is used to tag lines
286     /** State of memory access for head instruction fetch */
307     /** Sequence number for line fetch used for ordering lines to flush */
341      *  fetch from. */
344     /** Insert a line fetch into the requests.  This can be a partial
349     /** Try and issue a fetch for a translated request at the
355      *  the memory system.  Returns true if the fetch was successfully
376     /** Print the appropriate MinorLine line for a fetch response */