cpu/o3/fetch_impl.hh

64 #include "cpu/o3/fetch.hh"
113         fatal("fetch buffer size (%u bytes) is greater than the cache "
117               "fetch buffer (%u bytes)\n", cacheBlkSize, fetchBufferSize);
119     // Figure out fetch policy
156     return cpu->name() + ".fetch";
175         .desc("Number of cycles fetch is stalled on an Icache miss")
180         .desc("Number of instructions fetch has processed")
185         .desc("Number of branches that fetch encountered")
190         .desc("Number of branches that fetch has predicted taken")
195         .desc("Number of cycles fetch has run and was not squashing or"
201         .desc("Number of cycles fetch has spent squashing")
206         .desc("Number of cycles fetch has spent waiting for tlb")
211         .desc("Number of cycles fetch was idle")
216         .desc("Number of cycles fetch has spent blocked")
226         .desc("Number of cycles fetch has spent waiting on interrupts, or "
232         .desc("Number of cycles fetch has spent waiting on pipes to drain")
237         .desc("Number of stall cycles due to no active thread to fetch from")
275         .desc("Percent of cycles fetch was idle")
316     // Create wire to write information to proper place in fetch time buf.
412     DPRINTF(Activity, "[tid:%i] Activating fetch due to cache completion\n",
470         // Verify fetch queues are drained
613         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, cache blocked\n",
617         // Hold off fetch from getting new instructions when:
620         // fetch is switched out.
621         DPRINTF(Fetch, "[tid:%i] Can't fetch cache line, interrupt pending\n",
626     // Align the fetch address to the start of a fetch buffer segment.
680             warn("Address %#x is outside of physical memory, stopping fetch\n",
713             // Notify Fetch Request probe when a packet containing a fetch
798     // Empty fetch queue
822     // fetch and decode.
860                     DPRINTF(Activity, "[tid:%i] Activating fetch due to cache"
933         fetch(status_change);
940         // Change the fetch stage status if there was a status change.
951     // Send instructions enqueued into the fetch queue to decode.
972                     "from fetch queue. Fetch queue size: %i.\n",
1087         // Switch status to running if fetch isn't being told to block or
1098     // cause fetch to change its status.  Fetch remains the same as before.
1158 DefaultFetch<Impl>::fetch(bool &status_change)
1161     // Start actual fetch
1178     DPRINTF(Fetch, "Attempting to fetch from [tid:%i]\n", tid);
1197         // Align the fetch PC so its at the start of a fetch buffer segment.
1202         // from a macro-op, then start fetch from icache.
1231         // Status is Idle, so fetch should do nothing.
1250     // ended this fetch block.
1253     // Need to halt fetch if quiesce instruction detected
1277             // to the next cache block then start fetch from icache.
1372                         "Quiesce instruction encountered, halting fetch!\n");
1382         // Re-evaluate whether the next instruction to fetch is in micro-op ROM
1391         DPRINTF(Fetch, "[tid:%i] Done fetching, reached fetch bandwidth "
1395                 "fetch buffer.\n", tid);
1407     // pipeline a fetch if we're crossing a fetch buffer boundary and not in
1615     // Align the fetch PC so its at the start of a fetch buffer segment.
1618     // Unless buffer already got the block, fetch it from icache.
1630     DPRINTF(Fetch,"There are no more threads available to fetch from.\n");
1670         DPRINTF(Fetch, "[tid:%i] Unexpected fetch stall reason "
1684     fetch->processCacheCompletion(pkt);
1693     fetch->recvReqRetry();