cpu/o3/fetch.hh

66  * DefaultFetch class handles both single threaded and SMT fetch. Its
67  * width is specified by the parameters; each cycle it tries to fetch
91      * IcachePort class for instruction fetch.
96         /** Pointer to fetch. */
97         DefaultFetch<Impl> *fetch;
102             : MasterPort(_cpu->name() + ".icache_port", _cpu), fetch(_fetch)
107         /** Timing version of receive.  Handles setting fetch to the
111         /** Handles doing a retry of a failed fetch. */
118         DefaultFetch<Impl> *fetch;
122             : fetch(_fetch)
134             fetch->finishTranslation(fault, req);
140     /* Event to delay delivery of a fetch translation result in case of
146         DefaultFetch<Impl> *fetch;
152             : fetch(_fetch), req(nullptr)
168             assert(fetch->numInst < fetch->fetchWidth);
169             fetch->finishTranslation(fault, req);
179     /** Overall fetch status. Used to determine if the CPU can
218     /** To probe when a fetch request is successfully sent. */
225     /** Returns the name of fetch. */
249     /** Handles retrying the fetch access. */
268      * Stall the fetch stage after reaching a safe drain point.
278     /** Tells fetch to wake up from a quiesce instruction. */
281     /** For priority-based fetch policies, need to keep update priorityList */
309      * Fetches the cache line that contains the fetch PC.  Returns any
336      * remove any instructions between fetch and decode that should be sqaushed.
345     /** Updates overall fetch stage status; to be called at the end of each
357     /** Ticks the fetch stage, processing all inputs signals and fetching
369      * @param status_change fetch() sets this variable if there was a status
372     void fetch(bool &status_change);
374     /** Align a PC to the start of a fetch buffer block. */
390     /** Returns the appropriate thread to fetch, given the fetch policy. */
393     /** Returns the appropriate thread to fetch using a round robin policy. */
396     /** Returns the appropriate thread to fetch using the IQ count policy. */
399     /** Returns the appropriate thread to fetch using the LSQ count policy. */
402     /** Returns the appropriate thread to fetch using the branch count
409     /** Profile the reasons of fetch stall. */
444     /** Can the fetch stage redirect from an interrupt on this instruction? */
450     /** Variable that tracks if fetch has written to the time buffer this
464     /** Tracks which stages are telling fetch to stall. */
467     /** Decode to fetch delay. */
470     /** Rename to fetch delay. */
473     /** IEW to fetch delay. */
476     /** Commit to fetch delay. */
479     /** The width of fetch in instructions. */
491     /** The thread that is waiting on the cache to tell fetch to retry. */
497     /** The size of the fetch buffer in bytes. The fetch buffer
502     /** Mask to align a fetch address to a fetch buffer boundary. */
505     /** The fetch data that is being fetched and buffered. */
508     /** The PC of the first instruction loaded into the fetch buffer. */
511     /** The size of the fetch queue in micro-ops */
517     /** Whether or not the fetch buffer data is valid. */
538     /** Checks if there is an interrupt pending.  If there is, fetch
543     /** Instruction port. Note that it has to appear after the fetch stage. */
597     /** Rate of how often fetch was idle. */