Searched refs:CPSR (Results 1 - 25 of 26) sorted by relevance

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/gem5/src/arch/arm/
H A Dutility.hh121 inUserMode(CPSR cpsr)
133 inPrivilegedMode(CPSR cpsr)
149 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
160 currEL(CPSR cpsr)
216 itState(CPSR psr)
237 inSecureState(SCR scr, CPSR cpsr)
324 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
327 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
355 CPSR cpsr, SCR scr, NSACR nsacr,
H A Dinterrupts.hh143 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
176 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const
191 getISR(HCR hcr, CPSR cpsr, SCR scr)
194 CPSR isr = 0; // ARM ARM states ISR reg uses same bit possitions as CPSR
206 * Check the state of a particular interrupt, ignoring CPSR masks.
230 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dfaults.cc301 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
426 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
500 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
525 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
644 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
645 CPSR spsr = cpsr;
730 CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
757 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
800 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
849 CPSR cps
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H A Disa.cc217 CPSR cpsr = 0;
269 CPSR cpsr = 0;
292 // Initialize rest of CPSR
454 CPSR cpsr = 0;
623 CPSR cpsr = 0;
631 CPSR cpsr = 0;
632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
786 CPSR old_cpsr = miscRegs[MISCREG_CPSR];
788 CPSR cpsr = val;
798 DPRINTF(Arm, "Updating CPSR fro
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H A Dutility.cc214 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
340 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
472 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr,
652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr,
701 CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity)
H A Disa.hh381 updateRegMap(CPSR cpsr)
413 panic("Unrecognized mode setting in CPSR.\n");
424 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
429 CPSR cpsr M5_VAR_USED = readMiscReg(MISCREG_CPSR, tc);
481 CPSR cpsr = miscRegs[MISCREG_CPSR];
546 CPSR cpsr = miscRegs[MISCREG_CPSR];
683 // upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD (no-op)
716 CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
H A Dinterrupts.cc57 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dmiscregs.hh1871 // This mask selects bits of the CPSR that actually go in the CondCodes
1877 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1880 // Bit[9] returns the value of CPSR.E.
1881 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1884 // CPSR (Current Program Status Register Mask).
1905 * @param the CPSR
1909 CPSR cpsr);
1921 * @param the CPSR
1925 CPSR cps
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H A Dtlb.hh148 static ExceptionLevel tranTypeEL(CPSR cpsr, ArmTranslationType type);
411 CPSR cpsr;
H A Dnativetrace.cc118 //CPSR
119 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dmiscregs_types.hh51 BitUnion32(CPSR)
75 EndBitUnion(CPSR)
H A Dprocess.cc130 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
H A Dpmu.cc501 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
H A Dtable_walker.hh733 CPSR cpsr;
H A Dmiscregs.cc989 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1025 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr)
1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
/gem5/src/arch/arm/insts/
H A Dstatic_inst.hh203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr,
267 warn_once("Illegal change to CPSR mode attempted\n");
270 warn_once("Ignoring write of bad mode to CPSR.\n");
402 Fault checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const;
412 CPSR cpsr, CPACR cpacr) const;
421 CPSR cpsr, CPACR cpacr,
446 Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const;
454 Fault checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const;
482 Fault checkSveTrap(ThreadContext *tc, CPSR cpsr) const;
487 Fault checkSveEnabled(ThreadContext *tc, CPSR cps
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H A Dstatic_inst.cc668 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
687 CPSR cpsr, CPACR cpacr) const
699 CPSR cpsr, CPACR cpacr,
875 CPSR cpsr, SCR scr,
901 ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
989 ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const
1009 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1021 getRestoredITBits(ThreadContext *tc, CPSR spsr)
1050 illegalExceptionReturn(ThreadContext *tc, CPSR cpsr, CPSR sps
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H A Dmisc64.cc149 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
377 const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
/gem5/util/statetrace/arch/arm/
H A Dtracechild.hh69 CPSR, enumerator in enum:ARMTraceChild::RegNum
H A Dtracechild.cc68 assert(sizeof(regs.uregs)/sizeof(regs.uregs[0]) > CPSR);
105 assert(num <= CPSR && num >= 0);
146 if (num <= CPSR)
155 if (num <= CPSR)
/gem5/src/arch/arm/tracers/
H A Dtarmac_base.cc75 // Operating mode gained by reading the architectural register (CPSR)
76 const CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
H A Dtarmac_record.cc200 // If it is the CPSR:
201 // update the value of the CPSR register and add
204 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
249 // Reading operating mode from CPSR.
252 CPSR cpsr = thread->readMiscRegNoEffect(MISCREG_CPSR);
328 // Gem5 is treating CPSR flags as separate registers (CC registers),
330 // entries altogether with the CPSR register and produce a single entry.
H A Dtarmac_parser.cc685 CPSR cpsr = thread->readMiscRegNoEffect(it->index);
692 CPSR cpsr = 0;
/gem5/src/arch/arm/kvm/
H A Darmv8_cpu.cc221 CPSR cpsr(tc->readMiscReg(MISCREG_CPSR));
287 const CPSR cpsr(getOneRegU64(INT_REG(regs.pstate)));
/gem5/src/dev/arm/
H A Dgic_v3_cpu_interface.cc2331 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2339 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2391 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
2399 CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);

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