1/*
2 * Copyright (c) 2010, 2012, 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 *          Ali Saidi
42 */
43
44#include "arch/arm/process.hh"
45
46#include "arch/arm/isa_traits.hh"
47#include "arch/arm/types.hh"
48#include "base/loader/elf_object.hh"
49#include "base/loader/object_file.hh"
50#include "base/logging.hh"
51#include "cpu/thread_context.hh"
52#include "debug/Stack.hh"
53#include "mem/page_table.hh"
54#include "params/Process.hh"
55#include "sim/aux_vector.hh"
56#include "sim/byteswap.hh"
57#include "sim/process_impl.hh"
58#include "sim/syscall_return.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace ArmISA;
63
64ArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile,
65                       ObjectFile::Arch _arch)
66    : Process(params,
67              new EmulationPageTable(params->name, params->pid, PageBytes),
68              objFile),
69      arch(_arch)
70{
71    fatal_if(params->useArchPT, "Arch page tables not implemented.");
72}
73
74ArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile,
75                           ObjectFile::Arch _arch)
76    : ArmProcess(params, objFile, _arch)
77{
78    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
79                             objFile->bssSize(), PageBytes);
80    Addr stack_base = 0xbf000000L;
81    Addr max_stack_size = 8 * 1024 * 1024;
82    Addr next_thread_stack_base = stack_base - max_stack_size;
83    Addr mmap_end = 0x40000000L;
84
85    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
86                                     next_thread_stack_base, mmap_end);
87}
88
89ArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
90                           ObjectFile::Arch _arch)
91    : ArmProcess(params, objFile, _arch)
92{
93    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
94                             objFile->bssSize(), PageBytes);
95    Addr stack_base = 0x7fffff0000L;
96    Addr max_stack_size = 8 * 1024 * 1024;
97    Addr next_thread_stack_base = stack_base - max_stack_size;
98    Addr mmap_end = 0x4000000000L;
99
100    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
101                                     next_thread_stack_base, mmap_end);
102}
103
104void
105ArmProcess32::initState()
106{
107    Process::initState();
108    argsInit<uint32_t>(PageBytes, INTREG_SP);
109    for (int i = 0; i < contextIds.size(); i++) {
110        ThreadContext * tc = system->getThreadContext(contextIds[i]);
111        CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
112        // Enable the floating point coprocessors.
113        cpacr.cp10 = 0x3;
114        cpacr.cp11 = 0x3;
115        tc->setMiscReg(MISCREG_CPACR, cpacr);
116        // Generically enable floating point support.
117        FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
118        fpexc.en = 1;
119        tc->setMiscReg(MISCREG_FPEXC, fpexc);
120    }
121}
122
123void
124ArmProcess64::initState()
125{
126    Process::initState();
127    argsInit<uint64_t>(PageBytes, INTREG_SP0);
128    for (int i = 0; i < contextIds.size(); i++) {
129        ThreadContext * tc = system->getThreadContext(contextIds[i]);
130        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
131        cpsr.mode = MODE_EL0T;
132        tc->setMiscReg(MISCREG_CPSR, cpsr);
133        CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
134        // Enable the floating point coprocessors.
135        cpacr.cp10 = 0x3;
136        cpacr.cp11 = 0x3;
137        // Enable SVE.
138        cpacr.zen = 0x3;
139        tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
140        // Generically enable floating point support.
141        FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
142        fpexc.en = 1;
143        tc->setMiscReg(MISCREG_FPEXC, fpexc);
144    }
145}
146
147uint32_t
148ArmProcess32::armHwcapImpl() const
149{
150    enum ArmCpuFeature {
151        Arm_Swp = 1 << 0,
152        Arm_Half = 1 << 1,
153        Arm_Thumb = 1 << 2,
154        Arm_26Bit = 1 << 3,
155        Arm_FastMult = 1 << 4,
156        Arm_Fpa = 1 << 5,
157        Arm_Vfp = 1 << 6,
158        Arm_Edsp = 1 << 7,
159        Arm_Java = 1 << 8,
160        Arm_Iwmmxt = 1 << 9,
161        Arm_Crunch = 1 << 10,
162        Arm_ThumbEE = 1 << 11,
163        Arm_Neon = 1 << 12,
164        Arm_Vfpv3 = 1 << 13,
165        Arm_Vfpv3d16 = 1 << 14
166    };
167
168    return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
169           Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
170           Arm_Vfpv3 | Arm_Vfpv3d16;
171}
172
173uint32_t
174ArmProcess64::armHwcapImpl() const
175{
176    // In order to know what these flags mean, please refer to Linux
177    // /Documentation/arm64/elf_hwcaps.txt text file.
178    enum ArmCpuFeature {
179        Arm_Fp = 1 << 0,
180        Arm_Asimd = 1 << 1,
181        Arm_Evtstrm = 1 << 2,
182        Arm_Aes = 1 << 3,
183        Arm_Pmull = 1 << 4,
184        Arm_Sha1 = 1 << 5,
185        Arm_Sha2 = 1 << 6,
186        Arm_Crc32 = 1 << 7,
187        Arm_Atomics = 1 << 8,
188        Arm_Fphp = 1 << 9,
189        Arm_Asimdhp = 1 << 10,
190        Arm_Cpuid = 1 << 11,
191        Arm_Asimdrdm = 1 << 12,
192        Arm_Jscvt = 1 << 13,
193        Arm_Fcma = 1 << 14,
194        Arm_Lrcpc = 1 << 15,
195        Arm_Dcpop = 1 << 16,
196        Arm_Sha3 = 1 << 17,
197        Arm_Sm3 = 1 << 18,
198        Arm_Sm4 = 1 << 19,
199        Arm_Asimddp = 1 << 20,
200        Arm_Sha512 = 1 << 21,
201        Arm_Sve = 1 << 22,
202        Arm_Asimdfhm = 1 << 23,
203        Arm_Dit = 1 << 24,
204        Arm_Uscat = 1 << 25,
205        Arm_Ilrcpc = 1 << 26,
206        Arm_Flagm = 1 << 27
207    };
208
209    uint32_t hwcap = 0;
210
211    ThreadContext *tc = system->getThreadContext(contextIds[0]);
212
213    const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
214
215    hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0;
216    hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0;
217    hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0;
218    hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0;
219    hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0;
220    hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0;
221
222    const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
223
224    hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
225    hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
226    hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
227    hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
228    hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
229    hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
230    hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
231    hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
232    hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
233    hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
234    hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
235    hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
236    hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
237    hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;
238
239    const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
240
241    hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0;
242    hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0;
243    hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
244    hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
245    hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
246
247    const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
248
249    hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0;
250
251    return hwcap;
252}
253
254template <class IntType>
255void
256ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
257{
258    int intSize = sizeof(IntType);
259
260    std::vector<AuxVector<IntType>> auxv;
261
262    string filename;
263    if (argv.size() < 1)
264        filename = "";
265    else
266        filename = argv[0];
267
268    //We want 16 byte alignment
269    uint64_t align = 16;
270
271    // Patch the ld_bias for dynamic executables.
272    updateBias();
273
274    // load object file into target memory
275    objFile->loadSections(initVirtMem);
276
277    //Setup the auxilliary vectors. These will already have endian conversion.
278    //Auxilliary vectors are loaded only for elf formatted executables.
279    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
280    if (elfObject) {
281
282        if (objFile->getOpSys() == ObjectFile::Linux) {
283            IntType features = armHwcap<IntType>();
284
285            //Bits which describe the system hardware capabilities
286            //XXX Figure out what these should be
287            auxv.emplace_back(M5_AT_HWCAP, features);
288            //Frequency at which times() increments
289            auxv.emplace_back(M5_AT_CLKTCK, 0x64);
290            //Whether to enable "secure mode" in the executable
291            auxv.emplace_back(M5_AT_SECURE, 0);
292            // Pointer to 16 bytes of random data
293            auxv.emplace_back(M5_AT_RANDOM, 0);
294            //The filename of the program
295            auxv.emplace_back(M5_AT_EXECFN, 0);
296            //The string "v71" -- ARM v7 architecture
297            auxv.emplace_back(M5_AT_PLATFORM, 0);
298        }
299
300        //The system page size
301        auxv.emplace_back(M5_AT_PAGESZ, ArmISA::PageBytes);
302        // For statically linked executables, this is the virtual address of
303        // the program header tables if they appear in the executable image
304        auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
305        // This is the size of a program header entry from the elf file.
306        auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
307        // This is the number of program headers from the original elf file.
308        auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
309        // This is the base address of the ELF interpreter; it should be
310        // zero for static executables or contain the base address for
311        // dynamic executables.
312        auxv.emplace_back(M5_AT_BASE, getBias());
313        //XXX Figure out what this should be.
314        auxv.emplace_back(M5_AT_FLAGS, 0);
315        //The entry point to the program
316        auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
317        //Different user and group IDs
318        auxv.emplace_back(M5_AT_UID, uid());
319        auxv.emplace_back(M5_AT_EUID, euid());
320        auxv.emplace_back(M5_AT_GID, gid());
321        auxv.emplace_back(M5_AT_EGID, egid());
322    }
323
324    //Figure out how big the initial stack nedes to be
325
326    // A sentry NULL void pointer at the top of the stack.
327    int sentry_size = intSize;
328
329    string platform = "v71";
330    int platform_size = platform.size() + 1;
331
332    // Bytes for AT_RANDOM above, we'll just keep them 0
333    int aux_random_size = 16; // as per the specification
334
335    // The aux vectors are put on the stack in two groups. The first group are
336    // the vectors that are generated as the elf is loaded. The second group
337    // are the ones that were computed ahead of time and include the platform
338    // string.
339    int aux_data_size = filename.size() + 1;
340
341    int env_data_size = 0;
342    for (int i = 0; i < envp.size(); ++i) {
343        env_data_size += envp[i].size() + 1;
344    }
345    int arg_data_size = 0;
346    for (int i = 0; i < argv.size(); ++i) {
347        arg_data_size += argv[i].size() + 1;
348    }
349
350    int info_block_size =
351        sentry_size + env_data_size + arg_data_size +
352        aux_data_size + platform_size + aux_random_size;
353
354    //Each auxilliary vector is two 4 byte words
355    int aux_array_size = intSize * 2 * (auxv.size() + 1);
356
357    int envp_array_size = intSize * (envp.size() + 1);
358    int argv_array_size = intSize * (argv.size() + 1);
359
360    int argc_size = intSize;
361
362    //Figure out the size of the contents of the actual initial frame
363    int frame_size =
364        info_block_size +
365        aux_array_size +
366        envp_array_size +
367        argv_array_size +
368        argc_size;
369
370    //There needs to be padding after the auxiliary vector data so that the
371    //very bottom of the stack is aligned properly.
372    int partial_size = frame_size;
373    int aligned_partial_size = roundUp(partial_size, align);
374    int aux_padding = aligned_partial_size - partial_size;
375
376    int space_needed = frame_size + aux_padding;
377
378    memState->setStackMin(memState->getStackBase() - space_needed);
379    memState->setStackMin(roundDown(memState->getStackMin(), align));
380    memState->setStackSize(memState->getStackBase() - memState->getStackMin());
381
382    // map memory
383    allocateMem(roundDown(memState->getStackMin(), pageSize),
384                          roundUp(memState->getStackSize(), pageSize));
385
386    // map out initial stack contents
387    IntType sentry_base = memState->getStackBase() - sentry_size;
388    IntType aux_data_base = sentry_base - aux_data_size;
389    IntType env_data_base = aux_data_base - env_data_size;
390    IntType arg_data_base = env_data_base - arg_data_size;
391    IntType platform_base = arg_data_base - platform_size;
392    IntType aux_random_base = platform_base - aux_random_size;
393    IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
394    IntType envp_array_base = auxv_array_base - envp_array_size;
395    IntType argv_array_base = envp_array_base - argv_array_size;
396    IntType argc_base = argv_array_base - argc_size;
397
398    DPRINTF(Stack, "The addresses of items on the initial stack:\n");
399    DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
400    DPRINTF(Stack, "0x%x - env data\n", env_data_base);
401    DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
402    DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
403    DPRINTF(Stack, "0x%x - platform base\n", platform_base);
404    DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
405    DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
406    DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
407    DPRINTF(Stack, "0x%x - argc \n", argc_base);
408    DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
409
410    // write contents to stack
411
412    // figure out argc
413    IntType argc = argv.size();
414    IntType guestArgc = ArmISA::htog(argc);
415
416    //Write out the sentry void *
417    IntType sentry_NULL = 0;
418    initVirtMem.writeBlob(sentry_base, &sentry_NULL, sentry_size);
419
420    //Fix up the aux vectors which point to other data
421    for (int i = auxv.size() - 1; i >= 0; i--) {
422        if (auxv[i].type == M5_AT_PLATFORM) {
423            auxv[i].val = platform_base;
424            initVirtMem.writeString(platform_base, platform.c_str());
425        } else if (auxv[i].type == M5_AT_EXECFN) {
426            auxv[i].val = aux_data_base;
427            initVirtMem.writeString(aux_data_base, filename.c_str());
428        } else if (auxv[i].type == M5_AT_RANDOM) {
429            auxv[i].val = aux_random_base;
430            // Just leave the value 0, we don't want randomness
431        }
432    }
433
434    //Copy the aux stuff
435    Addr auxv_array_end = auxv_array_base;
436    for (const auto &aux: auxv) {
437        initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
438        auxv_array_end += sizeof(aux);
439    }
440    //Write out the terminating zeroed auxillary vector
441    const AuxVector<IntType> zero(0, 0);
442    initVirtMem.write(auxv_array_end, zero);
443    auxv_array_end += sizeof(zero);
444
445    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
446    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
447
448    initVirtMem.writeBlob(argc_base, &guestArgc, intSize);
449
450    ThreadContext *tc = system->getThreadContext(contextIds[0]);
451    //Set the stack pointer register
452    tc->setIntReg(spIndex, memState->getStackMin());
453    //A pointer to a function to run when the program exits. We'll set this
454    //to zero explicitly to make sure this isn't used.
455    tc->setIntReg(ArgumentReg0, 0);
456    //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
457    if (argv.size() > 0) {
458        tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
459                                    argv[argv.size() - 1].size() - 1);
460    } else {
461        tc->setIntReg(ArgumentReg1, 0);
462    }
463    if (envp.size() > 0) {
464        tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
465                                    envp[envp.size() - 1].size() - 1);
466    } else {
467        tc->setIntReg(ArgumentReg2, 0);
468    }
469
470    PCState pc;
471    pc.thumb(arch == ObjectFile::Thumb);
472    pc.nextThumb(pc.thumb());
473    pc.aarch64(arch == ObjectFile::Arm64);
474    pc.nextAArch64(pc.aarch64());
475    pc.set(getStartPC() & ~mask(1));
476    tc->pcState(pc);
477
478    //Align the "stackMin" to a page boundary.
479    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
480}
481
482RegVal
483ArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
484{
485    assert(i < 6);
486    return tc->readIntReg(ArgumentReg0 + i++);
487}
488
489RegVal
490ArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
491{
492    assert(i < 8);
493    return tc->readIntReg(ArgumentReg0 + i++);
494}
495
496RegVal
497ArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
498{
499    assert(width == 32 || width == 64);
500    if (width == 32)
501        return getSyscallArg(tc, i);
502
503    // 64 bit arguments are passed starting in an even register
504    if (i % 2 != 0)
505       i++;
506
507    // Registers r0-r6 can be used
508    assert(i < 5);
509    uint64_t val;
510    val = tc->readIntReg(ArgumentReg0 + i++);
511    val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
512    return val;
513}
514
515RegVal
516ArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
517{
518    return getSyscallArg(tc, i);
519}
520
521
522void
523ArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val)
524{
525    assert(i < 6);
526    tc->setIntReg(ArgumentReg0 + i, val);
527}
528
529void
530ArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
531{
532    assert(i < 8);
533    tc->setIntReg(ArgumentReg0 + i, val);
534}
535
536void
537ArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
538{
539
540    if (objFile->getOpSys() == ObjectFile::FreeBSD) {
541        // Decode return value
542        if (sysret.encodedValue() >= 0)
543            // FreeBSD checks the carry bit to determine if syscall is succeeded
544            tc->setCCReg(CCREG_C, 0);
545        else {
546            sysret = -sysret.encodedValue();
547        }
548    }
549
550    tc->setIntReg(ReturnValueReg, sysret.encodedValue());
551}
552
553void
554ArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
555{
556
557    if (objFile->getOpSys() == ObjectFile::FreeBSD) {
558        // Decode return value
559        if (sysret.encodedValue() >= 0)
560            // FreeBSD checks the carry bit to determine if syscall is succeeded
561            tc->setCCReg(CCREG_C, 0);
562        else {
563            sysret = -sysret.encodedValue();
564        }
565    }
566
567    tc->setIntReg(ReturnValueReg, sysret.encodedValue());
568}
569