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14128:6ed23d07d0d1 |
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28-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement ARMv8.1-PAN, Privileged access never
ARMv8.1-PAN adds a new bit to PSTATE. When the value of this PAN state bit is 1, any privileged data access from EL1 or EL2 to a virtual memory address that is accessible at EL0 generates a Permission fault. This feature is mandatory in ARMv8.1 implementations. This feature is supported in AArch64 and AArch32 states. The ID_AA64MMFR1_EL1.PAN, ID_MMFR3_EL1.PAN, and ID_MMFR3.PAN fields identify the support for ARMv8.1-PAN.
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Change-Id: I94a76311711739dd2394c72944d88ba9321fd159 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19729 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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14094:921238acf537 |
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18-Jul-2019 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Add HPD bit for TCR_EL2/EL3
This is controlling Hierarchical Permissions for EL3 and for EL2 when HCR_EL2.E2H = 0.
Change-Id: I9d6615ff4980cc56a28dc32088cf1524155f0fa4 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19609 Tested-by: kokoro <noreply+kokoro@google.com>
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13759:9941fca869a9 |
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16-Oct-2018 |
Giacomo Gabrielli <giacomo.gabrielli@arm.com> |
arch-arm,cpu: Add initial support for Arm SVE
This changeset adds initial support for the Arm Scalable Vector Extension (SVE) by implementing: - support for most data-processing instructions (no loads/stores yet); - basic system-level support.
Additional authors: - Javier Setoain <javier.setoain@arm.com> - Gabor Dozsa <gabor.dozsa@arm.com> - Giacomo Travaglini <giacomo.travaglini@arm.com>
Thanks to Pau Cabre for his contribution of bugfixes.
Change-Id: I1808b5ff55b401777eeb9b99c9a1129e0d527709 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/13515 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13528:f37f2da0513b |
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20-Dec-2018 |
Ivan Pizarro <ivan.pizarro@metempsy.com> |
arch-arm: Additional bits in misc ARM registers to use with the TLB and page walker
Change-Id: I71a6360709b35ad788d8c88fba1a7a2761233dbd Reviewed-on: https://gem5-review.googlesource.com/c/14555 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13394:ebe487b6f18a |
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02-Nov-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Remove SCTLR.VE bit
ARMv8 has removed SCTLR.VE bit which is now hardcoded to 0. We are removing it from gem5 since we were not handling it anyway.
Change-Id: Ibde2db45c7f8add4a3188f2cb8c23701a6088d03 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/13998 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13118:897ff5214d07 |
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10-Nov-2017 |
Edmund Grimley Evans <Edmund.Grimley-Evans@arm.com> |
arch-arm: Add FP16 support and other primitives to fplib
This changeset: - extends fplib to support emulation of half-precision floating-point (FP16) operations; - extends fplib to support additional primitives introduced by the Arm Scalable Vector Extension (SVE) (fplibExpa, fplibScale, fplibTrigMAdd, fplibTrigSMul, fplibTrigSSel); - adds the FZ16 bit to FPSCR; - cleans up fplib code by replacing constants with preprocessor macros and by adding inline functions to recognise NaNs and infinities.
Change-Id: If8fdb2a5824b478c8310bbc126ec60cc1105f135 Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13044 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13117:59959c5d7438 |
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25-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Implement AArch64 ID regs as bitunions
This patch is implementing the following AArch64 ID registers as bitunions, so that it is easier to query for feature availability:
- ID_AA64DFR0_EL1 - ID_AA64ISAR0_EL1 - ID_AA64ISAR1_EL1 - ID_AA64MMFR1_EL1 - ID_AA64MMFR2_EL1 - ID_AA64PFR0_EL1
They are updated to the latest Armv8.5 arch release version. RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added.
Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13067 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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13115:e056f29e1994 |
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25-Sep-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
arch-arm: Move MiscReg BitUnions into a separate header file
As the number of MiscRegs increases there is the need of a cleaner header file; this patch is separating miscreg.[cc,hh] where the miscreg decoding/utility functions are defined/declared from the MiscReg register types (BitUnion).
Change-Id: I815f53b117b50e47f93aa13d78356ef09d2a2541 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13065 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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