1/* 2 * Copyright (c) 2010-2019 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Gabe Black 41 * Giacomo Gabrielli 42 */ 43 44#ifndef __ARCH_ARM_MISCREGS_TYPES_HH__ 45#define __ARCH_ARM_MISCREGS_TYPES_HH__ 46 47#include "base/bitunion.hh" 48 49namespace ArmISA 50{ 51 BitUnion32(CPSR) 52 Bitfield<31, 30> nz; 53 Bitfield<29> c; 54 Bitfield<28> v; 55 Bitfield<27> q; 56 Bitfield<26, 25> it1; 57 Bitfield<24> j; 58 Bitfield<22> pan; 59 Bitfield<21> ss; // AArch64 60 Bitfield<20> il; // AArch64 61 Bitfield<19, 16> ge; 62 Bitfield<15, 10> it2; 63 Bitfield<9> d; // AArch64 64 Bitfield<9> e; 65 Bitfield<8> a; 66 Bitfield<7> i; 67 Bitfield<6> f; 68 Bitfield<8, 6> aif; 69 Bitfield<9, 6> daif; // AArch64 70 Bitfield<5> t; 71 Bitfield<4> width; // AArch64 72 Bitfield<3, 2> el; // AArch64 73 Bitfield<4, 0> mode; 74 Bitfield<0> sp; // AArch64 75 EndBitUnion(CPSR) 76 77 BitUnion64(AA64DFR0) 78 Bitfield<43, 40> tracefilt; 79 Bitfield<39, 36> doublelock; 80 Bitfield<35, 32> pmsver; 81 Bitfield<31, 28> ctx_cmps; 82 Bitfield<23, 20> wrps; 83 Bitfield<15, 12> brps; 84 Bitfield<11, 8> pmuver; 85 Bitfield<7, 4> tracever; 86 Bitfield<3, 0> debugver; 87 EndBitUnion(AA64DFR0) 88 89 BitUnion64(AA64ISAR0) 90 Bitfield<63, 60> rndr; 91 Bitfield<59, 56> tlb; 92 Bitfield<55, 52> ts; 93 Bitfield<51, 48> fhm; 94 Bitfield<47, 44> dp; 95 Bitfield<43, 40> sm4; 96 Bitfield<39, 36> sm3; 97 Bitfield<35, 32> sha3; 98 Bitfield<31, 28> rdm; 99 Bitfield<23, 20> atomic; 100 Bitfield<19, 16> crc32; 101 Bitfield<15, 12> sha2; 102 Bitfield<11, 8> sha1; 103 Bitfield<3, 0> aes; 104 EndBitUnion(AA64ISAR0) 105 106 BitUnion64(AA64ISAR1) 107 Bitfield<43, 40> specres; 108 Bitfield<39, 36> sb; 109 Bitfield<35, 32> frintts; 110 Bitfield<31, 28> gpi; 111 Bitfield<27, 24> gpa; 112 Bitfield<23, 20> lrcpc; 113 Bitfield<19, 16> fcma; 114 Bitfield<15, 12> jscvt; 115 Bitfield<11, 8> api; 116 Bitfield<7, 4> apa; 117 Bitfield<3, 0> dpb; 118 EndBitUnion(AA64ISAR1) 119 120 BitUnion64(AA64MMFR0) 121 Bitfield<47, 44> exs; 122 Bitfield<43, 40> tgran4_2; 123 Bitfield<39, 36> tgran64_2; 124 Bitfield<35, 32> tgran16_2; 125 Bitfield<31, 28> tgran4; 126 Bitfield<27, 24> tgran64; 127 Bitfield<23, 20> tgran16; 128 Bitfield<19, 16> bigendEL0; 129 Bitfield<15, 12> snsmem; 130 Bitfield<11, 8> bigend; 131 Bitfield<7, 4> asidbits; 132 Bitfield<3, 0> parange; 133 EndBitUnion(AA64MMFR0) 134 135 BitUnion64(AA64MMFR1) 136 Bitfield<31, 28> xnx; 137 Bitfield<27, 24> specsei; 138 Bitfield<23, 20> pan; 139 Bitfield<19, 16> lo; 140 Bitfield<15, 12> hpds; 141 Bitfield<11, 8> vh; 142 Bitfield<7, 4> vmidbits; 143 Bitfield<3, 0> hafdbs; 144 EndBitUnion(AA64MMFR1) 145 146 BitUnion64(AA64MMFR2) 147 Bitfield<63, 60> e0pd; 148 Bitfield<59, 56> evt; 149 Bitfield<55, 52> bbm; 150 Bitfield<51, 48> ttl; 151 Bitfield<43, 40> fwb; 152 Bitfield<39, 36> ids; 153 Bitfield<35, 32> at; 154 Bitfield<31, 28> st; 155 Bitfield<27, 24> nv; 156 Bitfield<23, 20> ccidx; 157 Bitfield<19, 16> varange; 158 Bitfield<15, 12> iesb; 159 Bitfield<11, 8> lsm; 160 Bitfield<7, 4> uao; 161 Bitfield<3, 0> cnp; 162 EndBitUnion(AA64MMFR2) 163 164 BitUnion64(AA64PFR0) 165 Bitfield<63, 60> csv3; 166 Bitfield<59, 56> csv2; 167 Bitfield<51, 48> dit; 168 Bitfield<47, 44> amu; 169 Bitfield<43, 40> mpam; 170 Bitfield<39, 36> sel2; 171 Bitfield<35, 32> sve; 172 Bitfield<31, 28> ras; 173 Bitfield<27, 24> gic; 174 Bitfield<23, 20> advsimd; 175 Bitfield<19, 16> fp; 176 Bitfield<15, 12> el3; 177 Bitfield<11, 8> el2; 178 Bitfield<7, 4> el1; 179 Bitfield<3, 0> el0; 180 EndBitUnion(AA64PFR0) 181 182 BitUnion32(HDCR) 183 Bitfield<11> tdra; 184 Bitfield<10> tdosa; 185 Bitfield<9> tda; 186 Bitfield<8> tde; 187 Bitfield<7> hpme; 188 Bitfield<6> tpm; 189 Bitfield<5> tpmcr; 190 Bitfield<4, 0> hpmn; 191 EndBitUnion(HDCR) 192 193 BitUnion32(HCPTR) 194 Bitfield<31> tcpac; 195 Bitfield<20> tta; 196 Bitfield<15> tase; 197 Bitfield<13> tcp13; 198 Bitfield<12> tcp12; 199 Bitfield<11> tcp11; 200 Bitfield<10> tcp10; 201 Bitfield<10> tfp; // AArch64 202 Bitfield<9> tcp9; 203 Bitfield<8> tcp8; 204 Bitfield<8> tz; // SVE 205 Bitfield<7> tcp7; 206 Bitfield<6> tcp6; 207 Bitfield<5> tcp5; 208 Bitfield<4> tcp4; 209 Bitfield<3> tcp3; 210 Bitfield<2> tcp2; 211 Bitfield<1> tcp1; 212 Bitfield<0> tcp0; 213 EndBitUnion(HCPTR) 214 215 BitUnion32(HSTR) 216 Bitfield<17> tjdbx; 217 Bitfield<16> ttee; 218 Bitfield<15> t15; 219 Bitfield<13> t13; 220 Bitfield<12> t12; 221 Bitfield<11> t11; 222 Bitfield<10> t10; 223 Bitfield<9> t9; 224 Bitfield<8> t8; 225 Bitfield<7> t7; 226 Bitfield<6> t6; 227 Bitfield<5> t5; 228 Bitfield<4> t4; 229 Bitfield<3> t3; 230 Bitfield<2> t2; 231 Bitfield<1> t1; 232 Bitfield<0> t0; 233 EndBitUnion(HSTR) 234 235 BitUnion64(HCR) 236 Bitfield<34> e2h; // AArch64 237 Bitfield<33> id; // AArch64 238 Bitfield<32> cd; // AArch64 239 Bitfield<31> rw; // AArch64 240 Bitfield<30> trvm; // AArch64 241 Bitfield<29> hcd; // AArch64 242 Bitfield<28> tdz; // AArch64 243 244 Bitfield<27> tge; 245 Bitfield<26> tvm; 246 Bitfield<25> ttlb; 247 Bitfield<24> tpu; 248 Bitfield<23> tpc; 249 Bitfield<22> tsw; 250 Bitfield<21> tac; 251 Bitfield<21> tacr; // AArch64 252 Bitfield<20> tidcp; 253 Bitfield<19> tsc; 254 Bitfield<18> tid3; 255 Bitfield<17> tid2; 256 Bitfield<16> tid1; 257 Bitfield<15> tid0; 258 Bitfield<14> twe; 259 Bitfield<13> twi; 260 Bitfield<12> dc; 261 Bitfield<11, 10> bsu; 262 Bitfield<9> fb; 263 Bitfield<8> va; 264 Bitfield<8> vse; // AArch64 265 Bitfield<7> vi; 266 Bitfield<6> vf; 267 Bitfield<5> amo; 268 Bitfield<4> imo; 269 Bitfield<3> fmo; 270 Bitfield<2> ptw; 271 Bitfield<1> swio; 272 Bitfield<0> vm; 273 EndBitUnion(HCR) 274 275 BitUnion32(NSACR) 276 Bitfield<20> nstrcdis; 277 Bitfield<19> rfr; 278 Bitfield<15> nsasedis; 279 Bitfield<14> nsd32dis; 280 Bitfield<13> cp13; 281 Bitfield<12> cp12; 282 Bitfield<11> cp11; 283 Bitfield<10> cp10; 284 Bitfield<9> cp9; 285 Bitfield<8> cp8; 286 Bitfield<7> cp7; 287 Bitfield<6> cp6; 288 Bitfield<5> cp5; 289 Bitfield<4> cp4; 290 Bitfield<3> cp3; 291 Bitfield<2> cp2; 292 Bitfield<1> cp1; 293 Bitfield<0> cp0; 294 EndBitUnion(NSACR) 295 296 BitUnion32(SCR) 297 Bitfield<13> twe; 298 Bitfield<12> twi; 299 Bitfield<11> st; // AArch64 300 Bitfield<10> rw; // AArch64 301 Bitfield<9> sif; 302 Bitfield<8> hce; 303 Bitfield<7> scd; 304 Bitfield<7> smd; // AArch64 305 Bitfield<6> nEt; 306 Bitfield<5> aw; 307 Bitfield<4> fw; 308 Bitfield<3> ea; 309 Bitfield<2> fiq; 310 Bitfield<1> irq; 311 Bitfield<0> ns; 312 EndBitUnion(SCR) 313 314 BitUnion32(SCTLR) 315 Bitfield<30> te; // Thumb Exception Enable (AArch32 only) 316 Bitfield<29> afe; // Access flag enable (AArch32 only) 317 Bitfield<28> tre; // TEX remap enable (AArch32 only) 318 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only) 319 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC, 320 // DC CVAC and IC IVAU instructions 321 // (AArch64 SCTLR_EL1 only) 322 Bitfield<25> ee; // Exception Endianness 323 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0 324 // (AArch64 SCTLR_EL1 only) 325 Bitfield<23> span; // Set Priviledge Access Never on taking 326 // an exception 327 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7) 328 Bitfield<22> u; // Alignment (dropped in ARMv7) 329 Bitfield<21> fi; // Fast interrupts configuration enable 330 // (ARMv7 only) 331 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN 332 // (AArch32 only) 333 Bitfield<19> dz; // Divide by Zero fault enable 334 // (dropped in ARMv7) 335 Bitfield<19> wxn; // Write permission implies XN 336 Bitfield<18> ntwe; // Not trap WFE 337 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 338 Bitfield<18> rao2; // Read as one 339 Bitfield<16> ntwi; // Not trap WFI 340 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 341 Bitfield<16> rao3; // Read as one 342 Bitfield<15> uct; // Enable EL0 access to CTR_EL0 343 // (AArch64 SCTLR_EL1 only) 344 Bitfield<14> rr; // Round Robin select (ARMv7 only) 345 Bitfield<14> dze; // Enable EL0 access to DC ZVA 346 // (AArch64 SCTLR_EL1 only) 347 Bitfield<13> v; // Vectors bit (AArch32 only) 348 Bitfield<12> i; // Instruction cache enable 349 Bitfield<11> z; // Branch prediction enable (ARMv7 only) 350 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only) 351 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7) 352 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only) 353 Bitfield<8> sed; // SETEND disable 354 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 355 Bitfield<7> b; // Endianness support (dropped in ARMv7) 356 Bitfield<7> itd; // IT disable 357 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 358 Bitfield<6, 3> rao4; // Read as one 359 Bitfield<6> thee; // ThumbEE enable 360 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only) 361 Bitfield<5> cp15ben; // CP15 barrier enable 362 // (AArch32 and AArch64 SCTLR_EL1 only) 363 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0 364 // (AArch64 SCTLR_EL1 only) 365 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only) 366 Bitfield<2> c; // Cache enable 367 Bitfield<1> a; // Alignment check enable 368 Bitfield<0> m; // MMU enable 369 EndBitUnion(SCTLR) 370 371 BitUnion32(CPACR) 372 Bitfield<1, 0> cp0; 373 Bitfield<3, 2> cp1; 374 Bitfield<5, 4> cp2; 375 Bitfield<7, 6> cp3; 376 Bitfield<9, 8> cp4; 377 Bitfield<11, 10> cp5; 378 Bitfield<13, 12> cp6; 379 Bitfield<15, 14> cp7; 380 Bitfield<17, 16> cp8; 381 Bitfield<17, 16> zen; // SVE 382 Bitfield<19, 18> cp9; 383 Bitfield<21, 20> cp10; 384 Bitfield<21, 20> fpen; // AArch64 385 Bitfield<23, 22> cp11; 386 Bitfield<25, 24> cp12; 387 Bitfield<27, 26> cp13; 388 Bitfield<29, 28> rsvd; 389 Bitfield<28> tta; // AArch64 390 Bitfield<30> d32dis; 391 Bitfield<31> asedis; 392 EndBitUnion(CPACR) 393 394 BitUnion32(FSR) 395 Bitfield<3, 0> fsLow; 396 Bitfield<5, 0> status; // LPAE 397 Bitfield<7, 4> domain; 398 Bitfield<9> lpae; 399 Bitfield<10> fsHigh; 400 Bitfield<11> wnr; 401 Bitfield<12> ext; 402 Bitfield<13> cm; // LPAE 403 EndBitUnion(FSR) 404 405 BitUnion32(FPSCR) 406 Bitfield<0> ioc; 407 Bitfield<1> dzc; 408 Bitfield<2> ofc; 409 Bitfield<3> ufc; 410 Bitfield<4> ixc; 411 Bitfield<7> idc; 412 Bitfield<8> ioe; 413 Bitfield<9> dze; 414 Bitfield<10> ofe; 415 Bitfield<11> ufe; 416 Bitfield<12> ixe; 417 Bitfield<15> ide; 418 Bitfield<18, 16> len; 419 Bitfield<19> fz16; 420 Bitfield<21, 20> stride; 421 Bitfield<23, 22> rMode; 422 Bitfield<24> fz; 423 Bitfield<25> dn; 424 Bitfield<26> ahp; 425 Bitfield<27> qc; 426 Bitfield<28> v; 427 Bitfield<29> c; 428 Bitfield<30> z; 429 Bitfield<31> n; 430 EndBitUnion(FPSCR) 431 432 BitUnion32(FPEXC) 433 Bitfield<31> ex; 434 Bitfield<30> en; 435 Bitfield<29, 0> subArchDefined; 436 EndBitUnion(FPEXC) 437 438 BitUnion32(MVFR0) 439 Bitfield<3, 0> advSimdRegisters; 440 Bitfield<7, 4> singlePrecision; 441 Bitfield<11, 8> doublePrecision; 442 Bitfield<15, 12> vfpExceptionTrapping; 443 Bitfield<19, 16> divide; 444 Bitfield<23, 20> squareRoot; 445 Bitfield<27, 24> shortVectors; 446 Bitfield<31, 28> roundingModes; 447 EndBitUnion(MVFR0) 448 449 BitUnion32(MVFR1) 450 Bitfield<3, 0> flushToZero; 451 Bitfield<7, 4> defaultNaN; 452 Bitfield<11, 8> advSimdLoadStore; 453 Bitfield<15, 12> advSimdInteger; 454 Bitfield<19, 16> advSimdSinglePrecision; 455 Bitfield<23, 20> advSimdHalfPrecision; 456 Bitfield<27, 24> vfpHalfPrecision; 457 Bitfield<31, 28> raz; 458 EndBitUnion(MVFR1) 459 460 BitUnion64(TTBCR) 461 // Short-descriptor translation table format 462 Bitfield<2, 0> n; 463 Bitfield<4> pd0; 464 Bitfield<5> pd1; 465 // Long-descriptor translation table format 466 Bitfield<2, 0> t0sz; 467 Bitfield<6> t2e; 468 Bitfield<7> epd0; 469 Bitfield<9, 8> irgn0; 470 Bitfield<11, 10> orgn0; 471 Bitfield<13, 12> sh0; 472 Bitfield<14> tg0; 473 Bitfield<18, 16> t1sz; 474 Bitfield<22> a1; 475 Bitfield<23> epd1; 476 Bitfield<25, 24> irgn1; 477 Bitfield<27, 26> orgn1; 478 Bitfield<29, 28> sh1; 479 Bitfield<30> tg1; 480 Bitfield<34, 32> ips; 481 Bitfield<36> as; 482 Bitfield<37> tbi0; 483 Bitfield<38> tbi1; 484 // Common 485 Bitfield<31> eae; 486 // TCR_EL2/3 (AArch64) 487 Bitfield<18, 16> ps; 488 Bitfield<20> tbi; 489 Bitfield<41> hpd0; 490 Bitfield<42> hpd1; 491 EndBitUnion(TTBCR) 492 493 // Fields of TCR_EL{1,2,3} (mostly overlapping) 494 // TCR_EL1 is natively 64 bits, the others are 32 bits 495 BitUnion64(TCR) 496 Bitfield<5, 0> t0sz; 497 Bitfield<7> epd0; // EL1 498 Bitfield<9, 8> irgn0; 499 Bitfield<11, 10> orgn0; 500 Bitfield<13, 12> sh0; 501 Bitfield<15, 14> tg0; 502 Bitfield<18, 16> ps; 503 Bitfield<20> tbi; // EL2/EL3 504 Bitfield<21, 16> t1sz; // EL1 505 Bitfield<22> a1; // EL1 506 Bitfield<23> epd1; // EL1 507 Bitfield<24> hpd; // EL2/EL3, E2H=0 508 Bitfield<25, 24> irgn1; // EL1 509 Bitfield<27, 26> orgn1; // EL1 510 Bitfield<29, 28> sh1; // EL1 511 Bitfield<31, 30> tg1; // EL1 512 Bitfield<34, 32> ips; // EL1 513 Bitfield<36> as; // EL1 514 Bitfield<37> tbi0; // EL1 515 Bitfield<38> tbi1; // EL1 516 Bitfield<39> ha; 517 Bitfield<40> hd; 518 Bitfield<41> hpd0; 519 Bitfield<42> hpd1; 520 EndBitUnion(TCR) 521 522 BitUnion32(HTCR) 523 Bitfield<2, 0> t0sz; 524 Bitfield<9, 8> irgn0; 525 Bitfield<11, 10> orgn0; 526 Bitfield<13, 12> sh0; 527 Bitfield<24> hpd; 528 EndBitUnion(HTCR) 529 530 BitUnion32(VTCR_t) 531 Bitfield<3, 0> t0sz; 532 Bitfield<4> s; 533 Bitfield<5, 0> t0sz64; 534 Bitfield<7, 6> sl0; 535 Bitfield<9, 8> irgn0; 536 Bitfield<11, 10> orgn0; 537 Bitfield<13, 12> sh0; 538 Bitfield<15, 14> tg0; 539 Bitfield<18, 16> ps; // Only defined for VTCR_EL2 540 Bitfield<21> ha; // Only defined for VTCR_EL2 541 Bitfield<22> hd; // Only defined for VTCR_EL2 542 EndBitUnion(VTCR_t) 543 544 BitUnion32(PRRR) 545 Bitfield<1,0> tr0; 546 Bitfield<3,2> tr1; 547 Bitfield<5,4> tr2; 548 Bitfield<7,6> tr3; 549 Bitfield<9,8> tr4; 550 Bitfield<11,10> tr5; 551 Bitfield<13,12> tr6; 552 Bitfield<15,14> tr7; 553 Bitfield<16> ds0; 554 Bitfield<17> ds1; 555 Bitfield<18> ns0; 556 Bitfield<19> ns1; 557 Bitfield<24> nos0; 558 Bitfield<25> nos1; 559 Bitfield<26> nos2; 560 Bitfield<27> nos3; 561 Bitfield<28> nos4; 562 Bitfield<29> nos5; 563 Bitfield<30> nos6; 564 Bitfield<31> nos7; 565 EndBitUnion(PRRR) 566 567 BitUnion32(NMRR) 568 Bitfield<1,0> ir0; 569 Bitfield<3,2> ir1; 570 Bitfield<5,4> ir2; 571 Bitfield<7,6> ir3; 572 Bitfield<9,8> ir4; 573 Bitfield<11,10> ir5; 574 Bitfield<13,12> ir6; 575 Bitfield<15,14> ir7; 576 Bitfield<17,16> or0; 577 Bitfield<19,18> or1; 578 Bitfield<21,20> or2; 579 Bitfield<23,22> or3; 580 Bitfield<25,24> or4; 581 Bitfield<27,26> or5; 582 Bitfield<29,28> or6; 583 Bitfield<31,30> or7; 584 EndBitUnion(NMRR) 585 586 BitUnion32(CONTEXTIDR) 587 Bitfield<7,0> asid; 588 Bitfield<31,8> procid; 589 EndBitUnion(CONTEXTIDR) 590 591 BitUnion32(L2CTLR) 592 Bitfield<2,0> sataRAMLatency; 593 Bitfield<4,3> reserved_4_3; 594 Bitfield<5> dataRAMSetup; 595 Bitfield<8,6> tagRAMLatency; 596 Bitfield<9> tagRAMSetup; 597 Bitfield<11,10> dataRAMSlice; 598 Bitfield<12> tagRAMSlice; 599 Bitfield<20,13> reserved_20_13; 600 Bitfield<21> eccandParityEnable; 601 Bitfield<22> reserved_22; 602 Bitfield<23> interptCtrlPresent; 603 Bitfield<25,24> numCPUs; 604 Bitfield<30,26> reserved_30_26; 605 Bitfield<31> l2rstDISABLE_monitor; 606 EndBitUnion(L2CTLR) 607 608 BitUnion32(CTR) 609 Bitfield<3,0> iCacheLineSize; 610 Bitfield<13,4> raz_13_4; 611 Bitfield<15,14> l1IndexPolicy; 612 Bitfield<19,16> dCacheLineSize; 613 Bitfield<23,20> erg; 614 Bitfield<27,24> cwg; 615 Bitfield<28> raz_28; 616 Bitfield<31,29> format; 617 EndBitUnion(CTR) 618 619 BitUnion32(PMSELR) 620 Bitfield<4, 0> sel; 621 EndBitUnion(PMSELR) 622 623 BitUnion64(PAR) 624 // 64-bit format 625 Bitfield<63, 56> attr; 626 Bitfield<39, 12> pa; 627 Bitfield<11> lpae; 628 Bitfield<9> ns; 629 Bitfield<8, 7> sh; 630 Bitfield<0> f; 631 EndBitUnion(PAR) 632 633 BitUnion32(ESR) 634 Bitfield<31, 26> ec; 635 Bitfield<25> il; 636 Bitfield<15, 0> imm16; 637 EndBitUnion(ESR) 638 639 BitUnion32(CPTR) 640 Bitfield<31> tcpac; 641 Bitfield<20> tta; 642 Bitfield<13, 12> res1_13_12_el2; 643 Bitfield<10> tfp; 644 Bitfield<9> res1_9_el2; 645 Bitfield<8> res1_8_el2; 646 Bitfield<8> ez; // SVE (CPTR_EL3) 647 Bitfield<8> tz; // SVE (CPTR_EL2) 648 Bitfield<7, 0> res1_7_0_el2; 649 EndBitUnion(CPTR) 650 651 BitUnion64(ZCR) 652 Bitfield<3, 0> len; 653 EndBitUnion(ZCR) 654 655} 656 657#endif // __ARCH_ARM_MISCREGS_TYPES_HH__ 658