16019Shines@cs.fsu.edu/*
213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2010, 2012, 2017-2018 ARM Limited
37414SAli.Saidi@ARM.com * All rights reserved
47414SAli.Saidi@ARM.com *
57414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97414SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137414SAli.Saidi@ARM.com *
146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University
156019Shines@cs.fsu.edu * All rights reserved.
166019Shines@cs.fsu.edu *
176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
266019Shines@cs.fsu.edu * this software without specific prior written permission.
276019Shines@cs.fsu.edu *
286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
396019Shines@cs.fsu.edu *
406019Shines@cs.fsu.edu * Authors: Stephen Hines
417414SAli.Saidi@ARM.com *          Ali Saidi
426019Shines@cs.fsu.edu */
436019Shines@cs.fsu.edu
4411793Sbrandon.potter@amd.com#include "arch/arm/process.hh"
4511793Sbrandon.potter@amd.com
466019Shines@cs.fsu.edu#include "arch/arm/isa_traits.hh"
476019Shines@cs.fsu.edu#include "arch/arm/types.hh"
486019Shines@cs.fsu.edu#include "base/loader/elf_object.hh"
496019Shines@cs.fsu.edu#include "base/loader/object_file.hh"
5012334Sgabeblack@google.com#include "base/logging.hh"
516019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
528232Snate@binkert.org#include "debug/Stack.hh"
536019Shines@cs.fsu.edu#include "mem/page_table.hh"
5412431Sgabeblack@google.com#include "params/Process.hh"
5511854Sbrandon.potter@amd.com#include "sim/aux_vector.hh"
567678Sgblack@eecs.umich.edu#include "sim/byteswap.hh"
576019Shines@cs.fsu.edu#include "sim/process_impl.hh"
5811800Sbrandon.potter@amd.com#include "sim/syscall_return.hh"
596019Shines@cs.fsu.edu#include "sim/system.hh"
606019Shines@cs.fsu.edu
616019Shines@cs.fsu.eduusing namespace std;
626019Shines@cs.fsu.eduusing namespace ArmISA;
636019Shines@cs.fsu.edu
6411851Sbrandon.potter@amd.comArmProcess::ArmProcess(ProcessParams *params, ObjectFile *objFile,
6511851Sbrandon.potter@amd.com                       ObjectFile::Arch _arch)
6612448Sgabeblack@google.com    : Process(params,
6712448Sgabeblack@google.com              new EmulationPageTable(params->name, params->pid, PageBytes),
6812432Sgabeblack@google.com              objFile),
6912448Sgabeblack@google.com      arch(_arch)
706019Shines@cs.fsu.edu{
7112441Sgabeblack@google.com    fatal_if(params->useArchPT, "Arch page tables not implemented.");
7210037SARM gem5 Developers}
7310037SARM gem5 Developers
7411851Sbrandon.potter@amd.comArmProcess32::ArmProcess32(ProcessParams *params, ObjectFile *objFile,
7511851Sbrandon.potter@amd.com                           ObjectFile::Arch _arch)
7611851Sbrandon.potter@amd.com    : ArmProcess(params, objFile, _arch)
7710037SARM gem5 Developers{
7811905SBrandon.Potter@amd.com    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
7911905SBrandon.Potter@amd.com                             objFile->bssSize(), PageBytes);
8011905SBrandon.Potter@amd.com    Addr stack_base = 0xbf000000L;
8111905SBrandon.Potter@amd.com    Addr max_stack_size = 8 * 1024 * 1024;
8211905SBrandon.Potter@amd.com    Addr next_thread_stack_base = stack_base - max_stack_size;
8311905SBrandon.Potter@amd.com    Addr mmap_end = 0x40000000L;
846019Shines@cs.fsu.edu
8511905SBrandon.Potter@amd.com    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
8611905SBrandon.Potter@amd.com                                     next_thread_stack_base, mmap_end);
876019Shines@cs.fsu.edu}
886019Shines@cs.fsu.edu
8911851Sbrandon.potter@amd.comArmProcess64::ArmProcess64(ProcessParams *params, ObjectFile *objFile,
9011851Sbrandon.potter@amd.com                           ObjectFile::Arch _arch)
9111851Sbrandon.potter@amd.com    : ArmProcess(params, objFile, _arch)
9210037SARM gem5 Developers{
9311905SBrandon.Potter@amd.com    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
9411905SBrandon.Potter@amd.com                             objFile->bssSize(), PageBytes);
9511905SBrandon.Potter@amd.com    Addr stack_base = 0x7fffff0000L;
9611905SBrandon.Potter@amd.com    Addr max_stack_size = 8 * 1024 * 1024;
9711905SBrandon.Potter@amd.com    Addr next_thread_stack_base = stack_base - max_stack_size;
9811905SBrandon.Potter@amd.com    Addr mmap_end = 0x4000000000L;
9910037SARM gem5 Developers
10011905SBrandon.Potter@amd.com    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
10111905SBrandon.Potter@amd.com                                     next_thread_stack_base, mmap_end);
10210037SARM gem5 Developers}
10310037SARM gem5 Developers
1046019Shines@cs.fsu.eduvoid
10511851Sbrandon.potter@amd.comArmProcess32::initState()
1066019Shines@cs.fsu.edu{
10711851Sbrandon.potter@amd.com    Process::initState();
10810318Sandreas.hansson@arm.com    argsInit<uint32_t>(PageBytes, INTREG_SP);
1097640Sgblack@eecs.umich.edu    for (int i = 0; i < contextIds.size(); i++) {
1107640Sgblack@eecs.umich.edu        ThreadContext * tc = system->getThreadContext(contextIds[i]);
1117640Sgblack@eecs.umich.edu        CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
1127640Sgblack@eecs.umich.edu        // Enable the floating point coprocessors.
1137640Sgblack@eecs.umich.edu        cpacr.cp10 = 0x3;
1147640Sgblack@eecs.umich.edu        cpacr.cp11 = 0x3;
1157640Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CPACR, cpacr);
1167640Sgblack@eecs.umich.edu        // Generically enable floating point support.
1177640Sgblack@eecs.umich.edu        FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
1187640Sgblack@eecs.umich.edu        fpexc.en = 1;
1197640Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_FPEXC, fpexc);
1207640Sgblack@eecs.umich.edu    }
1216019Shines@cs.fsu.edu}
1226019Shines@cs.fsu.edu
1236019Shines@cs.fsu.eduvoid
12411851Sbrandon.potter@amd.comArmProcess64::initState()
1256019Shines@cs.fsu.edu{
12611851Sbrandon.potter@amd.com    Process::initState();
12710318Sandreas.hansson@arm.com    argsInit<uint64_t>(PageBytes, INTREG_SP0);
12810037SARM gem5 Developers    for (int i = 0; i < contextIds.size(); i++) {
12910037SARM gem5 Developers        ThreadContext * tc = system->getThreadContext(contextIds[i]);
13010037SARM gem5 Developers        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
13110037SARM gem5 Developers        cpsr.mode = MODE_EL0T;
13210037SARM gem5 Developers        tc->setMiscReg(MISCREG_CPSR, cpsr);
13310037SARM gem5 Developers        CPACR cpacr = tc->readMiscReg(MISCREG_CPACR_EL1);
13410037SARM gem5 Developers        // Enable the floating point coprocessors.
13510037SARM gem5 Developers        cpacr.cp10 = 0x3;
13610037SARM gem5 Developers        cpacr.cp11 = 0x3;
13713759Sgiacomo.gabrielli@arm.com        // Enable SVE.
13813759Sgiacomo.gabrielli@arm.com        cpacr.zen = 0x3;
13910037SARM gem5 Developers        tc->setMiscReg(MISCREG_CPACR_EL1, cpacr);
14010037SARM gem5 Developers        // Generically enable floating point support.
14110037SARM gem5 Developers        FPEXC fpexc = tc->readMiscReg(MISCREG_FPEXC);
14210037SARM gem5 Developers        fpexc.en = 1;
14310037SARM gem5 Developers        tc->setMiscReg(MISCREG_FPEXC, fpexc);
14410037SARM gem5 Developers    }
14510037SARM gem5 Developers}
14610037SARM gem5 Developers
14713121Sgiacomo.travaglini@arm.comuint32_t
14813121Sgiacomo.travaglini@arm.comArmProcess32::armHwcapImpl() const
14913121Sgiacomo.travaglini@arm.com{
15013121Sgiacomo.travaglini@arm.com    enum ArmCpuFeature {
15113121Sgiacomo.travaglini@arm.com        Arm_Swp = 1 << 0,
15213121Sgiacomo.travaglini@arm.com        Arm_Half = 1 << 1,
15313121Sgiacomo.travaglini@arm.com        Arm_Thumb = 1 << 2,
15413121Sgiacomo.travaglini@arm.com        Arm_26Bit = 1 << 3,
15513121Sgiacomo.travaglini@arm.com        Arm_FastMult = 1 << 4,
15613121Sgiacomo.travaglini@arm.com        Arm_Fpa = 1 << 5,
15713121Sgiacomo.travaglini@arm.com        Arm_Vfp = 1 << 6,
15813121Sgiacomo.travaglini@arm.com        Arm_Edsp = 1 << 7,
15913121Sgiacomo.travaglini@arm.com        Arm_Java = 1 << 8,
16013121Sgiacomo.travaglini@arm.com        Arm_Iwmmxt = 1 << 9,
16113121Sgiacomo.travaglini@arm.com        Arm_Crunch = 1 << 10,
16213121Sgiacomo.travaglini@arm.com        Arm_ThumbEE = 1 << 11,
16313121Sgiacomo.travaglini@arm.com        Arm_Neon = 1 << 12,
16413121Sgiacomo.travaglini@arm.com        Arm_Vfpv3 = 1 << 13,
16513121Sgiacomo.travaglini@arm.com        Arm_Vfpv3d16 = 1 << 14
16613121Sgiacomo.travaglini@arm.com    };
16713121Sgiacomo.travaglini@arm.com
16813121Sgiacomo.travaglini@arm.com    return Arm_Swp | Arm_Half | Arm_Thumb | Arm_FastMult |
16913121Sgiacomo.travaglini@arm.com           Arm_Vfp | Arm_Edsp | Arm_ThumbEE | Arm_Neon |
17013121Sgiacomo.travaglini@arm.com           Arm_Vfpv3 | Arm_Vfpv3d16;
17113121Sgiacomo.travaglini@arm.com}
17213121Sgiacomo.travaglini@arm.com
17313121Sgiacomo.travaglini@arm.comuint32_t
17413121Sgiacomo.travaglini@arm.comArmProcess64::armHwcapImpl() const
17513121Sgiacomo.travaglini@arm.com{
17613121Sgiacomo.travaglini@arm.com    // In order to know what these flags mean, please refer to Linux
17713121Sgiacomo.travaglini@arm.com    // /Documentation/arm64/elf_hwcaps.txt text file.
17813121Sgiacomo.travaglini@arm.com    enum ArmCpuFeature {
17913121Sgiacomo.travaglini@arm.com        Arm_Fp = 1 << 0,
18013121Sgiacomo.travaglini@arm.com        Arm_Asimd = 1 << 1,
18113121Sgiacomo.travaglini@arm.com        Arm_Evtstrm = 1 << 2,
18213121Sgiacomo.travaglini@arm.com        Arm_Aes = 1 << 3,
18313121Sgiacomo.travaglini@arm.com        Arm_Pmull = 1 << 4,
18413121Sgiacomo.travaglini@arm.com        Arm_Sha1 = 1 << 5,
18513121Sgiacomo.travaglini@arm.com        Arm_Sha2 = 1 << 6,
18613121Sgiacomo.travaglini@arm.com        Arm_Crc32 = 1 << 7,
18713121Sgiacomo.travaglini@arm.com        Arm_Atomics = 1 << 8,
18813121Sgiacomo.travaglini@arm.com        Arm_Fphp = 1 << 9,
18913121Sgiacomo.travaglini@arm.com        Arm_Asimdhp = 1 << 10,
19013121Sgiacomo.travaglini@arm.com        Arm_Cpuid = 1 << 11,
19113121Sgiacomo.travaglini@arm.com        Arm_Asimdrdm = 1 << 12,
19213121Sgiacomo.travaglini@arm.com        Arm_Jscvt = 1 << 13,
19313121Sgiacomo.travaglini@arm.com        Arm_Fcma = 1 << 14,
19413121Sgiacomo.travaglini@arm.com        Arm_Lrcpc = 1 << 15,
19513121Sgiacomo.travaglini@arm.com        Arm_Dcpop = 1 << 16,
19613121Sgiacomo.travaglini@arm.com        Arm_Sha3 = 1 << 17,
19713121Sgiacomo.travaglini@arm.com        Arm_Sm3 = 1 << 18,
19813121Sgiacomo.travaglini@arm.com        Arm_Sm4 = 1 << 19,
19913121Sgiacomo.travaglini@arm.com        Arm_Asimddp = 1 << 20,
20013121Sgiacomo.travaglini@arm.com        Arm_Sha512 = 1 << 21,
20113121Sgiacomo.travaglini@arm.com        Arm_Sve = 1 << 22,
20213121Sgiacomo.travaglini@arm.com        Arm_Asimdfhm = 1 << 23,
20313121Sgiacomo.travaglini@arm.com        Arm_Dit = 1 << 24,
20413121Sgiacomo.travaglini@arm.com        Arm_Uscat = 1 << 25,
20513121Sgiacomo.travaglini@arm.com        Arm_Ilrcpc = 1 << 26,
20613121Sgiacomo.travaglini@arm.com        Arm_Flagm = 1 << 27
20713121Sgiacomo.travaglini@arm.com    };
20813121Sgiacomo.travaglini@arm.com
20913122Sgiacomo.travaglini@arm.com    uint32_t hwcap = 0;
21013122Sgiacomo.travaglini@arm.com
21113122Sgiacomo.travaglini@arm.com    ThreadContext *tc = system->getThreadContext(contextIds[0]);
21213122Sgiacomo.travaglini@arm.com
21313122Sgiacomo.travaglini@arm.com    const AA64PFR0 pf_r0 = tc->readMiscReg(MISCREG_ID_AA64PFR0_EL1);
21413122Sgiacomo.travaglini@arm.com
21513122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.fp == 0) ? Arm_Fp : 0;
21613122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.fp == 1) ? Arm_Fphp | Arm_Fp : 0;
21713122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.advsimd == 0) ? Arm_Asimd : 0;
21813122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.advsimd == 1) ? Arm_Asimdhp | Arm_Asimd : 0;
21913122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.sve >= 1) ? Arm_Sve : 0;
22013122Sgiacomo.travaglini@arm.com    hwcap |= (pf_r0.dit >= 1) ? Arm_Dit : 0;
22113122Sgiacomo.travaglini@arm.com
22213122Sgiacomo.travaglini@arm.com    const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
22313122Sgiacomo.travaglini@arm.com
22413122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.aes >= 1) ? Arm_Aes : 0;
22513122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.aes >= 2) ? Arm_Pmull : 0;
22613122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sha1 >= 1) ? Arm_Sha1 : 0;
22713122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sha2 >= 1) ? Arm_Sha2 : 0;
22813122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sha2 >= 2) ? Arm_Sha512 : 0;
22913122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.crc32 >= 1) ? Arm_Crc32 : 0;
23013122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.atomic >= 1) ? Arm_Atomics : 0;
23113122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.rdm >= 1) ? Arm_Asimdrdm : 0;
23213122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sha3 >= 1) ? Arm_Sha3 : 0;
23313122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sm3 >= 1) ? Arm_Sm3 : 0;
23413122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.sm4 >= 1) ? Arm_Sm4 : 0;
23513122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.dp >= 1) ? Arm_Asimddp : 0;
23613122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.fhm >= 1) ? Arm_Asimdfhm : 0;
23713122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r0.ts >= 1) ? Arm_Flagm : 0;
23813122Sgiacomo.travaglini@arm.com
23913122Sgiacomo.travaglini@arm.com    const AA64ISAR1 isa_r1 = tc->readMiscReg(MISCREG_ID_AA64ISAR1_EL1);
24013122Sgiacomo.travaglini@arm.com
24113122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r1.dpb >= 1) ? Arm_Dcpop : 0;
24213122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r1.jscvt >= 1) ? Arm_Jscvt : 0;
24313122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r1.fcma >= 1) ? Arm_Fcma : 0;
24413122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r1.lrcpc >= 1) ? Arm_Lrcpc : 0;
24513122Sgiacomo.travaglini@arm.com    hwcap |= (isa_r1.lrcpc >= 2) ? Arm_Ilrcpc : 0;
24613122Sgiacomo.travaglini@arm.com
24713122Sgiacomo.travaglini@arm.com    const AA64MMFR2 mm_fr2 = tc->readMiscReg(MISCREG_ID_AA64MMFR2_EL1);
24813122Sgiacomo.travaglini@arm.com
24913122Sgiacomo.travaglini@arm.com    hwcap |= (mm_fr2.at >= 1) ? Arm_Uscat : 0;
25013122Sgiacomo.travaglini@arm.com
25113122Sgiacomo.travaglini@arm.com    return hwcap;
25213121Sgiacomo.travaglini@arm.com}
25313121Sgiacomo.travaglini@arm.com
25410037SARM gem5 Developerstemplate <class IntType>
25510037SARM gem5 Developersvoid
25611851Sbrandon.potter@amd.comArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
25710037SARM gem5 Developers{
25810037SARM gem5 Developers    int intSize = sizeof(IntType);
25910037SARM gem5 Developers
26013894Sgabeblack@google.com    std::vector<AuxVector<IntType>> auxv;
2616400Sgblack@eecs.umich.edu
2626400Sgblack@eecs.umich.edu    string filename;
2636400Sgblack@eecs.umich.edu    if (argv.size() < 1)
2646400Sgblack@eecs.umich.edu        filename = "";
2656400Sgblack@eecs.umich.edu    else
2666400Sgblack@eecs.umich.edu        filename = argv[0];
2676400Sgblack@eecs.umich.edu
2686400Sgblack@eecs.umich.edu    //We want 16 byte alignment
2696400Sgblack@eecs.umich.edu    uint64_t align = 16;
2706400Sgblack@eecs.umich.edu
27111389Sbrandon.potter@amd.com    // Patch the ld_bias for dynamic executables.
27211389Sbrandon.potter@amd.com    updateBias();
27311389Sbrandon.potter@amd.com
2746019Shines@cs.fsu.edu    // load object file into target memory
2756019Shines@cs.fsu.edu    objFile->loadSections(initVirtMem);
2766019Shines@cs.fsu.edu
2776400Sgblack@eecs.umich.edu    //Setup the auxilliary vectors. These will already have endian conversion.
2786400Sgblack@eecs.umich.edu    //Auxilliary vectors are loaded only for elf formatted executables.
2796400Sgblack@eecs.umich.edu    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
2806400Sgblack@eecs.umich.edu    if (elfObject) {
2816400Sgblack@eecs.umich.edu
28210810Sbr@bsdpad.com        if (objFile->getOpSys() == ObjectFile::Linux) {
28313121Sgiacomo.travaglini@arm.com            IntType features = armHwcap<IntType>();
28410810Sbr@bsdpad.com
28510810Sbr@bsdpad.com            //Bits which describe the system hardware capabilities
28610810Sbr@bsdpad.com            //XXX Figure out what these should be
28713894Sgabeblack@google.com            auxv.emplace_back(M5_AT_HWCAP, features);
28810810Sbr@bsdpad.com            //Frequency at which times() increments
28913894Sgabeblack@google.com            auxv.emplace_back(M5_AT_CLKTCK, 0x64);
29010810Sbr@bsdpad.com            //Whether to enable "secure mode" in the executable
29113894Sgabeblack@google.com            auxv.emplace_back(M5_AT_SECURE, 0);
29210810Sbr@bsdpad.com            // Pointer to 16 bytes of random data
29313894Sgabeblack@google.com            auxv.emplace_back(M5_AT_RANDOM, 0);
29410810Sbr@bsdpad.com            //The filename of the program
29513894Sgabeblack@google.com            auxv.emplace_back(M5_AT_EXECFN, 0);
29610810Sbr@bsdpad.com            //The string "v71" -- ARM v7 architecture
29713894Sgabeblack@google.com            auxv.emplace_back(M5_AT_PLATFORM, 0);
29810810Sbr@bsdpad.com        }
29910810Sbr@bsdpad.com
3006400Sgblack@eecs.umich.edu        //The system page size
30113894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PAGESZ, ArmISA::PageBytes);
30213894Sgabeblack@google.com        // For statically linked executables, this is the virtual address of
30313894Sgabeblack@google.com        // the program header tables if they appear in the executable image
30413894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
3056400Sgblack@eecs.umich.edu        // This is the size of a program header entry from the elf file.
30613894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
3076400Sgblack@eecs.umich.edu        // This is the number of program headers from the original elf file.
30813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
30911389Sbrandon.potter@amd.com        // This is the base address of the ELF interpreter; it should be
31011389Sbrandon.potter@amd.com        // zero for static executables or contain the base address for
31111389Sbrandon.potter@amd.com        // dynamic executables.
31213894Sgabeblack@google.com        auxv.emplace_back(M5_AT_BASE, getBias());
3136400Sgblack@eecs.umich.edu        //XXX Figure out what this should be.
31413894Sgabeblack@google.com        auxv.emplace_back(M5_AT_FLAGS, 0);
3156400Sgblack@eecs.umich.edu        //The entry point to the program
31613894Sgabeblack@google.com        auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
3176400Sgblack@eecs.umich.edu        //Different user and group IDs
31813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_UID, uid());
31913894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EUID, euid());
32013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_GID, gid());
32113894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EGID, egid());
3226400Sgblack@eecs.umich.edu    }
3236400Sgblack@eecs.umich.edu
3246400Sgblack@eecs.umich.edu    //Figure out how big the initial stack nedes to be
3256400Sgblack@eecs.umich.edu
3266400Sgblack@eecs.umich.edu    // A sentry NULL void pointer at the top of the stack.
3276400Sgblack@eecs.umich.edu    int sentry_size = intSize;
3286400Sgblack@eecs.umich.edu
3297414SAli.Saidi@ARM.com    string platform = "v71";
3306400Sgblack@eecs.umich.edu    int platform_size = platform.size() + 1;
3316400Sgblack@eecs.umich.edu
3327414SAli.Saidi@ARM.com    // Bytes for AT_RANDOM above, we'll just keep them 0
3337414SAli.Saidi@ARM.com    int aux_random_size = 16; // as per the specification
3347414SAli.Saidi@ARM.com
3356400Sgblack@eecs.umich.edu    // The aux vectors are put on the stack in two groups. The first group are
3366400Sgblack@eecs.umich.edu    // the vectors that are generated as the elf is loaded. The second group
3376400Sgblack@eecs.umich.edu    // are the ones that were computed ahead of time and include the platform
3386400Sgblack@eecs.umich.edu    // string.
3396400Sgblack@eecs.umich.edu    int aux_data_size = filename.size() + 1;
3406400Sgblack@eecs.umich.edu
3416400Sgblack@eecs.umich.edu    int env_data_size = 0;
3426400Sgblack@eecs.umich.edu    for (int i = 0; i < envp.size(); ++i) {
3436400Sgblack@eecs.umich.edu        env_data_size += envp[i].size() + 1;
3446400Sgblack@eecs.umich.edu    }
3456019Shines@cs.fsu.edu    int arg_data_size = 0;
3466019Shines@cs.fsu.edu    for (int i = 0; i < argv.size(); ++i) {
3476019Shines@cs.fsu.edu        arg_data_size += argv[i].size() + 1;
3486019Shines@cs.fsu.edu    }
3496400Sgblack@eecs.umich.edu
3506400Sgblack@eecs.umich.edu    int info_block_size =
3516400Sgblack@eecs.umich.edu        sentry_size + env_data_size + arg_data_size +
3527414SAli.Saidi@ARM.com        aux_data_size + platform_size + aux_random_size;
3536400Sgblack@eecs.umich.edu
3546400Sgblack@eecs.umich.edu    //Each auxilliary vector is two 4 byte words
3556400Sgblack@eecs.umich.edu    int aux_array_size = intSize * 2 * (auxv.size() + 1);
3566400Sgblack@eecs.umich.edu
3576400Sgblack@eecs.umich.edu    int envp_array_size = intSize * (envp.size() + 1);
3586400Sgblack@eecs.umich.edu    int argv_array_size = intSize * (argv.size() + 1);
3596400Sgblack@eecs.umich.edu
3606400Sgblack@eecs.umich.edu    int argc_size = intSize;
3616400Sgblack@eecs.umich.edu
3626400Sgblack@eecs.umich.edu    //Figure out the size of the contents of the actual initial frame
3636400Sgblack@eecs.umich.edu    int frame_size =
3646400Sgblack@eecs.umich.edu        info_block_size +
3656400Sgblack@eecs.umich.edu        aux_array_size +
3666400Sgblack@eecs.umich.edu        envp_array_size +
3676400Sgblack@eecs.umich.edu        argv_array_size +
3686400Sgblack@eecs.umich.edu        argc_size;
3696400Sgblack@eecs.umich.edu
3706400Sgblack@eecs.umich.edu    //There needs to be padding after the auxiliary vector data so that the
3716400Sgblack@eecs.umich.edu    //very bottom of the stack is aligned properly.
3726400Sgblack@eecs.umich.edu    int partial_size = frame_size;
3736400Sgblack@eecs.umich.edu    int aligned_partial_size = roundUp(partial_size, align);
3746400Sgblack@eecs.umich.edu    int aux_padding = aligned_partial_size - partial_size;
3756400Sgblack@eecs.umich.edu
3766400Sgblack@eecs.umich.edu    int space_needed = frame_size + aux_padding;
3776400Sgblack@eecs.umich.edu
37811905SBrandon.Potter@amd.com    memState->setStackMin(memState->getStackBase() - space_needed);
37911905SBrandon.Potter@amd.com    memState->setStackMin(roundDown(memState->getStackMin(), align));
38011905SBrandon.Potter@amd.com    memState->setStackSize(memState->getStackBase() - memState->getStackMin());
3816400Sgblack@eecs.umich.edu
3826400Sgblack@eecs.umich.edu    // map memory
38311905SBrandon.Potter@amd.com    allocateMem(roundDown(memState->getStackMin(), pageSize),
38411905SBrandon.Potter@amd.com                          roundUp(memState->getStackSize(), pageSize));
3856400Sgblack@eecs.umich.edu
3866400Sgblack@eecs.umich.edu    // map out initial stack contents
38711905SBrandon.Potter@amd.com    IntType sentry_base = memState->getStackBase() - sentry_size;
38810037SARM gem5 Developers    IntType aux_data_base = sentry_base - aux_data_size;
38910037SARM gem5 Developers    IntType env_data_base = aux_data_base - env_data_size;
39010037SARM gem5 Developers    IntType arg_data_base = env_data_base - arg_data_size;
39110037SARM gem5 Developers    IntType platform_base = arg_data_base - platform_size;
39210037SARM gem5 Developers    IntType aux_random_base = platform_base - aux_random_size;
39310037SARM gem5 Developers    IntType auxv_array_base = aux_random_base - aux_array_size - aux_padding;
39410037SARM gem5 Developers    IntType envp_array_base = auxv_array_base - envp_array_size;
39510037SARM gem5 Developers    IntType argv_array_base = envp_array_base - argv_array_size;
39610037SARM gem5 Developers    IntType argc_base = argv_array_base - argc_size;
3976400Sgblack@eecs.umich.edu
3986400Sgblack@eecs.umich.edu    DPRINTF(Stack, "The addresses of items on the initial stack:\n");
3996400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
4006400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - env data\n", env_data_base);
4016400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
4027414SAli.Saidi@ARM.com    DPRINTF(Stack, "0x%x - random data\n", aux_random_base);
4036400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - platform base\n", platform_base);
4046400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
4056400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
4066400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
4076400Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - argc \n", argc_base);
40811905SBrandon.Potter@amd.com    DPRINTF(Stack, "0x%x - stack min\n", memState->getStackMin());
4096400Sgblack@eecs.umich.edu
4106400Sgblack@eecs.umich.edu    // write contents to stack
4116400Sgblack@eecs.umich.edu
4126400Sgblack@eecs.umich.edu    // figure out argc
41310037SARM gem5 Developers    IntType argc = argv.size();
41410037SARM gem5 Developers    IntType guestArgc = ArmISA::htog(argc);
4156400Sgblack@eecs.umich.edu
4166400Sgblack@eecs.umich.edu    //Write out the sentry void *
41710037SARM gem5 Developers    IntType sentry_NULL = 0;
41814010Sgabeblack@google.com    initVirtMem.writeBlob(sentry_base, &sentry_NULL, sentry_size);
4196400Sgblack@eecs.umich.edu
4206400Sgblack@eecs.umich.edu    //Fix up the aux vectors which point to other data
4216400Sgblack@eecs.umich.edu    for (int i = auxv.size() - 1; i >= 0; i--) {
42213894Sgabeblack@google.com        if (auxv[i].type == M5_AT_PLATFORM) {
42313894Sgabeblack@google.com            auxv[i].val = platform_base;
4248852Sandreas.hansson@arm.com            initVirtMem.writeString(platform_base, platform.c_str());
42513894Sgabeblack@google.com        } else if (auxv[i].type == M5_AT_EXECFN) {
42613894Sgabeblack@google.com            auxv[i].val = aux_data_base;
4278852Sandreas.hansson@arm.com            initVirtMem.writeString(aux_data_base, filename.c_str());
42813894Sgabeblack@google.com        } else if (auxv[i].type == M5_AT_RANDOM) {
42913894Sgabeblack@google.com            auxv[i].val = aux_random_base;
4307414SAli.Saidi@ARM.com            // Just leave the value 0, we don't want randomness
4316400Sgblack@eecs.umich.edu        }
4326019Shines@cs.fsu.edu    }
4336019Shines@cs.fsu.edu
4346400Sgblack@eecs.umich.edu    //Copy the aux stuff
43513894Sgabeblack@google.com    Addr auxv_array_end = auxv_array_base;
43613894Sgabeblack@google.com    for (const auto &aux: auxv) {
43713894Sgabeblack@google.com        initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
43813894Sgabeblack@google.com        auxv_array_end += sizeof(aux);
4396400Sgblack@eecs.umich.edu    }
44013798Stiago.muck@arm.com    //Write out the terminating zeroed auxillary vector
44113894Sgabeblack@google.com    const AuxVector<IntType> zero(0, 0);
44213894Sgabeblack@google.com    initVirtMem.write(auxv_array_end, zero);
44313894Sgabeblack@google.com    auxv_array_end += sizeof(zero);
4446019Shines@cs.fsu.edu
4456400Sgblack@eecs.umich.edu    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
4466400Sgblack@eecs.umich.edu    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
4476019Shines@cs.fsu.edu
44814010Sgabeblack@google.com    initVirtMem.writeBlob(argc_base, &guestArgc, intSize);
4496019Shines@cs.fsu.edu
4506020Sgblack@eecs.umich.edu    ThreadContext *tc = system->getThreadContext(contextIds[0]);
4516400Sgblack@eecs.umich.edu    //Set the stack pointer register
45211905SBrandon.Potter@amd.com    tc->setIntReg(spIndex, memState->getStackMin());
4536400Sgblack@eecs.umich.edu    //A pointer to a function to run when the program exits. We'll set this
4546400Sgblack@eecs.umich.edu    //to zero explicitly to make sure this isn't used.
4556400Sgblack@eecs.umich.edu    tc->setIntReg(ArgumentReg0, 0);
4566400Sgblack@eecs.umich.edu    //Set argument regs 1 and 2 to argv[0] and envp[0] respectively
4576400Sgblack@eecs.umich.edu    if (argv.size() > 0) {
4586400Sgblack@eecs.umich.edu        tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
4596400Sgblack@eecs.umich.edu                                    argv[argv.size() - 1].size() - 1);
4606400Sgblack@eecs.umich.edu    } else {
4616400Sgblack@eecs.umich.edu        tc->setIntReg(ArgumentReg1, 0);
4626400Sgblack@eecs.umich.edu    }
4636400Sgblack@eecs.umich.edu    if (envp.size() > 0) {
4646400Sgblack@eecs.umich.edu        tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
4656400Sgblack@eecs.umich.edu                                    envp[envp.size() - 1].size() - 1);
4666400Sgblack@eecs.umich.edu    } else {
4676400Sgblack@eecs.umich.edu        tc->setIntReg(ArgumentReg2, 0);
4686400Sgblack@eecs.umich.edu    }
4696019Shines@cs.fsu.edu
4707720Sgblack@eecs.umich.edu    PCState pc;
4717720Sgblack@eecs.umich.edu    pc.thumb(arch == ObjectFile::Thumb);
4727720Sgblack@eecs.umich.edu    pc.nextThumb(pc.thumb());
47310037SARM gem5 Developers    pc.aarch64(arch == ObjectFile::Arm64);
47410037SARM gem5 Developers    pc.nextAArch64(pc.aarch64());
47511389Sbrandon.potter@amd.com    pc.set(getStartPC() & ~mask(1));
4767720Sgblack@eecs.umich.edu    tc->pcState(pc);
4776400Sgblack@eecs.umich.edu
47811886Sbrandon.potter@amd.com    //Align the "stackMin" to a page boundary.
47911905SBrandon.Potter@amd.com    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
4806019Shines@cs.fsu.edu}
4816019Shines@cs.fsu.edu
48213581Sgabeblack@google.comRegVal
48311851Sbrandon.potter@amd.comArmProcess32::getSyscallArg(ThreadContext *tc, int &i)
4846020Sgblack@eecs.umich.edu{
4857441SAli.Saidi@ARM.com    assert(i < 6);
4866701Sgblack@eecs.umich.edu    return tc->readIntReg(ArgumentReg0 + i++);
4876020Sgblack@eecs.umich.edu}
4886020Sgblack@eecs.umich.edu
48913581Sgabeblack@google.comRegVal
49011851Sbrandon.potter@amd.comArmProcess64::getSyscallArg(ThreadContext *tc, int &i)
49110037SARM gem5 Developers{
49210037SARM gem5 Developers    assert(i < 8);
49310037SARM gem5 Developers    return tc->readIntReg(ArgumentReg0 + i++);
49410037SARM gem5 Developers}
49510037SARM gem5 Developers
49613581Sgabeblack@google.comRegVal
49711851Sbrandon.potter@amd.comArmProcess32::getSyscallArg(ThreadContext *tc, int &i, int width)
4987441SAli.Saidi@ARM.com{
4997441SAli.Saidi@ARM.com    assert(width == 32 || width == 64);
5007441SAli.Saidi@ARM.com    if (width == 32)
5017441SAli.Saidi@ARM.com        return getSyscallArg(tc, i);
5027441SAli.Saidi@ARM.com
5037441SAli.Saidi@ARM.com    // 64 bit arguments are passed starting in an even register
5047441SAli.Saidi@ARM.com    if (i % 2 != 0)
5057441SAli.Saidi@ARM.com       i++;
5067441SAli.Saidi@ARM.com
5077441SAli.Saidi@ARM.com    // Registers r0-r6 can be used
5087441SAli.Saidi@ARM.com    assert(i < 5);
5097441SAli.Saidi@ARM.com    uint64_t val;
5107441SAli.Saidi@ARM.com    val = tc->readIntReg(ArgumentReg0 + i++);
5117441SAli.Saidi@ARM.com    val |= ((uint64_t)tc->readIntReg(ArgumentReg0 + i++) << 32);
5127441SAli.Saidi@ARM.com    return val;
5137441SAli.Saidi@ARM.com}
5147441SAli.Saidi@ARM.com
51513581Sgabeblack@google.comRegVal
51611851Sbrandon.potter@amd.comArmProcess64::getSyscallArg(ThreadContext *tc, int &i, int width)
51710037SARM gem5 Developers{
51810037SARM gem5 Developers    return getSyscallArg(tc, i);
51910037SARM gem5 Developers}
52010037SARM gem5 Developers
5217441SAli.Saidi@ARM.com
5226020Sgblack@eecs.umich.eduvoid
52313581Sgabeblack@google.comArmProcess32::setSyscallArg(ThreadContext *tc, int i, RegVal val)
5246020Sgblack@eecs.umich.edu{
52510037SARM gem5 Developers    assert(i < 6);
5266020Sgblack@eecs.umich.edu    tc->setIntReg(ArgumentReg0 + i, val);
5276020Sgblack@eecs.umich.edu}
5286020Sgblack@eecs.umich.edu
5296020Sgblack@eecs.umich.eduvoid
53013581Sgabeblack@google.comArmProcess64::setSyscallArg(ThreadContext *tc, int i, RegVal val)
53110037SARM gem5 Developers{
53210037SARM gem5 Developers    assert(i < 8);
53310037SARM gem5 Developers    tc->setIntReg(ArgumentReg0 + i, val);
53410037SARM gem5 Developers}
53510037SARM gem5 Developers
53610037SARM gem5 Developersvoid
53711851Sbrandon.potter@amd.comArmProcess32::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
5386020Sgblack@eecs.umich.edu{
53910810Sbr@bsdpad.com
54010810Sbr@bsdpad.com    if (objFile->getOpSys() == ObjectFile::FreeBSD) {
54110810Sbr@bsdpad.com        // Decode return value
54210810Sbr@bsdpad.com        if (sysret.encodedValue() >= 0)
54310810Sbr@bsdpad.com            // FreeBSD checks the carry bit to determine if syscall is succeeded
54410810Sbr@bsdpad.com            tc->setCCReg(CCREG_C, 0);
54510810Sbr@bsdpad.com        else {
54610810Sbr@bsdpad.com            sysret = -sysret.encodedValue();
54710810Sbr@bsdpad.com        }
54810810Sbr@bsdpad.com    }
54910810Sbr@bsdpad.com
55010223Ssteve.reinhardt@amd.com    tc->setIntReg(ReturnValueReg, sysret.encodedValue());
5516020Sgblack@eecs.umich.edu}
55210037SARM gem5 Developers
55310037SARM gem5 Developersvoid
55411851Sbrandon.potter@amd.comArmProcess64::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
55510037SARM gem5 Developers{
55610810Sbr@bsdpad.com
55710810Sbr@bsdpad.com    if (objFile->getOpSys() == ObjectFile::FreeBSD) {
55810810Sbr@bsdpad.com        // Decode return value
55910810Sbr@bsdpad.com        if (sysret.encodedValue() >= 0)
56010810Sbr@bsdpad.com            // FreeBSD checks the carry bit to determine if syscall is succeeded
56110810Sbr@bsdpad.com            tc->setCCReg(CCREG_C, 0);
56210810Sbr@bsdpad.com        else {
56310810Sbr@bsdpad.com            sysret = -sysret.encodedValue();
56410810Sbr@bsdpad.com        }
56510810Sbr@bsdpad.com    }
56610810Sbr@bsdpad.com
56710223Ssteve.reinhardt@amd.com    tc->setIntReg(ReturnValueReg, sysret.encodedValue());
56810037SARM gem5 Developers}
569