14776SN/A/* 213759Sgiacomo.gabrielli@arm.com * Copyright (c) 2010-2011, 2014, 2016-2017 ARM Limited 37414SAli.Saidi@ARM.com * All rights reserved 47414SAli.Saidi@ARM.com * 57414SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67414SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77414SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87414SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97414SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107414SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117414SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127414SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137414SAli.Saidi@ARM.com * 146365SN/A * Copyright (c) 2006 The Regents of The University of Michigan 154776SN/A * All rights reserved. 164776SN/A * 174776SN/A * Redistribution and use in source and binary forms, with or without 184776SN/A * modification, are permitted provided that the following conditions are 194776SN/A * met: redistributions of source code must retain the above copyright 204776SN/A * notice, this list of conditions and the following disclaimer; 214776SN/A * redistributions in binary form must reproduce the above copyright 224776SN/A * notice, this list of conditions and the following disclaimer in the 234776SN/A * documentation and/or other materials provided with the distribution; 244776SN/A * neither the name of the copyright holders nor the names of its 254776SN/A * contributors may be used to endorse or promote products derived from 264776SN/A * this software without specific prior written permission. 274776SN/A * 284776SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 294776SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 304776SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 314776SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 324776SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 334776SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 344776SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 354776SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 364776SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 374776SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 384776SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394776SN/A * 406365SN/A * Authors: Gabe Black 414776SN/A */ 424776SN/A 4311793Sbrandon.potter@amd.com#include "arch/arm/nativetrace.hh" 4411793Sbrandon.potter@amd.com 456397Sgblack@eecs.umich.edu#include "arch/arm/isa_traits.hh" 466397Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 474776SN/A#include "cpu/thread_context.hh" 488232Snate@binkert.org#include "debug/ExecRegDelta.hh" 496397Sgblack@eecs.umich.edu#include "params/ArmNativeTrace.hh" 507678Sgblack@eecs.umich.edu#include "sim/byteswap.hh" 514776SN/A 524776SN/Anamespace Trace { 534776SN/A 546398Sgblack@eecs.umich.edu#if TRACING_ON 556397Sgblack@eecs.umich.edustatic const char *regNames[] = { 566397Sgblack@eecs.umich.edu "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 576397Sgblack@eecs.umich.edu "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc", 588271SAli.Saidi@ARM.com "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6", 598271SAli.Saidi@ARM.com "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", 608271SAli.Saidi@ARM.com "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", 618271SAli.Saidi@ARM.com "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", 628271SAli.Saidi@ARM.com "f31", "fpscr" 636365SN/A}; 646398Sgblack@eecs.umich.edu#endif 656398Sgblack@eecs.umich.edu 666398Sgblack@eecs.umich.eduvoid 676398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(NativeTrace *parent) 686398Sgblack@eecs.umich.edu{ 696398Sgblack@eecs.umich.edu oldState = state[current]; 706398Sgblack@eecs.umich.edu current = (current + 1) % 2; 716398Sgblack@eecs.umich.edu newState = state[current]; 726398Sgblack@eecs.umich.edu 736411Sgblack@eecs.umich.edu memcpy(newState, oldState, sizeof(state[0])); 746411Sgblack@eecs.umich.edu 758271SAli.Saidi@ARM.com uint64_t diffVector; 766411Sgblack@eecs.umich.edu parent->read(&diffVector, sizeof(diffVector)); 776411Sgblack@eecs.umich.edu diffVector = ArmISA::gtoh(diffVector); 786411Sgblack@eecs.umich.edu 796411Sgblack@eecs.umich.edu int changes = 0; 806398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 816411Sgblack@eecs.umich.edu if (diffVector & 0x1) { 826411Sgblack@eecs.umich.edu changed[i] = true; 836411Sgblack@eecs.umich.edu changes++; 846411Sgblack@eecs.umich.edu } else { 856411Sgblack@eecs.umich.edu changed[i] = false; 866411Sgblack@eecs.umich.edu } 876411Sgblack@eecs.umich.edu diffVector >>= 1; 886411Sgblack@eecs.umich.edu } 896411Sgblack@eecs.umich.edu 908271SAli.Saidi@ARM.com uint64_t values[changes]; 916411Sgblack@eecs.umich.edu parent->read(values, sizeof(values)); 926411Sgblack@eecs.umich.edu int pos = 0; 936411Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 946411Sgblack@eecs.umich.edu if (changed[i]) { 956411Sgblack@eecs.umich.edu newState[i] = ArmISA::gtoh(values[pos++]); 966411Sgblack@eecs.umich.edu changed[i] = (newState[i] != oldState[i]); 976411Sgblack@eecs.umich.edu } 986398Sgblack@eecs.umich.edu } 996398Sgblack@eecs.umich.edu} 1006398Sgblack@eecs.umich.edu 1016398Sgblack@eecs.umich.eduvoid 1026398Sgblack@eecs.umich.eduTrace::ArmNativeTrace::ThreadState::update(ThreadContext *tc) 1036398Sgblack@eecs.umich.edu{ 1046398Sgblack@eecs.umich.edu oldState = state[current]; 1056398Sgblack@eecs.umich.edu current = (current + 1) % 2; 1066398Sgblack@eecs.umich.edu newState = state[current]; 1076398Sgblack@eecs.umich.edu 1086398Sgblack@eecs.umich.edu // Regular int regs 1096398Sgblack@eecs.umich.edu for (int i = 0; i < 15; i++) { 1106398Sgblack@eecs.umich.edu newState[i] = tc->readIntReg(i); 1116398Sgblack@eecs.umich.edu changed[i] = (oldState[i] != newState[i]); 1126398Sgblack@eecs.umich.edu } 1136398Sgblack@eecs.umich.edu 1146398Sgblack@eecs.umich.edu //R15, aliased with the PC 1157720Sgblack@eecs.umich.edu newState[STATE_PC] = tc->pcState().npc(); 1166398Sgblack@eecs.umich.edu changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]); 1176398Sgblack@eecs.umich.edu 1186398Sgblack@eecs.umich.edu //CPSR 1198303SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 12010338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 12110338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 12210338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 12310338SCurtis.Dunham@arm.com cpsr.ge = tc->readCCReg(CCREG_GE); 1248303SAli.Saidi@ARM.com 1258303SAli.Saidi@ARM.com newState[STATE_CPSR] = cpsr; 1266398Sgblack@eecs.umich.edu changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]); 1278271SAli.Saidi@ARM.com 12812109SRekai.GonzalezAlberquilla@arm.com for (int i = 0; i < NumVecV7ArchRegs; i++) { 12913759Sgiacomo.gabrielli@arm.com auto vec(tc->readVecReg(RegId(VecRegClass,i)) 13013759Sgiacomo.gabrielli@arm.com .as<uint64_t, MaxSveVecLenInDWords>()); 13112109SRekai.GonzalezAlberquilla@arm.com newState[STATE_F0 + 2*i] = vec[0]; 13212109SRekai.GonzalezAlberquilla@arm.com newState[STATE_F0 + 2*i + 1] = vec[1]; 1338271SAli.Saidi@ARM.com } 1348271SAli.Saidi@ARM.com newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) | 13510338SCurtis.Dunham@arm.com tc->readCCReg(CCREG_FP); 1366398Sgblack@eecs.umich.edu} 1376365SN/A 1386365SN/Avoid 1396397Sgblack@eecs.umich.eduTrace::ArmNativeTrace::check(NativeTraceRecord *record) 1404776SN/A{ 1416417Sgblack@eecs.umich.edu ThreadContext *tc = record->getThread(); 1426417Sgblack@eecs.umich.edu // This area is read only on the target. It can't stop there to tell us 1436417Sgblack@eecs.umich.edu // what's going on, so we should skip over anything there also. 1447720Sgblack@eecs.umich.edu if (tc->nextInstAddr() > 0xffff0000) 1456417Sgblack@eecs.umich.edu return; 1466398Sgblack@eecs.umich.edu nState.update(this); 1476417Sgblack@eecs.umich.edu mState.update(tc); 1485523SN/A 1497414SAli.Saidi@ARM.com // If a syscall just happened native trace needs another tick 1507414SAli.Saidi@ARM.com if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) && 1517414SAli.Saidi@ARM.com (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) { 1527414SAli.Saidi@ARM.com DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n"); 1537414SAli.Saidi@ARM.com nState.update(this); 1547414SAli.Saidi@ARM.com 1557414SAli.Saidi@ARM.com } 1567414SAli.Saidi@ARM.com 1576409Sgblack@eecs.umich.edu bool errorFound = false; 1586397Sgblack@eecs.umich.edu // Regular int regs 1596398Sgblack@eecs.umich.edu for (int i = 0; i < STATE_NUMVALS; i++) { 1606398Sgblack@eecs.umich.edu if (nState.changed[i] || mState.changed[i]) { 1616410Sgblack@eecs.umich.edu bool oldMatch = (mState.oldState[i] == nState.oldState[i]); 1626410Sgblack@eecs.umich.edu bool newMatch = (mState.newState[i] == nState.newState[i]); 1636410Sgblack@eecs.umich.edu if (oldMatch && newMatch) { 1646410Sgblack@eecs.umich.edu // The more things change, the more they stay the same. 1656410Sgblack@eecs.umich.edu continue; 1668641Snate@binkert.org } 1678641Snate@binkert.org 1688641Snate@binkert.org errorFound = true; 1698641Snate@binkert.org 1708641Snate@binkert.org#ifndef NDEBUG 1718641Snate@binkert.org const char *vergence = " "; 1728641Snate@binkert.org if (oldMatch && !newMatch) { 1736398Sgblack@eecs.umich.edu vergence = "<>"; 1746410Sgblack@eecs.umich.edu } else if (!oldMatch && newMatch) { 1756398Sgblack@eecs.umich.edu vergence = "><"; 1766398Sgblack@eecs.umich.edu } 1778641Snate@binkert.org 1786398Sgblack@eecs.umich.edu if (!nState.changed[i]) { 1796398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1806398Sgblack@eecs.umich.edu "Native: %#010x "\ 1816398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1826398Sgblack@eecs.umich.edu vergence, regNames[i], 1836398Sgblack@eecs.umich.edu nState.newState[i], 1846398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1856398Sgblack@eecs.umich.edu } else if (!mState.changed[i]) { 1866398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1876398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1886398Sgblack@eecs.umich.edu "M5: %#010x \n", 1896398Sgblack@eecs.umich.edu vergence, regNames[i], 1906398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1916398Sgblack@eecs.umich.edu mState.newState[i]); 1926410Sgblack@eecs.umich.edu } else { 1936398Sgblack@eecs.umich.edu DPRINTF(ExecRegDelta, "%s [%5s] "\ 1946398Sgblack@eecs.umich.edu "Native: %#010x => %#010x "\ 1956398Sgblack@eecs.umich.edu "M5: %#010x => %#010x\n", 1966398Sgblack@eecs.umich.edu vergence, regNames[i], 1976398Sgblack@eecs.umich.edu nState.oldState[i], nState.newState[i], 1986398Sgblack@eecs.umich.edu mState.oldState[i], mState.newState[i]); 1996398Sgblack@eecs.umich.edu } 2008641Snate@binkert.org#endif 2016398Sgblack@eecs.umich.edu } 2024776SN/A } 2036409Sgblack@eecs.umich.edu if (errorFound) { 2046409Sgblack@eecs.umich.edu StaticInstPtr inst = record->getStaticInst(); 2056409Sgblack@eecs.umich.edu assert(inst); 2066409Sgblack@eecs.umich.edu bool ran = true; 2076409Sgblack@eecs.umich.edu if (inst->isMicroop()) { 2086409Sgblack@eecs.umich.edu ran = false; 2096409Sgblack@eecs.umich.edu inst = record->getMacroStaticInst(); 2106409Sgblack@eecs.umich.edu } 2116409Sgblack@eecs.umich.edu assert(inst); 2126409Sgblack@eecs.umich.edu record->traceInst(inst, ran); 2136419Sgblack@eecs.umich.edu 2146419Sgblack@eecs.umich.edu bool pcError = (mState.newState[STATE_PC] != 2156419Sgblack@eecs.umich.edu nState.newState[STATE_PC]); 2166419Sgblack@eecs.umich.edu if (stopOnPCError && pcError) 2176419Sgblack@eecs.umich.edu panic("Native trace detected an error in control flow!"); 2186409Sgblack@eecs.umich.edu } 2194776SN/A} 2204776SN/A 2217811Ssteve.reinhardt@amd.com} // namespace Trace 2224776SN/A 2234776SN/A//////////////////////////////////////////////////////////////////////// 2244776SN/A// 2254776SN/A// ExeTracer Simulation Object 2264776SN/A// 2276397Sgblack@eecs.umich.eduTrace::ArmNativeTrace * 2286397Sgblack@eecs.umich.eduArmNativeTraceParams::create() 2294776SN/A{ 2306397Sgblack@eecs.umich.edu return new Trace::ArmNativeTrace(this); 2318902Sandreas.hansson@arm.com} 232