/gem5/src/mem/probes/ |
H A D | mem_footprint.cc | 48 cacheLineSizeLg2(floorLog2(p->system->cacheLineSize())), 50 totalCacheLinesInMem(p->system->memSize() / p->system->cacheLineSize()), 51 totalPagesInMem(p->system->memSize() / p->page_size), 56 system(p->system) 58 fatal_if(!isPowerOf2(system->cacheLineSize()), 102 if (!pi.cmd.isRequest() || !system->isMemAddr(pi.addr))
|
H A D | mem_trace.hh | 71 System *system; member in class:MemTraceProbe
|
H A D | MemTraceProbe.py | 56 system = Param.System(Parent.any, "System the probe belongs to") variable in class:MemTraceProbe
|
/gem5/tests/long/se/70.twolf/ |
H A D | test.py | 36 root.system.cpu[0].workload = workload.makeProcess() 37 cwd = root.system.cpu[0].workload[0].cwd
|
/gem5/tests/quick/se/70.twolf/ |
H A D | test.py | 37 root.system.cpu[0].workload = workload.makeProcess() 38 cwd = root.system.cpu[0].workload[0].cwd
|
/gem5/configs/common/ |
H A D | GPUTLBConfig.py | 77 def config_tlb_hierarchy(options, system, shader_idx): 80 # is always the last item in the system.cpu list. 81 dispatcher_idx = len(system.cpu) - 1 111 # Call the appropriate constructors and add objects to the system 133 # add the different TLB levels to the system 136 exec('system.%s = TLB_array' % system_TLB_name) 137 exec('system.%s = Coalescer_array' % system_Coalescer_name) 153 exec('system.%s_coalescer[%d].master[0] = \ 154 system.%s_tlb[%d].slave[0]' % \ 167 exec('system [all...] |
/gem5/configs/example/ |
H A D | garnet_synth_traffic.py | 116 # create the desired simulated system 117 system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)]) variable 121 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 123 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 124 voltage_domain = system.voltage_domain) 126 Ruby.create_system(options, False, system) 129 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 130 voltage_domain = system.voltage_domain) 133 for ruby_port in system.ruby._cpu_ports: 144 root = Root(full_system = False, system [all...] |
H A D | memtest.py | 52 # This example script stress tests the memory system by creating false 56 # of testers and caches. Thus, it is possible to create a system with 109 help = """Top-level clock for blocks running at system 225 # Set up the system along with a simple memory and reference memory 226 system = System(physmem = SimpleMemory(), variable 229 system.voltage_domain = VoltageDomain(voltage = '1V') 231 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 232 voltage_domain = system.voltage_domain) 248 setattr(system, 'l%dsubsys%d' % (level, index), subsys) 307 last_subsys = getattr(system, ' [all...] |
H A D | memcheck.py | 67 # it is designed to stress tests the memory system. However, this 75 # it is possible to create a system with arbitrarily deep cache 108 help = """Top-level clock for blocks running at system 221 # Set up the system along with a DRAM controller 222 system = System(physmem = DDR3_1600_8x8()) variable 224 system.voltage_domain = VoltageDomain(voltage = '1V') 226 system.clk_domain = SrcClockDomain(clock = options.sys_clock, 227 voltage_domain = system.voltage_domain) 229 system.memchecker = MemChecker() 245 setattr(system, ' [all...] |
/gem5/configs/splash2/ |
H A D | run.py | 197 # Create a system, and add system wide objects 199 system = System(cpu = cpus, physmem = SimpleMemory(), variable 201 system.clock = '1GHz' 203 system.toL2bus = L2XBar(clock = busFrequency) 204 system.l2 = L2(size = options.l2size, assoc = 8) 210 system.physmem.port = system.membus.master 211 system.l2.cpu_side = system [all...] |
/gem5/src/mem/ |
H A D | abstract_mem.cc | 55 #include "sim/system.hh" 72 assert(system()); 98 assert(system()); 101 .init(system()->maxMasters()) 106 for (int i = 0; i < system()->maxMasters(); i++) { 107 bytesRead.subname(i, system()->getMasterName(i)); 110 .init(system()->maxMasters()) 115 for (int i = 0; i < system()->maxMasters(); i++) { 116 bytesInstRead.subname(i, system()->getMasterName(i)); 119 .init(system() [all...] |
H A D | ExternalMaster.py | 56 system = Param.System(Parent.any, 'System this external port belongs to') variable in class:ExternalMaster
|
/gem5/src/arch/mips/ |
H A D | MipsISA.py | 47 system = Param.System(Parent.any, "System this ISA object belongs to") variable in class:MipsISA
|
/gem5/src/dev/storage/ |
H A D | simple_disk.hh | 32 * Simple disk interface for the system console 53 System *system; member in class:SimpleDisk
|
/gem5/src/dev/x86/ |
H A D | pc.hh | 50 /** Pointer to the system */ 51 System *system; member in class:Pc
|
/gem5/src/cpu/testers/directedtest/ |
H A D | DirectedGenerator.cc | 32 #include "sim/system.hh" 36 masterId(p->system->getMasterId(this))
|
/gem5/tests/configs/ |
H A D | x86_generic.py | 60 system = FSConfig.makeLinuxX86System(self.mem_mode, 63 system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9') 65 self.init_system(system) 66 return system 70 """Basic X86 full system builder.""" 73 """Initialize an X86 system that supports full system simulation. 92 """Basic X86 full system builder for uniprocessor systems. 112 """Uniprocessor X86 system prepared for CPU switching"""
|
H A D | arm_generic.py | 80 num_cpus -- integer number of CPUs in the system 81 use_ruby -- True if ruby is used instead of the classic memory system 90 system = FSConfig.makeArmSystem(self.mem_mode, 97 system.panic_on_panic = True 98 system.panic_on_oops = True 105 system.kernel = SysPaths.binary(default_kernels[self.machine_type]) 112 system.dtb_filename = SysPaths.binary(default_dtbs[self.machine_type]) 114 self.init_system(system) 115 return system 119 """Basic ARM full system builde [all...] |
H A D | switcheroo.py | 49 The sequential CPU switches between all CPUs in a system in 50 order. The CPUs in the system must have been prepared for 53 system. 64 fatal("The system contains no switched in CPUs") 79 The switcheroo test runner is used to switch CPUs in a system that 86 switcher sequentially switches between all CPUs in a system, 90 the memory mode of the system based on the first CPU the switcher 101 switcher = Sequential(root.system.cpu) 104 system = root.system [all...] |
/gem5/src/learning_gem5/part2/ |
H A D | SimpleCache.py | 47 system = Param.System(Parent.any, "The system this cache is part of") variable in class:SimpleCache
|
/gem5/configs/ruby/ |
H A D | Ruby.py | 64 help="Clock for blocks running at Ruby system's speed") 89 def setup_memory_controllers(system, ruby, dir_cntrls, options): 111 if len(system.mem_ranges) > 1: 117 for r in system.mem_ranges: 141 system.mem_ctrls = mem_ctrls 157 def create_system(options, full_system, system, piobus = None, dma_ports = [], 160 system.ruby = RubySystem() 161 ruby = system.ruby 164 FileSystemConfig.config_filesystem(system, options) 175 eval("%s.create_system(options, full_system, system, dma_port [all...] |
/gem5/src/dev/mips/ |
H A D | malta.cc | 47 #include "sim/system.hh" 52 : Platform(p), system(p->system)
|
/gem5/src/dev/sparc/ |
H A D | t1000.cc | 42 #include "sim/system.hh" 47 : Platform(p), system(p->system)
|
H A D | t1000.hh | 49 /** Pointer to the system */ 50 System *system; member in class:T1000 57 * @param s system the object belongs to
|
/gem5/src/systemc/tlm_bridge/ |
H A D | TlmBridge.py | 40 system = Param.System(Parent.any, "system") variable in class:Gem5ToTlmBridgeBase 52 system = Param.System(Parent.any, "system") variable in class:TlmToGem5BridgeBase
|