12391SN/A/* 213998Stiago.muck@arm.com * Copyright (c) 2010-2012,2017-2019 ARM Limited 37733SN/A * All rights reserved 47733SN/A * 57733SN/A * The license below extends only to copyright in the software and shall 67733SN/A * not be construed as granting a license to any other intellectual 77733SN/A * property including but not limited to intellectual property relating 87733SN/A * to a hardware implementation of the functionality of the software 97733SN/A * licensed hereunder. You may use the software subject to the license 107733SN/A * terms below provided that you ensure that this notice is replicated 117733SN/A * unmodified and in its entirety in all distributions of the software, 127733SN/A * modified or unmodified, in source code or in binary form. 137733SN/A * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 412914SN/A * Ali Saidi 428931Sandreas.hansson@arm.com * Andreas Hansson 432391SN/A */ 442391SN/A 4511793Sbrandon.potter@amd.com#include "mem/abstract_mem.hh" 4611793Sbrandon.potter@amd.com 4710466Sandreas.hansson@arm.com#include <vector> 4810466Sandreas.hansson@arm.com 4912218Snikos.nikoleris@arm.com#include "arch/locked_mem.hh" 5010102Sali.saidi@arm.com#include "cpu/base.hh" 5110102Sali.saidi@arm.com#include "cpu/thread_context.hh" 528232SN/A#include "debug/LLSC.hh" 538232SN/A#include "debug/MemoryAccess.hh" 543879SN/A#include "mem/packet_access.hh" 559053Sdam.sunwoo@arm.com#include "sim/system.hh" 562394SN/A 572391SN/Ausing namespace std; 582391SN/A 598931Sandreas.hansson@arm.comAbstractMemory::AbstractMemory(const Params *p) : 6013892Sgabeblack@google.com ClockedObject(p), range(params()->range), pmemAddr(NULL), 6113853Sgabeblack@google.com backdoor(params()->range, nullptr, 6213853Sgabeblack@google.com (MemBackdoor::Flags)(MemBackdoor::Readable | 6313853Sgabeblack@google.com MemBackdoor::Writeable)), 649053Sdam.sunwoo@arm.com confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 6511614Sdavid.j.hashe@gmail.com kvmMap(p->kvm_map), _system(NULL) 662391SN/A{ 6710466Sandreas.hansson@arm.com} 6810466Sandreas.hansson@arm.com 6910466Sandreas.hansson@arm.comvoid 7010466Sandreas.hansson@arm.comAbstractMemory::init() 7110466Sandreas.hansson@arm.com{ 7210466Sandreas.hansson@arm.com assert(system()); 7310466Sandreas.hansson@arm.com 7410466Sandreas.hansson@arm.com if (size() % _system->getPageBytes() != 0) 752391SN/A panic("Memory Size not divisible by page size\n"); 762391SN/A} 772391SN/A 789293Sandreas.hansson@arm.comvoid 799293Sandreas.hansson@arm.comAbstractMemory::setBackingStore(uint8_t* pmem_addr) 802391SN/A{ 8113853Sgabeblack@google.com // If there was an existing backdoor, let everybody know it's going away. 8213853Sgabeblack@google.com if (backdoor.ptr()) 8313853Sgabeblack@google.com backdoor.invalidate(); 8413853Sgabeblack@google.com 8513853Sgabeblack@google.com // The back door can't handle interleaved memory. 8613853Sgabeblack@google.com backdoor.ptr(range.interleaved() ? nullptr : pmem_addr); 8713853Sgabeblack@google.com 889293Sandreas.hansson@arm.com pmemAddr = pmem_addr; 892391SN/A} 902391SN/A 918719SN/Avoid 928931Sandreas.hansson@arm.comAbstractMemory::regStats() 938719SN/A{ 9413892Sgabeblack@google.com ClockedObject::regStats(); 9511522Sstephan.diestelhorst@arm.com 968719SN/A using namespace Stats; 978719SN/A 989053Sdam.sunwoo@arm.com assert(system()); 999053Sdam.sunwoo@arm.com 1008719SN/A bytesRead 1019053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1028719SN/A .name(name() + ".bytes_read") 1038719SN/A .desc("Number of bytes read from this memory") 1049053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1058719SN/A ; 1069053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1079053Sdam.sunwoo@arm.com bytesRead.subname(i, system()->getMasterName(i)); 1089053Sdam.sunwoo@arm.com } 1098719SN/A bytesInstRead 1109053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1118719SN/A .name(name() + ".bytes_inst_read") 1128719SN/A .desc("Number of instructions bytes read from this memory") 1139053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1148719SN/A ; 1159053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1169053Sdam.sunwoo@arm.com bytesInstRead.subname(i, system()->getMasterName(i)); 1179053Sdam.sunwoo@arm.com } 1188719SN/A bytesWritten 1199053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1208719SN/A .name(name() + ".bytes_written") 1218719SN/A .desc("Number of bytes written to this memory") 1229053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1238719SN/A ; 1249053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1259053Sdam.sunwoo@arm.com bytesWritten.subname(i, system()->getMasterName(i)); 1269053Sdam.sunwoo@arm.com } 1278719SN/A numReads 1289053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1298719SN/A .name(name() + ".num_reads") 1308719SN/A .desc("Number of read requests responded to by this memory") 1319053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1328719SN/A ; 1339053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1349053Sdam.sunwoo@arm.com numReads.subname(i, system()->getMasterName(i)); 1359053Sdam.sunwoo@arm.com } 1368719SN/A numWrites 1379053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1388719SN/A .name(name() + ".num_writes") 1398719SN/A .desc("Number of write requests responded to by this memory") 1409053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1418719SN/A ; 1429053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1439053Sdam.sunwoo@arm.com numWrites.subname(i, system()->getMasterName(i)); 1449053Sdam.sunwoo@arm.com } 1458719SN/A numOther 1469053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1478719SN/A .name(name() + ".num_other") 1488719SN/A .desc("Number of other requests responded to by this memory") 1499053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1508719SN/A ; 1519053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1529053Sdam.sunwoo@arm.com numOther.subname(i, system()->getMasterName(i)); 1539053Sdam.sunwoo@arm.com } 1548719SN/A bwRead 1558719SN/A .name(name() + ".bw_read") 1568719SN/A .desc("Total read bandwidth from this memory (bytes/s)") 1578719SN/A .precision(0) 1588719SN/A .prereq(bytesRead) 1599053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1608719SN/A ; 1619053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1629053Sdam.sunwoo@arm.com bwRead.subname(i, system()->getMasterName(i)); 1639053Sdam.sunwoo@arm.com } 1649053Sdam.sunwoo@arm.com 1658719SN/A bwInstRead 1668719SN/A .name(name() + ".bw_inst_read") 1678719SN/A .desc("Instruction read bandwidth from this memory (bytes/s)") 1688719SN/A .precision(0) 1698719SN/A .prereq(bytesInstRead) 1709053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1718719SN/A ; 1729053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1739053Sdam.sunwoo@arm.com bwInstRead.subname(i, system()->getMasterName(i)); 1749053Sdam.sunwoo@arm.com } 1758719SN/A bwWrite 1768719SN/A .name(name() + ".bw_write") 1778719SN/A .desc("Write bandwidth from this memory (bytes/s)") 1788719SN/A .precision(0) 1798719SN/A .prereq(bytesWritten) 1809053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1818719SN/A ; 1829053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1839053Sdam.sunwoo@arm.com bwWrite.subname(i, system()->getMasterName(i)); 1849053Sdam.sunwoo@arm.com } 1858719SN/A bwTotal 1868719SN/A .name(name() + ".bw_total") 1878719SN/A .desc("Total bandwidth to/from this memory (bytes/s)") 1888719SN/A .precision(0) 1898719SN/A .prereq(bwTotal) 1909053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1918719SN/A ; 1929053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1939053Sdam.sunwoo@arm.com bwTotal.subname(i, system()->getMasterName(i)); 1949053Sdam.sunwoo@arm.com } 1958719SN/A bwRead = bytesRead / simSeconds; 1968719SN/A bwInstRead = bytesInstRead / simSeconds; 1978719SN/A bwWrite = bytesWritten / simSeconds; 1988719SN/A bwTotal = (bytesRead + bytesWritten) / simSeconds; 1998719SN/A} 2008719SN/A 2019235Sandreas.hansson@arm.comAddrRange 2029098Sandreas.hansson@arm.comAbstractMemory::getAddrRange() const 2032408SN/A{ 2048931Sandreas.hansson@arm.com return range; 2052408SN/A} 2062408SN/A 2073170SN/A// Add load-locked to tracking list. Should only be called if the 2086076SN/A// operation is a load and the LLSC flag is set. 2093170SN/Avoid 2108931Sandreas.hansson@arm.comAbstractMemory::trackLoadLocked(PacketPtr pkt) 2113170SN/A{ 21212749Sgiacomo.travaglini@arm.com const RequestPtr &req = pkt->req; 2133170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2143170SN/A 2153170SN/A // first we check if we already have a locked addr for this 2163170SN/A // xc. Since each xc only gets one, we just update the 2173170SN/A // existing record with the new address. 2183170SN/A list<LockedAddr>::iterator i; 2193170SN/A 2203170SN/A for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 2213170SN/A if (i->matchesContext(req)) { 2225714SN/A DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 2235714SN/A req->contextId(), paddr); 2243170SN/A i->addr = paddr; 2253170SN/A return; 2263170SN/A } 2273170SN/A } 2283170SN/A 2293170SN/A // no record for this xc: need to allocate a new one 2305714SN/A DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 2315714SN/A req->contextId(), paddr); 2323170SN/A lockedAddrList.push_front(LockedAddr(req)); 2333170SN/A} 2343170SN/A 2353170SN/A 2363170SN/A// Called on *writes* only... both regular stores and 2373170SN/A// store-conditional operations. Check for conventional stores which 2383170SN/A// conflict with locked addresses, and for success/failure of store 2393170SN/A// conditionals. 2403170SN/Abool 2418931Sandreas.hansson@arm.comAbstractMemory::checkLockedAddrList(PacketPtr pkt) 2423170SN/A{ 24312749Sgiacomo.travaglini@arm.com const RequestPtr &req = pkt->req; 2443170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2456102SN/A bool isLLSC = pkt->isLLSC(); 2463170SN/A 2473170SN/A // Initialize return value. Non-conditional stores always 2483170SN/A // succeed. Assume conditional stores will fail until proven 2493170SN/A // otherwise. 2509080Smatt.evans@arm.com bool allowStore = !isLLSC; 2513170SN/A 2529080Smatt.evans@arm.com // Iterate over list. Note that there could be multiple matching records, 2539080Smatt.evans@arm.com // as more than one context could have done a load locked to this location. 2549080Smatt.evans@arm.com // Only remove records when we succeed in finding a record for (xc, addr); 2559080Smatt.evans@arm.com // then, remove all records with this address. Failed store-conditionals do 2569080Smatt.evans@arm.com // not blow unrelated reservations. 2573170SN/A list<LockedAddr>::iterator i = lockedAddrList.begin(); 2583170SN/A 2599080Smatt.evans@arm.com if (isLLSC) { 2609080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2619080Smatt.evans@arm.com if (i->addr == paddr && i->matchesContext(req)) { 2629080Smatt.evans@arm.com // it's a store conditional, and as far as the memory system can 2639080Smatt.evans@arm.com // tell, the requesting context's lock is still valid. 2645714SN/A DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 2655714SN/A req->contextId(), paddr); 2669080Smatt.evans@arm.com allowStore = true; 2679080Smatt.evans@arm.com break; 2683170SN/A } 2699080Smatt.evans@arm.com // If we didn't find a match, keep searching! Someone else may well 2709080Smatt.evans@arm.com // have a reservation on this line here but we may find ours in just 2719080Smatt.evans@arm.com // a little while. 2729080Smatt.evans@arm.com i++; 2733170SN/A } 2749080Smatt.evans@arm.com req->setExtraData(allowStore ? 1 : 0); 2759080Smatt.evans@arm.com } 2769080Smatt.evans@arm.com // LLSCs that succeeded AND non-LLSC stores both fall into here: 2779080Smatt.evans@arm.com if (allowStore) { 2789080Smatt.evans@arm.com // We write address paddr. However, there may be several entries with a 2799080Smatt.evans@arm.com // reservation on this address (for other contextIds) and they must all 2809080Smatt.evans@arm.com // be removed. 2819080Smatt.evans@arm.com i = lockedAddrList.begin(); 2829080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2839080Smatt.evans@arm.com if (i->addr == paddr) { 2849080Smatt.evans@arm.com DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 2859080Smatt.evans@arm.com i->contextId, paddr); 28612218Snikos.nikoleris@arm.com ContextID owner_cid = i->contextId; 28713998Stiago.muck@arm.com assert(owner_cid != InvalidContextID); 28813998Stiago.muck@arm.com ContextID requester_cid = req->hasContextId() ? 28913998Stiago.muck@arm.com req->contextId() : 29013998Stiago.muck@arm.com InvalidContextID; 29112218Snikos.nikoleris@arm.com if (owner_cid != requester_cid) { 29212218Snikos.nikoleris@arm.com ThreadContext* ctx = system()->getThreadContext(owner_cid); 29312218Snikos.nikoleris@arm.com TheISA::globalClearExclusive(ctx); 29412218Snikos.nikoleris@arm.com } 2959080Smatt.evans@arm.com i = lockedAddrList.erase(i); 2969080Smatt.evans@arm.com } else { 2979080Smatt.evans@arm.com i++; 2989080Smatt.evans@arm.com } 2993170SN/A } 3003170SN/A } 3013170SN/A 3029080Smatt.evans@arm.com return allowStore; 3033170SN/A} 3043170SN/A 30513486Sgiacomo.travaglini@arm.com#if TRACING_ON 30613346Sgabeblack@google.comstatic inline void 30713346Sgabeblack@google.comtracePacket(System *sys, const char *label, PacketPtr pkt) 30813346Sgabeblack@google.com{ 30913346Sgabeblack@google.com int size = pkt->getSize(); 31013346Sgabeblack@google.com#if THE_ISA != NULL_ISA 31113346Sgabeblack@google.com if (size == 1 || size == 2 || size == 4 || size == 8) { 31213346Sgabeblack@google.com DPRINTF(MemoryAccess,"%s from %s of size %i on address %#x data " 31313346Sgabeblack@google.com "%#x %c\n", label, sys->getMasterName(pkt->req->masterId()), 31413346Sgabeblack@google.com size, pkt->getAddr(), pkt->getUintX(TheISA::GuestByteOrder), 31513346Sgabeblack@google.com pkt->req->isUncacheable() ? 'U' : 'C'); 31613346Sgabeblack@google.com return; 31713346Sgabeblack@google.com } 31813346Sgabeblack@google.com#endif 31913346Sgabeblack@google.com DPRINTF(MemoryAccess, "%s from %s of size %i on address %#x %c\n", 32013346Sgabeblack@google.com label, sys->getMasterName(pkt->req->masterId()), 32113346Sgabeblack@google.com size, pkt->getAddr(), pkt->req->isUncacheable() ? 'U' : 'C'); 32213346Sgabeblack@google.com DDUMP(MemoryAccess, pkt->getConstPtr<uint8_t>(), pkt->getSize()); 32313346Sgabeblack@google.com} 3244626SN/A 32513346Sgabeblack@google.com# define TRACE_PACKET(A) tracePacket(system(), A, pkt) 3264626SN/A#else 32713346Sgabeblack@google.com# define TRACE_PACKET(A) 3284626SN/A#endif 3294626SN/A 3308931Sandreas.hansson@arm.comvoid 3318931Sandreas.hansson@arm.comAbstractMemory::access(PacketPtr pkt) 3322413SN/A{ 33311284Sandreas.hansson@arm.com if (pkt->cacheResponding()) { 33411284Sandreas.hansson@arm.com DPRINTF(MemoryAccess, "Cache responding to %#llx: not responding\n", 3354626SN/A pkt->getAddr()); 3368931Sandreas.hansson@arm.com return; 3373175SN/A } 3384626SN/A 33911199Sandreas.hansson@arm.com if (pkt->cmd == MemCmd::CleanEvict || pkt->cmd == MemCmd::WritebackClean) { 34010883Sali.jafri@arm.com DPRINTF(MemoryAccess, "CleanEvict on 0x%x: not responding\n", 34110883Sali.jafri@arm.com pkt->getAddr()); 34210883Sali.jafri@arm.com return; 34310883Sali.jafri@arm.com } 34410883Sali.jafri@arm.com 34513856Sodanrc@yahoo.com.br assert(pkt->getAddrRange().isSubset(range)); 34610883Sali.jafri@arm.com 3479405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 3484626SN/A 3494626SN/A if (pkt->cmd == MemCmd::SwapReq) { 35011306Santhony.gutierrez@amd.com if (pkt->isAtomicOp()) { 35111306Santhony.gutierrez@amd.com if (pmemAddr) { 35213377Sodanrc@yahoo.com.br pkt->setData(hostAddr); 35311306Santhony.gutierrez@amd.com (*(pkt->getAtomicOp()))(hostAddr); 35411306Santhony.gutierrez@amd.com } 35511306Santhony.gutierrez@amd.com } else { 35611306Santhony.gutierrez@amd.com std::vector<uint8_t> overwrite_val(pkt->getSize()); 35711306Santhony.gutierrez@amd.com uint64_t condition_val64; 35811306Santhony.gutierrez@amd.com uint32_t condition_val32; 3594040SN/A 36013377Sodanrc@yahoo.com.br panic_if(!pmemAddr, "Swap only works if there is real memory " \ 36113377Sodanrc@yahoo.com.br "(i.e. null=False)"); 3624040SN/A 36311306Santhony.gutierrez@amd.com bool overwrite_mem = true; 36411306Santhony.gutierrez@amd.com // keep a copy of our possible write value, and copy what is at the 36511306Santhony.gutierrez@amd.com // memory address into the packet 36613377Sodanrc@yahoo.com.br pkt->writeData(&overwrite_val[0]); 36713377Sodanrc@yahoo.com.br pkt->setData(hostAddr); 3684040SN/A 36911306Santhony.gutierrez@amd.com if (pkt->req->isCondSwap()) { 37011306Santhony.gutierrez@amd.com if (pkt->getSize() == sizeof(uint64_t)) { 37111306Santhony.gutierrez@amd.com condition_val64 = pkt->req->getExtraData(); 37211306Santhony.gutierrez@amd.com overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 37311306Santhony.gutierrez@amd.com sizeof(uint64_t)); 37411306Santhony.gutierrez@amd.com } else if (pkt->getSize() == sizeof(uint32_t)) { 37511306Santhony.gutierrez@amd.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 37611306Santhony.gutierrez@amd.com overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 37711306Santhony.gutierrez@amd.com sizeof(uint32_t)); 37811306Santhony.gutierrez@amd.com } else 37911306Santhony.gutierrez@amd.com panic("Invalid size for conditional read/write\n"); 38011306Santhony.gutierrez@amd.com } 38111306Santhony.gutierrez@amd.com 38211306Santhony.gutierrez@amd.com if (overwrite_mem) 38311306Santhony.gutierrez@amd.com std::memcpy(hostAddr, &overwrite_val[0], pkt->getSize()); 38411306Santhony.gutierrez@amd.com 38511306Santhony.gutierrez@amd.com assert(!pkt->req->isInstFetch()); 38611306Santhony.gutierrez@amd.com TRACE_PACKET("Read/Write"); 38711306Santhony.gutierrez@amd.com numOther[pkt->req->masterId()]++; 3884040SN/A } 3894626SN/A } else if (pkt->isRead()) { 3904626SN/A assert(!pkt->isWrite()); 3916102SN/A if (pkt->isLLSC()) { 39212218Snikos.nikoleris@arm.com assert(!pkt->fromCache()); 39312218Snikos.nikoleris@arm.com // if the packet is not coming from a cache then we have 39412218Snikos.nikoleris@arm.com // to do the LL/SC tracking here 3954626SN/A trackLoadLocked(pkt); 3964040SN/A } 39713377Sodanrc@yahoo.com.br if (pmemAddr) { 39813377Sodanrc@yahoo.com.br pkt->setData(hostAddr); 39913377Sodanrc@yahoo.com.br } 4006429SN/A TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 4019053Sdam.sunwoo@arm.com numReads[pkt->req->masterId()]++; 4029053Sdam.sunwoo@arm.com bytesRead[pkt->req->masterId()] += pkt->getSize(); 4038719SN/A if (pkt->req->isInstFetch()) 4049053Sdam.sunwoo@arm.com bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 40512354Snikos.nikoleris@arm.com } else if (pkt->isInvalidate() || pkt->isClean()) { 40612354Snikos.nikoleris@arm.com assert(!pkt->isWrite()); 40712354Snikos.nikoleris@arm.com // in a fastmem system invalidating and/or cleaning packets 40812354Snikos.nikoleris@arm.com // can be seen due to cache maintenance requests 40912354Snikos.nikoleris@arm.com 41010583SCurtis.Dunham@arm.com // no need to do anything 4114626SN/A } else if (pkt->isWrite()) { 4124626SN/A if (writeOK(pkt)) { 4139663Suri.wiener@arm.com if (pmemAddr) { 41413377Sodanrc@yahoo.com.br pkt->writeData(hostAddr); 41511653SBrad.Beckmann@amd.com DPRINTF(MemoryAccess, "%s wrote %i bytes to address %x\n", 4169663Suri.wiener@arm.com __func__, pkt->getSize(), pkt->getAddr()); 4179663Suri.wiener@arm.com } 4186429SN/A assert(!pkt->req->isInstFetch()); 4194626SN/A TRACE_PACKET("Write"); 4209053Sdam.sunwoo@arm.com numWrites[pkt->req->masterId()]++; 4219053Sdam.sunwoo@arm.com bytesWritten[pkt->req->masterId()] += pkt->getSize(); 4224626SN/A } 4234040SN/A } else { 42412354Snikos.nikoleris@arm.com panic("Unexpected packet %s", pkt->print()); 4252413SN/A } 4262420SN/A 4274626SN/A if (pkt->needsResponse()) { 4288931Sandreas.hansson@arm.com pkt->makeResponse(); 4294626SN/A } 4302413SN/A} 4312413SN/A 4328931Sandreas.hansson@arm.comvoid 4338931Sandreas.hansson@arm.comAbstractMemory::functionalAccess(PacketPtr pkt) 4348931Sandreas.hansson@arm.com{ 43513856Sodanrc@yahoo.com.br assert(pkt->getAddrRange().isSubset(range)); 4364626SN/A 4379405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 4384626SN/A 4395314SN/A if (pkt->isRead()) { 44013377Sodanrc@yahoo.com.br if (pmemAddr) { 44113377Sodanrc@yahoo.com.br pkt->setData(hostAddr); 44213377Sodanrc@yahoo.com.br } 4434626SN/A TRACE_PACKET("Read"); 4448931Sandreas.hansson@arm.com pkt->makeResponse(); 4455314SN/A } else if (pkt->isWrite()) { 44613377Sodanrc@yahoo.com.br if (pmemAddr) { 44713377Sodanrc@yahoo.com.br pkt->writeData(hostAddr); 44813377Sodanrc@yahoo.com.br } 4494626SN/A TRACE_PACKET("Write"); 4508931Sandreas.hansson@arm.com pkt->makeResponse(); 4515314SN/A } else if (pkt->isPrint()) { 4525315SN/A Packet::PrintReqState *prs = 4535315SN/A dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 4548992SAli.Saidi@ARM.com assert(prs); 4555315SN/A // Need to call printLabels() explicitly since we're not going 4565315SN/A // through printObj(). 4575314SN/A prs->printLabels(); 4585315SN/A // Right now we just print the single byte at the specified address. 4595314SN/A ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 4604626SN/A } else { 4618931Sandreas.hansson@arm.com panic("AbstractMemory: unimplemented functional command %s", 4624626SN/A pkt->cmdString()); 4634626SN/A } 4644490SN/A} 465