Lines Matching refs:system
67 # it is designed to stress tests the memory system. However, this
75 # it is possible to create a system with arbitrarily deep cache
108 help = """Top-level clock for blocks running at system
221 # Set up the system along with a DRAM controller
222 system = System(physmem = DDR3_1600_8x8())
224 system.voltage_domain = VoltageDomain(voltage = '1V')
226 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
227 voltage_domain = system.voltage_domain)
229 system.memchecker = MemChecker()
245 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
251 checkers = [MemCheckerMonitor(memchecker = system.memchecker) \
301 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
302 last_subsys.xbar.master = system.physmem.port
305 root = Root(full_system = False, system = system)
307 root.system.mem_mode = 'atomic'
309 root.system.mem_mode = 'timing'
311 # The system port is never used in the tester so merely connect it
313 root.system.system_port = last_subsys.xbar.slave