1# Copyright (c) 2012, 2017, 2019 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Sandberg 37 38from abc import ABCMeta, abstractmethod 39import m5 40from m5.objects import * 41from m5.proxy import * 42m5.util.addToPath('../configs/') 43from common import FSConfig 44from common.Caches import * 45from base_config import * 46from common.cores.arm.O3_ARM_v7a import * 47from common.Benchmarks import SysConfig 48 49from common import SysPaths 50 51class ArmSESystemUniprocessor(BaseSESystemUniprocessor): 52 """Syscall-emulation builder for ARM uniprocessor systems. 53 54 A small tweak of the syscall-emulation builder to use more 55 representative cache configurations. 56 """ 57 58 def __init__(self, **kwargs): 59 BaseSESystem.__init__(self, **kwargs) 60 61 def create_caches_private(self, cpu): 62 # The atomic SE configurations do not use caches 63 if self.mem_mode == "timing": 64 # Use the more representative cache configuration 65 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 66 O3_ARM_v7a_DCache(), 67 O3_ARM_v7aL2()) 68 69class LinuxArmSystemBuilder(object): 70 """Mix-in that implements create_system. 71 72 This mix-in is intended as a convenient way of adding an 73 ARM-specific create_system method to a class deriving from one of 74 the generic base systems. 75 """ 76 def __init__(self, machine_type, **kwargs): 77 """ 78 Arguments: 79 machine_type -- String describing the platform to simulate 80 num_cpus -- integer number of CPUs in the system 81 use_ruby -- True if ruby is used instead of the classic memory system 82 """ 83 self.machine_type = machine_type 84 self.num_cpus = kwargs.get('num_cpus', 1) 85 self.mem_size = kwargs.get('mem_size', '256MB') 86 self.use_ruby = kwargs.get('use_ruby', False) 87 88 def create_system(self): 89 sc = SysConfig(None, self.mem_size, None) 90 system = FSConfig.makeArmSystem(self.mem_mode, 91 self.machine_type, self.num_cpus, 92 sc, False, ruby=self.use_ruby) 93 94 # We typically want the simulator to panic if the kernel 95 # panics or oopses. This prevents the simulator from running 96 # an obviously failed test case until the end of time. 97 system.panic_on_panic = True 98 system.panic_on_oops = True 99 100 default_kernels = { 101 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 102 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 103 "VExpress_EMM64": "vmlinux.aarch64.20140821", 104 } 105 system.kernel = SysPaths.binary(default_kernels[self.machine_type]) 106 default_dtbs = { 107 "RealViewPBX": None, 108 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \ 109 .format(self.num_cpus), 110 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 111 } 112 system.dtb_filename = SysPaths.binary(default_dtbs[self.machine_type]) 113 114 self.init_system(system) 115 return system 116 117class LinuxArmFSSystem(LinuxArmSystemBuilder, 118 BaseFSSystem): 119 """Basic ARM full system builder.""" 120 121 def __init__(self, machine_type='VExpress_EMM', **kwargs): 122 """Initialize an ARM system that supports full system simulation. 123 124 Note: Keyword arguments that are not listed below will be 125 passed to the BaseFSSystem. 126 127 Keyword Arguments: 128 machine_type -- String describing the platform to simulate 129 """ 130 BaseSystem.__init__(self, **kwargs) 131 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 132 133 def create_caches_private(self, cpu): 134 # Use the more representative cache configuration 135 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(), 136 O3_ARM_v7a_DCache(), 137 O3_ARM_v7aL2()) 138 139class LinuxArmFSSystemUniprocessor(LinuxArmSystemBuilder, 140 BaseFSSystemUniprocessor): 141 """Basic ARM full system builder for uniprocessor systems. 142 143 Note: This class is a specialization of the ArmFSSystem and is 144 only really needed to provide backwards compatibility for existing 145 test cases. 146 """ 147 148 def __init__(self, machine_type='VExpress_EMM', **kwargs): 149 BaseFSSystemUniprocessor.__init__(self, **kwargs) 150 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 151 152class LinuxArmFSSwitcheroo(LinuxArmSystemBuilder, BaseFSSwitcheroo): 153 """Uniprocessor ARM system prepared for CPU switching""" 154 155 def __init__(self, machine_type='VExpress_EMM', **kwargs): 156 BaseFSSwitcheroo.__init__(self, **kwargs) 157 LinuxArmSystemBuilder.__init__(self, machine_type, **kwargs) 158