Lines Matching refs:system
116 # create the desired simulated system
117 system = System(cpu = cpus, mem_ranges = [AddrRange(options.mem_size)])
121 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
123 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
124 voltage_domain = system.voltage_domain)
126 Ruby.create_system(options, False, system)
129 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
130 voltage_domain = system.voltage_domain)
133 for ruby_port in system.ruby._cpu_ports:
144 root = Root(full_system = False, system = system)
145 root.system.mem_mode = 'timing'