Lines Matching refs:system
52 # This example script stress tests the memory system by creating false
56 # of testers and caches. Thus, it is possible to create a system with
109 help = """Top-level clock for blocks running at system
225 # Set up the system along with a simple memory and reference memory
226 system = System(physmem = SimpleMemory(),
229 system.voltage_domain = VoltageDomain(voltage = '1V')
231 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
232 voltage_domain = system.voltage_domain)
248 setattr(system, 'l%dsubsys%d' % (level, index), subsys)
307 last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
310 system.llc = NoncoherentCache(size = '16MB', assoc = 16, tag_latency = 10,
314 last_subsys.xbar.master = system.llc.cpu_side
315 system.llc.mem_side = system.physmem.port
317 last_subsys.xbar.master = system.physmem.port
319 root = Root(full_system = False, system = system)
321 root.system.mem_mode = 'atomic'
323 root.system.mem_mode = 'timing'
325 # The system port is never used in the tester so merely connect it
327 root.system.system_port = last_subsys.xbar.slave