Lines Matching refs:system
197 # Create a system, and add system wide objects
199 system = System(cpu = cpus, physmem = SimpleMemory(),
201 system.clock = '1GHz'
203 system.toL2bus = L2XBar(clock = busFrequency)
204 system.l2 = L2(size = options.l2size, assoc = 8)
210 system.physmem.port = system.membus.master
211 system.l2.cpu_side = system.toL2bus.master
212 system.l2.mem_side = system.membus.slave
213 system.system_port = system.membus.slave
222 cpu.connectAllPorts(system.toL2bus, system.membus)
229 root = Root(full_system = False, system = system)
277 root.system.mem_mode = 'timing'