/gem5/src/mem/ruby/system/ |
H A D | Sequencer.py | 37 cxx_header = "mem/ruby/system/RubyPort.hh" 50 system = Param.System(Parent.any, "system object") variable in class:RubyPort 57 cxx_header = "mem/ruby/system/RubyPortProxy.hh" 62 cxx_header = "mem/ruby/system/Sequencer.hh" 78 cxx_header = "mem/ruby/system/DMASequencer.hh"
|
H A D | RubyPort.cc | 42 #include "mem/ruby/system/RubyPort.hh" 52 #include "sim/system.hh" 57 m_usingRubyTester(p->using_ruby_tester), system(p->system), 218 if (!ruby_port->system->bypassCaches()) { 308 if (!ruby_port->system->bypassCaches()) { 424 assert(system->isMemAddr(pkt->getAddr())); 585 return ruby_port->system->isMemAddr(addr);
|
/gem5/src/sim/ |
H A D | Process.py | 45 system = Param.System(Parent.any, "system process will run on") variable in class:Process
|
/gem5/src/cpu/minor/ |
H A D | cpu.cc | 59 thread = new Minor::MinorThread(this, i, params->system, 63 thread = new Minor::MinorThread(this, i, params->system, 99 system->getMemoryMode() != Enums::timing) 101 fatal("The Minor CPU requires the memory system to be in " 238 if (!system->isTimingMode()) { 239 fatal("The Minor CPU requires the memory system to be in "
|
/gem5/util/stats/ |
H A D | profile.py | 287 def get(self, job, stat, system=None): 288 if system is None and hasattr('system', job): 289 system = job.system 291 if system is None: 292 raise AttributeError, 'The job must have a system set' 294 cpu = '%s.run%d' % (system, self.cpu) 322 cpu = '%s.run%d' % (job.system, self.cpu) 336 cpu = '%s.run%d' % (job.system, sel [all...] |
/gem5/src/cpu/ |
H A D | base.cc | 73 #include "sim/system.hh" 130 _instMasterId(p->system->getMasterId(this, "inst")), 131 _dataMasterId(p->system->getMasterId(this, "data")), 133 _switchedOut(p->switched_out), _cacheLineSize(p->system->cacheLineSize()), 135 numThreads(p->numThreads), system(p->system), 471 assert(system->multiThread || numThreads == 1); 477 if (system->multiThread) { 478 tc->setContextId(system->registerThreadContext(tc)); 480 tc->setContextId(system [all...] |
/gem5/configs/ruby/ |
H A D | MOESI_hammer.py | 56 def create_system(options, full_system, system, dma_ports, bootmem, 65 # The ruby network creation expects the list of nodes in the system to be 95 # is stored in system.cpu. because there is only ever one 97 # size of system.cpu; therefore if len(system.cpu) == 1 98 # we use system.cpu[0] to set the clk_domain, thereby ensuring 100 if len(system.cpu) == 1: 101 clk_domain = system.cpu[0].clk_domain 103 clk_domain = system.cpu[i].clk_domain 171 # the ruby system [all...] |
H A D | MOESI_CMP_token.py | 53 def create_system(options, full_system, system, dma_ports, bootmem, 68 # The ruby network creation expects the list of nodes in the system to be 96 # is stored in system.cpu. because there is only ever one 98 # size of system.cpu; therefore if len(system.cpu) == 1 99 # we use system.cpu[0] to set the clk_domain, thereby ensuring 101 if len(system.cpu) == 1: 102 clk_domain = system.cpu[0].clk_domain 104 clk_domain = system.cpu[i].clk_domain 188 # the ruby system [all...] |
H A D | MESI_Three_Level.py | 53 def create_system(options, full_system, system, dma_ports, bootmem, 63 # The ruby network creation expects the list of nodes in the system to be 102 # is stored in system.cpu. because there is only ever one 104 # size of system.cpu; therefore if len(system.cpu) == 1 105 # we use system.cpu[0] to set the clk_domain, thereby ensuring 107 if len(system.cpu) == 1: 108 clk_domain = system.cpu[0].clk_domain 110 clk_domain = system.cpu[i].clk_domain 199 # the ruby system [all...] |
/gem5/src/arch/arm/ |
H A D | isa.cc | 43 #include "arch/arm/system.hh" 56 #include "sim/system.hh" 63 system(NULL), 82 system = dynamic_cast<ArmSystem *>(p->system); 84 // Cache system-level properties 85 if (FullSystem && system) { 86 highestELIs64 = system->highestELIs64(); 87 haveSecurity = system->haveSecurity(); 88 haveLPAE = system [all...] |
H A D | ArmISA.py | 55 system = Param.System(Parent.any, "System this ISA object belongs to") variable in class:ArmISA
|
/gem5/configs/common/ |
H A D | Simulation.py | 102 def setWorkCountOptions(system, options): 104 system.work_item_id = options.work_item_id 106 system.num_work_ids = options.num_work_ids 108 system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 110 system.work_end_exit_count = options.work_end_exit_count 112 system.work_end_ckpt_count = options.work_end_checkpoint_count 114 system.work_begin_exit_count = options.work_begin_exit_count 116 system.work_begin_ckpt_count = options.work_begin_checkpoint_count 118 system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 471 switch_cpus[i].system [all...] |
/gem5/src/mem/ |
H A D | snoop_filter.hh | 57 #include "sim/system.hh" 85 * (4) ordering: there is no single point of order in the system. Instead, 98 linesize(p->system->cacheLineSize()), lookupLatency(p->lookup_latency), 99 maxEntryCount(p->max_capacity / p->system->cacheLineSize())
|
/gem5/src/mem/probes/ |
H A D | stack_dist.cc | 43 #include "sim/system.hh" 52 fatal_if(p->system->cacheLineSize() > p->line_size, 54 "larger or equal to the system's cahce line size.");
|
/gem5/util/tlm/src/ |
H A D | sc_master_port.hh | 100 System* system; member in class:Gem5SystemC::SCMasterPort
|
H A D | sc_master_port.cc | 41 #include "sim/system.hh" 98 system = 99 dynamic_cast<const ExternalMasterParams*>(owner_.params())->system; 117 if (system->isTimingMode()) { 121 } else if (system->isAtomicMode()) {
|
/gem5/src/arch/arm/kvm/ |
H A D | base_cpu.cc | 82 if (!((ArmSystem *)system)->highestELIs64()) {
|
/gem5/ext/pybind11/docs/ |
H A D | benchmark.py | 81 os.system("g++ -Os -shared -rdynamic -undefined dynamic_lookup "
|
/gem5/src/arch/x86/ |
H A D | remote_gdb.hh | 146 RemoteGDB(System *system, ThreadContext *context, int _port);
|
/gem5/src/mem/qos/ |
H A D | policy_pf.cc | 60 MasterID m_id = memCtrl->system()->lookupMasterId(master);
|
/gem5/ext/googletest/googletest/scripts/ |
H A D | release_docs.py | 135 os.system(command)
|
/gem5/src/dev/x86/ |
H A D | Pc.py | 52 system = Param.System(Parent.any, "system") variable in class:Pc
|
/gem5/src/mem/cache/ |
H A D | Cache.py | 119 system = Param.System(Parent.any, "System we belong to") variable in class:BaseCache
|
/gem5/src/dev/ |
H A D | Device.py | 53 system = Param.System(Parent.any, "System this device is part of") variable in class:PioDevice
|
/gem5/src/arch/alpha/ |
H A D | process.cc | 46 #include "sim/system.hh" 177 ThreadContext *tc = system->getThreadContext(contextIds[0]); 189 ThreadContext *tc = system->getThreadContext(contextIds[0]); 215 ThreadContext *tc = system->getThreadContext(contextIds[0]);
|