114272Sgiacomo.travaglini@arm.com# Copyright (c) 2012-2016,2019 ARM Limited 212472Sglenn.bergmans@arm.com# All rights reserved. 312472Sglenn.bergmans@arm.com# 412472Sglenn.bergmans@arm.com# The license below extends only to copyright in the software and shall 512472Sglenn.bergmans@arm.com# not be construed as granting a license to any other intellectual 612472Sglenn.bergmans@arm.com# property including but not limited to intellectual property relating 712472Sglenn.bergmans@arm.com# to a hardware implementation of the functionality of the software 812472Sglenn.bergmans@arm.com# licensed hereunder. You may use the software subject to the license 912472Sglenn.bergmans@arm.com# terms below provided that you ensure that this notice is replicated 1012472Sglenn.bergmans@arm.com# unmodified and in its entirety in all distributions of the software, 1112472Sglenn.bergmans@arm.com# modified or unmodified, in source code or in binary form. 1212472Sglenn.bergmans@arm.com# 134486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486Sbinkertn@umich.edu# 394486Sbinkertn@umich.edu# Authors: Nathan Binkert 4012472Sglenn.bergmans@arm.com# Glenn Bergmans 414486Sbinkertn@umich.edu 423102SN/Afrom m5.params import * 433102SN/Afrom m5.proxy import * 4412472Sglenn.bergmans@arm.comfrom m5.util.fdthelper import * 4513665Sandreas.sandberg@arm.com 4613892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 471310SN/A 4813892Sgabeblack@google.comclass PioDevice(ClockedObject): 491366SN/A type = 'PioDevice' 509338SAndreas.Sandberg@arm.com cxx_header = "dev/io_device.hh" 511310SN/A abstract = True 528839Sandreas.hansson@arm.com pio = SlavePort("Programmed I/O port") 532542SN/A system = Param.System(Parent.any, "System this device is part of") 541310SN/A 5512472Sglenn.bergmans@arm.com def generateBasicPioDeviceNode(self, state, name, pio_addr, 5612472Sglenn.bergmans@arm.com size, interrupts = None): 5712472Sglenn.bergmans@arm.com node = FdtNode("%s@%x" % (name, long(pio_addr))) 5812472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("reg", 5912472Sglenn.bergmans@arm.com state.addrCells(pio_addr) + 6012472Sglenn.bergmans@arm.com state.sizeCells(size) )) 6112472Sglenn.bergmans@arm.com 6212472Sglenn.bergmans@arm.com if interrupts: 6312472Sglenn.bergmans@arm.com if any([i < 32 for i in interrupts]): 6412472Sglenn.bergmans@arm.com raise(("Interrupt number smaller than 32 "+ 6512472Sglenn.bergmans@arm.com " in PioDevice %s") % name) 6612472Sglenn.bergmans@arm.com 6712472Sglenn.bergmans@arm.com # subtracting 32 because Linux assumes that SPIs start at 0, while 6812472Sglenn.bergmans@arm.com # gem5 uses the internal GIC numbering (SPIs start at 32) 6912472Sglenn.bergmans@arm.com node.append(FdtPropertyWords("interrupts", sum( 7012472Sglenn.bergmans@arm.com [[0, i - 32, 4] for i in interrupts], []) )) 7112472Sglenn.bergmans@arm.com 7212472Sglenn.bergmans@arm.com return node 7312472Sglenn.bergmans@arm.com 742542SN/Aclass BasicPioDevice(PioDevice): 752542SN/A type = 'BasicPioDevice' 769338SAndreas.Sandberg@arm.com cxx_header = "dev/io_device.hh" 771310SN/A abstract = True 782542SN/A pio_addr = Param.Addr("Device Address") 799198Sandreas.hansson@arm.com pio_latency = Param.Latency('100ns', "Programmed IO latency") 802565SN/A 812565SN/Aclass DmaDevice(PioDevice): 822565SN/A type = 'DmaDevice' 8311764Sandreas.sandberg@arm.com cxx_header = "dev/dma_device.hh" 842565SN/A abstract = True 858839Sandreas.hansson@arm.com dma = MasterPort("DMA port") 864439SN/A 8714272Sgiacomo.travaglini@arm.com _iommu = None 8814272Sgiacomo.travaglini@arm.com 8913930Sgiacomo.travaglini@arm.com sid = Param.Unsigned(0, 9013930Sgiacomo.travaglini@arm.com "Stream identifier used by an IOMMU to distinguish amongst " 9113930Sgiacomo.travaglini@arm.com "several devices attached to it") 9213930Sgiacomo.travaglini@arm.com ssid = Param.Unsigned(0, 9313930Sgiacomo.travaglini@arm.com "Substream identifier used by an IOMMU to distinguish amongst " 9413930Sgiacomo.travaglini@arm.com "several devices attached to it") 9513930Sgiacomo.travaglini@arm.com 9614272Sgiacomo.travaglini@arm.com def addIommuProperty(self, state, node): 9714272Sgiacomo.travaglini@arm.com """ 9814272Sgiacomo.travaglini@arm.com This method takes an FdtState and a FdtNode as parameters, and 9914272Sgiacomo.travaglini@arm.com it is appending a "iommus = <>" property in case the DmaDevice 10014272Sgiacomo.travaglini@arm.com is attached to an IOMMU. 10114272Sgiacomo.travaglini@arm.com This method is necessary for autogenerating a binding between 10214272Sgiacomo.travaglini@arm.com a dma device and the iommu. 10314272Sgiacomo.travaglini@arm.com """ 10414272Sgiacomo.travaglini@arm.com if self._iommu is not None: 10514272Sgiacomo.travaglini@arm.com node.append(FdtPropertyWords("iommus", 10614272Sgiacomo.travaglini@arm.com [ state.phandle(self._iommu), self.sid ])) 1073812SN/A 1083812SN/Aclass IsaFake(BasicPioDevice): 1093812SN/A type = 'IsaFake' 11010127SAndreas.Bardsley@arm.com cxx_header = "dev/isa_fake.hh" 1113812SN/A pio_size = Param.Addr(0x8, "Size of address range") 1123814SN/A ret_data8 = Param.UInt8(0xFF, "Default data to return") 1133814SN/A ret_data16 = Param.UInt16(0xFFFF, "Default data to return") 1143814SN/A ret_data32 = Param.UInt32(0xFFFFFFFF, "Default data to return") 1153814SN/A ret_data64 = Param.UInt64(0xFFFFFFFFFFFFFFFF, "Default data to return") 1163812SN/A ret_bad_addr = Param.Bool(False, "Return pkt status bad address on access") 1173814SN/A update_data = Param.Bool(False, "Update the data that is returned on writes") 1183814SN/A warn_access = Param.String("", "String to print when device is accessed") 1198461SAli.Saidi@ARM.com fake_mem = Param.Bool(False, 1208461SAli.Saidi@ARM.com "Is this device acting like a memory and thus may get a cache line sized req") 1213812SN/A 1223812SN/Aclass BadAddr(IsaFake): 1236122SSteve.Reinhardt@amd.com pio_addr = 0 1243812SN/A ret_bad_addr = Param.Bool(True, "Return pkt status bad address on access") 1253812SN/A 1263812SN/A 127