12207SN/A/*
22207SN/A * Copyright (c) 2003-2004 The Regents of The University of Michigan
32207SN/A * All rights reserved.
42207SN/A *
52207SN/A * Redistribution and use in source and binary forms, with or without
62207SN/A * modification, are permitted provided that the following conditions are
72207SN/A * met: redistributions of source code must retain the above copyright
82207SN/A * notice, this list of conditions and the following disclaimer;
92207SN/A * redistributions in binary form must reproduce the above copyright
102207SN/A * notice, this list of conditions and the following disclaimer in the
112207SN/A * documentation and/or other materials provided with the distribution;
122207SN/A * neither the name of the copyright holders nor the names of its
132207SN/A * contributors may be used to endorse or promote products derived from
142207SN/A * this software without specific prior written permission.
152207SN/A *
162207SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172207SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182207SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192207SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202207SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212207SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222207SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232207SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242207SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252207SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262207SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665Ssaidi@eecs.umich.edu *
282665Ssaidi@eecs.umich.edu * Authors: Gabe Black
292665Ssaidi@eecs.umich.edu *          Ali Saidi
302207SN/A */
312207SN/A
3211793Sbrandon.potter@amd.com#include "arch/alpha/process.hh"
3311793Sbrandon.potter@amd.com
342972Sgblack@eecs.umich.edu#include "arch/alpha/isa_traits.hh"
358229Snate@binkert.org#include "base/loader/elf_object.hh"
362454SN/A#include "base/loader/object_file.hh"
3712334Sgabeblack@google.com#include "base/logging.hh"
382680Sktlim@umich.edu#include "cpu/thread_context.hh"
398232Snate@binkert.org#include "debug/Loader.hh"
405759Shsul@eecs.umich.edu#include "mem/page_table.hh"
4112431Sgabeblack@google.com#include "params/Process.hh"
4211854Sbrandon.potter@amd.com#include "sim/aux_vector.hh"
437678Sgblack@eecs.umich.edu#include "sim/byteswap.hh"
445759Shsul@eecs.umich.edu#include "sim/process_impl.hh"
4511800Sbrandon.potter@amd.com#include "sim/syscall_return.hh"
462474SN/A#include "sim/system.hh"
472207SN/A
482474SN/Ausing namespace AlphaISA;
492474SN/Ausing namespace std;
502474SN/A
5111851Sbrandon.potter@amd.comAlphaProcess::AlphaProcess(ProcessParams *params, ObjectFile *objFile)
5212448Sgabeblack@google.com    : Process(params,
5312448Sgabeblack@google.com              new EmulationPageTable(params->name, params->pid, PageBytes),
5412432Sgabeblack@google.com      objFile)
552474SN/A{
5612441Sgabeblack@google.com    fatal_if(params->useArchPT, "Arch page tables not implemented.");
5711905SBrandon.Potter@amd.com    Addr brk_point = objFile->dataBase() + objFile->dataSize() +
5811905SBrandon.Potter@amd.com                     objFile->bssSize();
5911905SBrandon.Potter@amd.com    brk_point = roundUp(brk_point, PageBytes);
602474SN/A
612474SN/A    // Set up stack.  On Alpha, stack goes below text section.  This
622474SN/A    // code should get moved to some architecture-specific spot.
6311905SBrandon.Potter@amd.com    Addr stack_base = objFile->textBase() - (409600+4096);
642474SN/A
6511905SBrandon.Potter@amd.com    // Set up region for mmaps.
6611905SBrandon.Potter@amd.com    Addr mmap_end = 0x10000;
6711905SBrandon.Potter@amd.com
6811905SBrandon.Potter@amd.com    Addr max_stack_size = 8 * 1024 * 1024;
692474SN/A
702474SN/A    // Set pointer for next thread stack.  Reserve 8M for main stack.
7111905SBrandon.Potter@amd.com    Addr next_thread_stack_base = stack_base - max_stack_size;
722474SN/A
7311905SBrandon.Potter@amd.com    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
7411905SBrandon.Potter@amd.com                                     next_thread_stack_base, mmap_end);
752474SN/A}
762474SN/A
772474SN/Avoid
7811851Sbrandon.potter@amd.comAlphaProcess::argsInit(int intSize, int pageSize)
795759Shsul@eecs.umich.edu{
8011389Sbrandon.potter@amd.com    // Patch the ld_bias for dynamic executables.
8111389Sbrandon.potter@amd.com    updateBias();
8211389Sbrandon.potter@amd.com
835759Shsul@eecs.umich.edu    objFile->loadSections(initVirtMem);
845759Shsul@eecs.umich.edu
8513894Sgabeblack@google.com    std::vector<AuxVector<uint64_t>>  auxv;
865759Shsul@eecs.umich.edu
875759Shsul@eecs.umich.edu    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
8811321Ssteve.reinhardt@amd.com    if (elfObject)
895759Shsul@eecs.umich.edu    {
9011320Ssteve.reinhardt@amd.com        // modern glibc uses a bunch of auxiliary vectors to set up
915759Shsul@eecs.umich.edu        // TLS as well as do a bunch of other stuff
925759Shsul@eecs.umich.edu        // these vectors go on the bottom of the stack, below argc/argv/envp
935759Shsul@eecs.umich.edu        // pointers but above actual arg strings
945759Shsul@eecs.umich.edu        // I don't have all the ones glibc looks at here, but so far it doesn't
955759Shsul@eecs.umich.edu        // seem to be a problem.
965759Shsul@eecs.umich.edu        // check out _dl_aux_init() in glibc/elf/dl-support.c for details
975759Shsul@eecs.umich.edu        // --Lisa
9813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PAGESZ, AlphaISA::PageBytes);
9913894Sgabeblack@google.com        auxv.emplace_back(M5_AT_CLKTCK, 100);
10013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
10113894Sgabeblack@google.com        DPRINTF(Loader, "auxv at PHDR %08p\n",
10213894Sgabeblack@google.com                elfObject->programHeaderTable());
10313894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
10411389Sbrandon.potter@amd.com        // This is the base address of the ELF interpreter; it should be
10511389Sbrandon.potter@amd.com        // zero for static executables or contain the base address for
10611389Sbrandon.potter@amd.com        // dynamic executables.
10713894Sgabeblack@google.com        auxv.emplace_back(M5_AT_BASE, getBias());
10813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
10913894Sgabeblack@google.com        auxv.emplace_back(M5_AT_UID, uid());
11013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EUID, euid());
11113894Sgabeblack@google.com        auxv.emplace_back(M5_AT_GID, gid());
11213894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EGID, egid());
1135759Shsul@eecs.umich.edu
1145759Shsul@eecs.umich.edu    }
1155759Shsul@eecs.umich.edu
1165759Shsul@eecs.umich.edu    // Calculate how much space we need for arg & env & auxv arrays.
1175759Shsul@eecs.umich.edu    int argv_array_size = intSize * (argv.size() + 1);
1185759Shsul@eecs.umich.edu    int envp_array_size = intSize * (envp.size() + 1);
1195759Shsul@eecs.umich.edu    int auxv_array_size = intSize * 2 * (auxv.size() + 1);
1205759Shsul@eecs.umich.edu
1215759Shsul@eecs.umich.edu    int arg_data_size = 0;
1226227Snate@binkert.org    for (vector<string>::size_type i = 0; i < argv.size(); ++i) {
1235759Shsul@eecs.umich.edu        arg_data_size += argv[i].size() + 1;
1245759Shsul@eecs.umich.edu    }
1255759Shsul@eecs.umich.edu    int env_data_size = 0;
1266227Snate@binkert.org    for (vector<string>::size_type i = 0; i < envp.size(); ++i) {
1275759Shsul@eecs.umich.edu        env_data_size += envp[i].size() + 1;
1285759Shsul@eecs.umich.edu    }
1295759Shsul@eecs.umich.edu
1305759Shsul@eecs.umich.edu    int space_needed =
13111320Ssteve.reinhardt@amd.com        argv_array_size +
13211320Ssteve.reinhardt@amd.com        envp_array_size +
1335759Shsul@eecs.umich.edu        auxv_array_size +
13411320Ssteve.reinhardt@amd.com        arg_data_size +
1355759Shsul@eecs.umich.edu        env_data_size;
1365759Shsul@eecs.umich.edu
1375759Shsul@eecs.umich.edu    if (space_needed < 32*1024)
1385759Shsul@eecs.umich.edu        space_needed = 32*1024;
1395759Shsul@eecs.umich.edu
1405759Shsul@eecs.umich.edu    // set bottom of stack
14111905SBrandon.Potter@amd.com    memState->setStackMin(memState->getStackBase() - space_needed);
1425759Shsul@eecs.umich.edu    // align it
14311905SBrandon.Potter@amd.com    memState->setStackMin(roundDown(memState->getStackMin(), pageSize));
14411905SBrandon.Potter@amd.com    memState->setStackSize(memState->getStackBase() - memState->getStackMin());
1455759Shsul@eecs.umich.edu    // map memory
14611905SBrandon.Potter@amd.com    allocateMem(memState->getStackMin(), roundUp(memState->getStackSize(),
14711905SBrandon.Potter@amd.com                pageSize));
1485759Shsul@eecs.umich.edu
1495759Shsul@eecs.umich.edu    // map out initial stack contents
15011905SBrandon.Potter@amd.com    Addr argv_array_base = memState->getStackMin() + intSize; // room for argc
1515759Shsul@eecs.umich.edu    Addr envp_array_base = argv_array_base + argv_array_size;
1525759Shsul@eecs.umich.edu    Addr auxv_array_base = envp_array_base + envp_array_size;
1535759Shsul@eecs.umich.edu    Addr arg_data_base = auxv_array_base + auxv_array_size;
1545759Shsul@eecs.umich.edu    Addr env_data_base = arg_data_base + arg_data_size;
1555759Shsul@eecs.umich.edu
1565759Shsul@eecs.umich.edu    // write contents to stack
1575759Shsul@eecs.umich.edu    uint64_t argc = argv.size();
1585759Shsul@eecs.umich.edu    if (intSize == 8)
1595759Shsul@eecs.umich.edu        argc = htog((uint64_t)argc);
1605759Shsul@eecs.umich.edu    else if (intSize == 4)
1615759Shsul@eecs.umich.edu        argc = htog((uint32_t)argc);
1625759Shsul@eecs.umich.edu    else
1635759Shsul@eecs.umich.edu        panic("Unknown int size");
1645759Shsul@eecs.umich.edu
16514010Sgabeblack@google.com    initVirtMem.writeBlob(memState->getStackMin(), &argc, intSize);
1665759Shsul@eecs.umich.edu
1675759Shsul@eecs.umich.edu    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
1685759Shsul@eecs.umich.edu    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
1695759Shsul@eecs.umich.edu
1705759Shsul@eecs.umich.edu    //Copy the aux stuff
17113894Sgabeblack@google.com    Addr auxv_array_end = auxv_array_base;
17213894Sgabeblack@google.com    for (const auto &aux: auxv) {
17313894Sgabeblack@google.com        initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
17413894Sgabeblack@google.com        auxv_array_end += sizeof(aux);
1755759Shsul@eecs.umich.edu    }
1765759Shsul@eecs.umich.edu
1775759Shsul@eecs.umich.edu    ThreadContext *tc = system->getThreadContext(contextIds[0]);
1785759Shsul@eecs.umich.edu
1795958Sgblack@eecs.umich.edu    setSyscallArg(tc, 0, argc);
1805958Sgblack@eecs.umich.edu    setSyscallArg(tc, 1, argv_array_base);
18111905SBrandon.Potter@amd.com    tc->setIntReg(StackPointerReg, memState->getStackMin());
1825759Shsul@eecs.umich.edu
18311389Sbrandon.potter@amd.com    tc->pcState(getStartPC());
1845759Shsul@eecs.umich.edu}
1855759Shsul@eecs.umich.edu
1865759Shsul@eecs.umich.eduvoid
18711851Sbrandon.potter@amd.comAlphaProcess::setupASNReg()
1882474SN/A{
1896820SLisa.Hsu@amd.com    ThreadContext *tc = system->getThreadContext(contextIds[0]);
19011801Sbrandon.potter@amd.com    tc->setMiscRegNoEffect(IPR_DTB_ASN, _pid << 57);
1917532Ssteve.reinhardt@amd.com}
1926820SLisa.Hsu@amd.com
1935183Ssaidi@eecs.umich.edu
1947532Ssteve.reinhardt@amd.comvoid
19512186Sgabeblack@google.comAlphaProcess::unserialize(CheckpointIn &cp)
1967532Ssteve.reinhardt@amd.com{
19712186Sgabeblack@google.com    Process::unserialize(cp);
19811801Sbrandon.potter@amd.com    // need to set up ASN after unserialization since _pid value may
1997532Ssteve.reinhardt@amd.com    // come from checkpoint
2007532Ssteve.reinhardt@amd.com    setupASNReg();
2017532Ssteve.reinhardt@amd.com}
2027532Ssteve.reinhardt@amd.com
2037532Ssteve.reinhardt@amd.com
2047532Ssteve.reinhardt@amd.comvoid
20511851Sbrandon.potter@amd.comAlphaProcess::initState()
2067532Ssteve.reinhardt@amd.com{
2077532Ssteve.reinhardt@amd.com    // need to set up ASN before further initialization since init
2087532Ssteve.reinhardt@amd.com    // will involve writing to virtual memory addresses
2097532Ssteve.reinhardt@amd.com    setupASNReg();
2107532Ssteve.reinhardt@amd.com
21111851Sbrandon.potter@amd.com    Process::initState();
2125759Shsul@eecs.umich.edu
21310318Sandreas.hansson@arm.com    argsInit(MachineBytes, PageBytes);
2142474SN/A
2157532Ssteve.reinhardt@amd.com    ThreadContext *tc = system->getThreadContext(contextIds[0]);
2165713Shsul@eecs.umich.edu    tc->setIntReg(GlobalPointerReg, objFile->globalPointer());
2175713Shsul@eecs.umich.edu    //Operate in user mode
2187701Sgblack@eecs.umich.edu    tc->setMiscRegNoEffect(IPR_ICM, mode_user << 3);
2197701Sgblack@eecs.umich.edu    tc->setMiscRegNoEffect(IPR_DTB_CM, mode_user << 3);
2204997Sgblack@eecs.umich.edu    //No super page mapping
2215713Shsul@eecs.umich.edu    tc->setMiscRegNoEffect(IPR_MCSR, 0);
2222474SN/A}
2232474SN/A
22413614Sgabeblack@google.comRegVal
22511851Sbrandon.potter@amd.comAlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
2265958Sgblack@eecs.umich.edu{
2275958Sgblack@eecs.umich.edu    assert(i < 6);
2286701Sgblack@eecs.umich.edu    return tc->readIntReg(FirstArgumentReg + i++);
2295958Sgblack@eecs.umich.edu}
2305958Sgblack@eecs.umich.edu
2315958Sgblack@eecs.umich.eduvoid
23213614Sgabeblack@google.comAlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
2335958Sgblack@eecs.umich.edu{
2345958Sgblack@eecs.umich.edu    assert(i < 6);
2355958Sgblack@eecs.umich.edu    tc->setIntReg(FirstArgumentReg + i, val);
2365958Sgblack@eecs.umich.edu}
2375958Sgblack@eecs.umich.edu
2385958Sgblack@eecs.umich.eduvoid
23911851Sbrandon.potter@amd.comAlphaProcess::setSyscallReturn(ThreadContext *tc, SyscallReturn sysret)
2405958Sgblack@eecs.umich.edu{
2415958Sgblack@eecs.umich.edu    // check for error condition.  Alpha syscall convention is to
2425958Sgblack@eecs.umich.edu    // indicate success/failure in reg a3 (r19) and put the
2435958Sgblack@eecs.umich.edu    // return value itself in the standard return value reg (v0).
24410223Ssteve.reinhardt@amd.com    if (sysret.successful()) {
2455958Sgblack@eecs.umich.edu        // no error
2465958Sgblack@eecs.umich.edu        tc->setIntReg(SyscallSuccessReg, 0);
24710223Ssteve.reinhardt@amd.com        tc->setIntReg(ReturnValueReg, sysret.returnValue());
2485958Sgblack@eecs.umich.edu    } else {
2495958Sgblack@eecs.umich.edu        // got an error, return details
25013614Sgabeblack@google.com        tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
25110223Ssteve.reinhardt@amd.com        tc->setIntReg(ReturnValueReg, sysret.errnoValue());
2525958Sgblack@eecs.umich.edu    }
2535958Sgblack@eecs.umich.edu}
254