/gem5/src/systemc/core/ |
H A D | process.cc | 33 #include "systemc/core/port.hh" 429 Port *port = Port::fromPort(pb); local 430 port->addReset(new Reset(p, s, v));
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/gem5/configs/common/ |
H A D | FSConfig.py | 169 self.rom.port = self.membus.master 170 self.nvram.port = self.membus.master 171 self.hypervisor_desc.port = self.membus.master 172 self.partition_desc.port = self.membus.master 352 self.external_io.port = self.iobus.slave 358 self.iocache.port = self.iobus.master 440 def x86IOAddress(port): 442 return IO_address_space_base + port
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/gem5/src/dev/ |
H A D | dma_device.hh | 113 /** The device that owns this port. */ 116 /** The system that device/port are in. This is used to select which mode 130 /** Number of outstanding packets the dma port has. */ 133 /** If the port is currently waiting for a retry before it can 311 * DmaReadFifo *dma = new DmaReadFifo(port, 1024, 64, 8, 332 DmaReadFifo(DmaPort &port, size_t size, 473 DmaPort &port;
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/gem5/configs/example/ |
H A D | se.py | 270 system.cpu[i].itb.walker.port = ruby_port.slave 271 system.cpu[i].dtb.walker.port = ruby_port.slave
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H A D | fs.py | 159 # Connect the ruby io port to the PIO bus, 160 # assuming that there is just one such port. 175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 294 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
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H A D | ruby_mem_test.py | 150 cpu.port = system.ruby._cpu_ports[i].slave
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/gem5/src/arch/x86/ |
H A D | pagetable_walker.cc | 158 if (port.sendTimingReq(pkt)) { 173 if (if_name == "port") 174 return port; 241 walker->port.sendAtomic(read); 248 walker->port.sendAtomic(write); 265 walker->port.sendFunctional(read); 662 //If we're already waiting for the port to become available, just return.
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/gem5/src/python/m5/ |
H A D | params.py | 1133 # the form "a.b.c.d:p", or an ip and port as positional or keyword arguments. 1154 handle_kwarg(self, kwargs, 'port') 1158 if not 'ip' in kwargs and not 'port' in kwargs: 1161 handle_kwarg(self, kwargs, 'port', args[0]) 1164 self.port = args[0].port 1166 (self.ip, self.port) = convert.toIpWithPort(args[0]) 1170 self.port = args[1] 1184 return "%s:%d" % (super(IpWithPort, self).__str__(), self.port) 1188 return self.ip == other.ip and self.port [all...] |
/gem5/ext/sst/ |
H A D | ExtMaster.cc | 61 Port(n, p), out(o), port(p), simPhase(CONSTRUCTION),
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/gem5/ext/googletest/googlemock/ |
H A D | Makefile.am | 45 include/gmock/internal/gmock-port.h \ 48 include/gmock/internal/custom/gmock-port.h
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/gem5/ext/googletest/googletest/src/ |
H A D | gtest-internal-inl.h | 59 #include "gtest/internal/gtest-port.h" 1034 // Streams test results to the given port on the given host machine. 1057 SocketWriter(const string& host, const string& port) argument 1058 : sockfd_(-1), host_name_(host), port_num_(port) { 1103 StreamingListener(const string& host, const string& port) argument 1104 : socket_writer_(new SocketWriter(host, port)) { Start(); }
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/gem5/configs/dram/ |
H A D | sweep.py | 95 # which amounts to 42.7 GByte/s per layer and thus per port 171 system.tgen.port = system.monitor.slave 174 # connect the system port even if it is not used in this example
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H A D | low_power_sweep.py | 91 # which amounts to 42.7 GByte/s per layer and thus per port. 229 system.tgen.port = system.monitor.slave 232 # connect the system port even if it is not used in this example
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H A D | lat_mem_rd.py | 103 # amounts to 42.7 GByte/s per layer and thus per port 261 system.tgen.port = system.monitor.slave 296 # connect the system port even if it is not used in this example
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/gem5/tests/gem5/cpu_tests/ |
H A D | run.py | 51 """Connect this cache's port to a CPU-side port 62 """Connect this cache's port to a CPU icache port""" 72 """Connect this cache's port to a CPU dcache port""" 160 system.mem_ctrl.port = system.membus.master
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/gem5/src/cpu/testers/traffic_gen/ |
H A D | base.hh | 92 * Receive a retry from the neighbouring port and attempt to 129 /** Master port specialisation for the traffic generator */ 163 /** The instance of master port used by the traffic generator. */ 164 TrafficGenPort port; member in class:BaseTrafficGen
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/gem5/tests/configs/ |
H A D | base_config.py | 233 system.physmem.port = system.membus.master 273 # Connect the ruby io port to the PIO bus, 274 # assuming that there is just one such port. 292 system.physmem[i].port = system.llc[i].mem_side
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/gem5/src/cpu/ |
H A D | BaseCPU.py | 217 _cached_ports += ["itb.walker.port", "dtb.walker.port"] 255 self.itb.walker.port = iwc.cpu_side 256 self.dtb.walker.port = dwc.cpu_side 260 self._cached_ports += ["itb.walker.port", "dtb.walker.port"] 265 self._cached_ports += ["checker.itb.walker.port", \ 266 "checker.dtb.walker.port"]
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | AbstractController.cc | 118 DPRINTF(RubyQueue, "stalling %s port %d addr %#x\n", buf, m_cur_in_port, 206 AbstractController::blockOnQueue(Addr addr, MessageBuffer* port) argument 209 m_block_map[addr] = port;
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/gem5/ext/systemc/src/sysc/communication/ |
H A D | sc_signal_ports.h | 22 sc_signal_ports.h -- The sc_signal<T> port classes. 73 // The sc_signal<T> input port class. 172 // bind to parent in port 181 // bind to parent inout port 259 // implement virtual base_type port-binding function 495 // bind to parent in port 504 // bind to parent inout port 626 // implement virtual base_type port-binding function 762 // bind to parent in port 771 // bind to parent inout port 1793 sc_trace(sc_trace_file* tf, const sc_in<T>& port, const std::string& name) argument 1810 sc_trace( sc_trace_file* tf, const sc_inout<T>& port, const std::string& name ) argument [all...] |
/gem5/src/dev/virtio/ |
H A D | fs9p.cc | 519 if ((ret = getaddrinfo(p.server.c_str(), p.port.c_str(), 540 panic("Failed to connect to 9p server (%s:%s)", p.server, p.port);
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/gem5/ext/systemc/src/sysc/qt/md/ |
H A D | hppa_b.s | 12 ; This file (pa-risc_b.s) is part of the port of QuickThreads for
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/gem5/configs/splash2/ |
H A D | run.py | 210 system.physmem.port = system.membus.master
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/gem5/src/base/ |
H A D | remote_gdb.hh | 134 int port() const;
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/gem5/src/dev/net/ |
H A D | Ethernet.py | 81 server_port = Param.UInt32('2200', "Message server port") 100 output_buffer_size = Param.MemorySize('1MB', "size of output port buffers") 124 port = Param.UInt16(3500, "Port helper should send packets to") variable in class:EtherTapStub
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