1# Copyright (c) 2010-2012, 2015-2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
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26# this software without specific prior written permission.
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from __future__ import print_function
43from __future__ import absolute_import
44
45from m5.objects import *
46from m5.util import *
47from .Benchmarks import *
48from . import PlatformConfig
49
50# Populate to reflect supported os types per target ISA
51os_types = { 'alpha' : [ 'linux' ],
52             'mips'  : [ 'linux' ],
53             'sparc' : [ 'linux' ],
54             'x86'   : [ 'linux' ],
55             'arm'   : [ 'linux',
56                         'android-gingerbread',
57                         'android-ics',
58                         'android-jellybean',
59                         'android-kitkat',
60                         'android-nougat', ],
61           }
62
63class CowIdeDisk(IdeDisk):
64    image = CowDiskImage(child=RawDiskImage(read_only=True),
65                         read_only=False)
66
67    def childImage(self, ci):
68        self.image.child.image_file = ci
69
70class MemBus(SystemXBar):
71    badaddr_responder = BadAddr()
72    default = Self.badaddr_responder.pio
73
74def fillInCmdline(mdesc, template, **kwargs):
75    kwargs.setdefault('disk', mdesc.disk())
76    kwargs.setdefault('rootdev', mdesc.rootdev())
77    kwargs.setdefault('mem', mdesc.mem())
78    kwargs.setdefault('script', mdesc.script())
79    return template % kwargs
80
81def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
82
83    class BaseTsunami(Tsunami):
84        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
85        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
86                            pci_func=0, pci_dev=0, pci_bus=0)
87
88    self = LinuxAlphaSystem()
89    if not mdesc:
90        # generic system
91        mdesc = SysConfig()
92    self.readfile = mdesc.script()
93
94    self.tsunami = BaseTsunami()
95
96    # Create the io bus to connect all device ports
97    self.iobus = IOXBar()
98    self.tsunami.attachIO(self.iobus)
99
100    self.tsunami.ide.pio = self.iobus.master
101
102    self.tsunami.ethernet.pio = self.iobus.master
103
104    if ruby:
105        # Store the dma devices for later connection to dma ruby ports.
106        # Append an underscore to dma_ports to avoid the SimObjectVector check.
107        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
108    else:
109        self.membus = MemBus()
110
111        # By default the bridge responds to all addresses above the I/O
112        # base address (including the PCI config space)
113        IO_address_space_base = 0x80000000000
114        self.bridge = Bridge(delay='50ns',
115                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
116        self.bridge.master = self.iobus.slave
117        self.bridge.slave = self.membus.master
118
119        self.tsunami.ide.dma = self.iobus.slave
120        self.tsunami.ethernet.dma = self.iobus.slave
121
122        self.system_port = self.membus.slave
123
124    self.mem_ranges = [AddrRange(mdesc.mem())]
125    self.disk0 = CowIdeDisk(driveID='master')
126    self.disk2 = CowIdeDisk(driveID='master')
127    self.disk0.childImage(mdesc.disk())
128    self.disk2.childImage(disk('linux-bigswap2.img'))
129    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
130                                               read_only = True))
131    self.intrctrl = IntrControl()
132    self.mem_mode = mem_mode
133    self.terminal = Terminal()
134    self.pal = binary('ts_osfpal')
135    self.console = binary('console')
136    if not cmdline:
137        cmdline = 'root=/dev/hda1 console=ttyS0'
138    self.boot_osflags = fillInCmdline(mdesc, cmdline)
139
140    return self
141
142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
143    # Constants from iob.cc and uart8250.cc
144    iob_man_addr = 0x9800000000
145    uart_pio_size = 8
146
147    class CowMmDisk(MmDisk):
148        image = CowDiskImage(child=RawDiskImage(read_only=True),
149                             read_only=False)
150
151        def childImage(self, ci):
152            self.image.child.image_file = ci
153
154    self = SparcSystem()
155    if not mdesc:
156        # generic system
157        mdesc = SysConfig()
158    self.readfile = mdesc.script()
159    self.iobus = IOXBar()
160    self.membus = MemBus()
161    self.bridge = Bridge(delay='50ns')
162    self.t1000 = T1000()
163    self.t1000.attachOnChipIO(self.membus)
164    self.t1000.attachIO(self.iobus)
165    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
166                       AddrRange(Addr('2GB'), size ='256MB')]
167    self.bridge.master = self.iobus.slave
168    self.bridge.slave = self.membus.master
169    self.rom.port = self.membus.master
170    self.nvram.port = self.membus.master
171    self.hypervisor_desc.port = self.membus.master
172    self.partition_desc.port = self.membus.master
173    self.intrctrl = IntrControl()
174    self.disk0 = CowMmDisk()
175    self.disk0.childImage(mdesc.disk())
176    self.disk0.pio = self.iobus.master
177
178    # The puart0 and hvuart are placed on the IO bus, so create ranges
179    # for them. The remaining IO range is rather fragmented, so poke
180    # holes for the iob and partition descriptors etc.
181    self.bridge.ranges = \
182        [
183        AddrRange(self.t1000.puart0.pio_addr,
184                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
185        AddrRange(self.disk0.pio_addr,
186                  self.t1000.fake_jbi.pio_addr +
187                  self.t1000.fake_jbi.pio_size - 1),
188        AddrRange(self.t1000.fake_clk.pio_addr,
189                  iob_man_addr - 1),
190        AddrRange(self.t1000.fake_l2_1.pio_addr,
191                  self.t1000.fake_ssi.pio_addr +
192                  self.t1000.fake_ssi.pio_size - 1),
193        AddrRange(self.t1000.hvuart.pio_addr,
194                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
195        ]
196    self.reset_bin = binary('reset_new.bin')
197    self.hypervisor_bin = binary('q_new.bin')
198    self.openboot_bin = binary('openboot_new.bin')
199    self.nvram_bin = binary('nvram1')
200    self.hypervisor_desc_bin = binary('1up-hv.bin')
201    self.partition_desc_bin = binary('1up-md.bin')
202
203    self.system_port = self.membus.slave
204
205    return self
206
207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
208                  dtb_filename=None, bare_metal=False, cmdline=None,
209                  external_memory="", ruby=False, security=False):
210    assert machine_type
211
212    pci_devices = []
213
214    if bare_metal:
215        self = ArmSystem()
216    else:
217        self = LinuxArmSystem()
218
219    if not mdesc:
220        # generic system
221        mdesc = SysConfig()
222
223    self.readfile = mdesc.script()
224    self.iobus = IOXBar()
225    if not ruby:
226        self.bridge = Bridge(delay='50ns')
227        self.bridge.master = self.iobus.slave
228        self.membus = MemBus()
229        self.membus.badaddr_responder.warn_access = "warn"
230        self.bridge.slave = self.membus.master
231
232    self.mem_mode = mem_mode
233
234    platform_class = PlatformConfig.get(machine_type)
235    # Resolve the real platform name, the original machine_type
236    # variable might have been an alias.
237    machine_type = platform_class.__name__
238    self.realview = platform_class()
239
240    if isinstance(self.realview, VExpress_EMM64):
241        if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
242            print("Selected 64-bit ARM architecture, updating default "
243                  "disk image...")
244            mdesc.diskname = 'linaro-minimal-aarch64.img'
245
246
247    # Attach any PCI devices this platform supports
248    self.realview.attachPciDevices()
249
250    self.cf0 = CowIdeDisk(driveID='master')
251    self.cf0.childImage(mdesc.disk())
252    # Old platforms have a built-in IDE or CF controller. Default to
253    # the IDE controller if both exist. New platforms expect the
254    # storage controller to be added from the config script.
255    if hasattr(self.realview, "ide"):
256        self.realview.ide.disks = [self.cf0]
257    elif hasattr(self.realview, "cf_ctrl"):
258        self.realview.cf_ctrl.disks = [self.cf0]
259    else:
260        self.pci_ide = IdeController(disks=[self.cf0])
261        pci_devices.append(self.pci_ide)
262
263    self.mem_ranges = []
264    size_remain = long(Addr(mdesc.mem()))
265    for region in self.realview._mem_regions:
266        if size_remain > long(region.size()):
267            self.mem_ranges.append(region)
268            size_remain = size_remain - long(region.size())
269        else:
270            self.mem_ranges.append(AddrRange(region.start, size=size_remain))
271            size_remain = 0
272            break
273        warn("Memory size specified spans more than one region. Creating" \
274             " another memory controller for that range.")
275
276    if size_remain > 0:
277        fatal("The currently selected ARM platforms doesn't support" \
278              " the amount of DRAM you've selected. Please try" \
279              " another platform")
280
281    self.have_security = security
282
283    if bare_metal:
284        # EOT character on UART will end the simulation
285        self.realview.uart[0].end_on_eot = True
286    else:
287        if dtb_filename:
288            self.dtb_filename = binary(dtb_filename)
289
290        self.machine_type = machine_type if machine_type in ArmMachineType.map \
291                            else "DTOnly"
292
293        # Ensure that writes to the UART actually go out early in the boot
294        if not cmdline:
295            cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
296                      'lpj=19988480 norandmaps rw loglevel=8 ' + \
297                      'mem=%(mem)s root=%(rootdev)s'
298
299        # When using external memory, gem5 writes the boot loader to nvmem
300        # and then SST will read from it, but SST can only get to nvmem from
301        # iobus, as gem5's membus is only used for initialization and
302        # SST doesn't use it.  Attaching nvmem to iobus solves this issue.
303        # During initialization, system_port -> membus -> iobus -> nvmem.
304        if external_memory:
305            self.realview.setupBootLoader(self.iobus,  self, binary)
306        elif ruby:
307            self.realview.setupBootLoader(None, self, binary)
308        else:
309            self.realview.setupBootLoader(self.membus, self, binary)
310
311        if hasattr(self.realview.gic, 'cpu_addr'):
312            self.gic_cpu_addr = self.realview.gic.cpu_addr
313
314        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
315
316        # This check is for users who have previously put 'android' in
317        # the disk image filename to tell the config scripts to
318        # prepare the kernel with android-specific boot options. That
319        # behavior has been replaced with a more explicit option per
320        # the error message below. The disk can have any name now and
321        # doesn't need to include 'android' substring.
322        if (os.path.split(mdesc.disk())[-1]).lower().count('android'):
323            if 'android' not in mdesc.os_type():
324                fatal("It looks like you are trying to boot an Android " \
325                      "platform.  To boot Android, you must specify " \
326                      "--os-type with an appropriate Android release on " \
327                      "the command line.")
328
329        # android-specific tweaks
330        if 'android' in mdesc.os_type():
331            # generic tweaks
332            cmdline += " init=/init"
333
334            # release-specific tweaks
335            if 'kitkat' in mdesc.os_type():
336                cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
337                           "android.bootanim=0 "
338            elif 'nougat' in mdesc.os_type():
339                cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
340                           "android.bootanim=0 " + \
341                           "vmalloc=640MB " + \
342                           "android.early.fstab=/fstab.gem5 " + \
343                           "androidboot.selinux=permissive " + \
344                           "video=Virtual-1:1920x1080-16"
345
346        self.boot_osflags = fillInCmdline(mdesc, cmdline)
347
348    if external_memory:
349        # I/O traffic enters iobus
350        self.external_io = ExternalMaster(port_data="external_io",
351                                          port_type=external_memory)
352        self.external_io.port = self.iobus.slave
353
354        # Ensure iocache only receives traffic destined for (actual) memory.
355        self.iocache = ExternalSlave(port_data="iocache",
356                                     port_type=external_memory,
357                                     addr_ranges=self.mem_ranges)
358        self.iocache.port = self.iobus.master
359
360        # Let system_port get to nvmem and nothing else.
361        self.bridge.ranges = [self.realview.nvmem.range]
362
363        self.realview.attachOnChipIO(self.iobus)
364        # Attach off-chip devices
365        self.realview.attachIO(self.iobus)
366    elif ruby:
367        self._dma_ports = [ ]
368        self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports)
369        self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
370    else:
371        self.realview.attachOnChipIO(self.membus, self.bridge)
372        # Attach off-chip devices
373        self.realview.attachIO(self.iobus)
374
375    for dev_id, dev in enumerate(pci_devices):
376        dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0)
377        self.realview.attachPciDevice(
378            dev, self.iobus,
379            dma_ports=self._dma_ports if ruby else None)
380
381    self.intrctrl = IntrControl()
382    self.terminal = Terminal()
383    self.vncserver = VncServer()
384
385    if not ruby:
386        self.system_port = self.membus.slave
387
388    if ruby:
389        if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
390            fatal("The MI_example protocol cannot implement Load/Store "
391                  "Exclusive operations. Multicore ARM systems configured "
392                  "with the MI_example protocol will not work properly.")
393        warn("You are trying to use Ruby on ARM, which is not working "
394             "properly yet.")
395
396    return self
397
398
399def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
400    class BaseMalta(Malta):
401        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
402        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
403                            pci_func=0, pci_dev=0, pci_bus=0)
404
405    self = LinuxMipsSystem()
406    if not mdesc:
407        # generic system
408        mdesc = SysConfig()
409    self.readfile = mdesc.script()
410    self.iobus = IOXBar()
411    self.membus = MemBus()
412    self.bridge = Bridge(delay='50ns')
413    self.mem_ranges = [AddrRange('1GB')]
414    self.bridge.master = self.iobus.slave
415    self.bridge.slave = self.membus.master
416    self.disk0 = CowIdeDisk(driveID='master')
417    self.disk2 = CowIdeDisk(driveID='master')
418    self.disk0.childImage(mdesc.disk())
419    self.disk2.childImage(disk('linux-bigswap2.img'))
420    self.malta = BaseMalta()
421    self.malta.attachIO(self.iobus)
422    self.malta.ide.pio = self.iobus.master
423    self.malta.ide.dma = self.iobus.slave
424    self.malta.ethernet.pio = self.iobus.master
425    self.malta.ethernet.dma = self.iobus.slave
426    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
427                                               read_only = True))
428    self.intrctrl = IntrControl()
429    self.mem_mode = mem_mode
430    self.terminal = Terminal()
431    self.console = binary('mips/console')
432    if not cmdline:
433        cmdline = 'root=/dev/hda1 console=ttyS0'
434    self.boot_osflags = fillInCmdline(mdesc, cmdline)
435
436    self.system_port = self.membus.slave
437
438    return self
439
440def x86IOAddress(port):
441    IO_address_space_base = 0x8000000000000000
442    return IO_address_space_base + port
443
444def connectX86ClassicSystem(x86_sys, numCPUs):
445    # Constants similar to x86_traits.hh
446    IO_address_space_base = 0x8000000000000000
447    pci_config_address_space_base = 0xc000000000000000
448    interrupts_address_space_base = 0xa000000000000000
449    APIC_range_size = 1 << 12;
450
451    x86_sys.membus = MemBus()
452
453    # North Bridge
454    x86_sys.iobus = IOXBar()
455    x86_sys.bridge = Bridge(delay='50ns')
456    x86_sys.bridge.master = x86_sys.iobus.slave
457    x86_sys.bridge.slave = x86_sys.membus.master
458    # Allow the bridge to pass through:
459    #  1) kernel configured PCI device memory map address: address range
460    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
461    #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
462    #  3) everything in the IO address range up to the local APIC, and
463    #  4) then the entire PCI address space and beyond.
464    x86_sys.bridge.ranges = \
465        [
466        AddrRange(0xC0000000, 0xFFFF0000),
467        AddrRange(IO_address_space_base,
468                  interrupts_address_space_base - 1),
469        AddrRange(pci_config_address_space_base,
470                  Addr.max)
471        ]
472
473    # Create a bridge from the IO bus to the memory bus to allow access to
474    # the local APIC (two pages)
475    x86_sys.apicbridge = Bridge(delay='50ns')
476    x86_sys.apicbridge.slave = x86_sys.iobus.master
477    x86_sys.apicbridge.master = x86_sys.membus.slave
478    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
479                                           interrupts_address_space_base +
480                                           numCPUs * APIC_range_size
481                                           - 1)]
482
483    # connect the io bus
484    x86_sys.pc.attachIO(x86_sys.iobus)
485
486    x86_sys.system_port = x86_sys.membus.slave
487
488def connectX86RubySystem(x86_sys):
489    # North Bridge
490    x86_sys.iobus = IOXBar()
491
492    # add the ide to the list of dma devices that later need to attach to
493    # dma controllers
494    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
495    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
496
497
498def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
499    if self == None:
500        self = X86System()
501
502    if not mdesc:
503        # generic system
504        mdesc = SysConfig()
505    self.readfile = mdesc.script()
506
507    self.mem_mode = mem_mode
508
509    # Physical memory
510    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
511    # for various devices.  Hence, if the physical memory size is greater than
512    # 3GB, we need to split it into two parts.
513    excess_mem_size = \
514        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
515    if excess_mem_size <= 0:
516        self.mem_ranges = [AddrRange(mdesc.mem())]
517    else:
518        warn("Physical memory size specified is %s which is greater than " \
519             "3GB.  Twice the number of memory controllers would be " \
520             "created."  % (mdesc.mem()))
521
522        self.mem_ranges = [AddrRange('3GB'),
523            AddrRange(Addr('4GB'), size = excess_mem_size)]
524
525    # Platform
526    self.pc = Pc()
527
528    # Create and connect the busses required by each memory system
529    if Ruby:
530        connectX86RubySystem(self)
531    else:
532        connectX86ClassicSystem(self, numCPUs)
533
534    self.intrctrl = IntrControl()
535
536    # Disks
537    disk0 = CowIdeDisk(driveID='master')
538    disk2 = CowIdeDisk(driveID='master')
539    disk0.childImage(mdesc.disk())
540    disk2.childImage(disk('linux-bigswap2.img'))
541    self.pc.south_bridge.ide.disks = [disk0, disk2]
542
543    # Add in a Bios information structure.
544    structures = [X86SMBiosBiosInformation()]
545    self.smbios_table.structures = structures
546
547    # Set up the Intel MP table
548    base_entries = []
549    ext_entries = []
550    for i in range(numCPUs):
551        bp = X86IntelMPProcessor(
552                local_apic_id = i,
553                local_apic_version = 0x14,
554                enable = True,
555                bootstrap = (i == 0))
556        base_entries.append(bp)
557    io_apic = X86IntelMPIOAPIC(
558            id = numCPUs,
559            version = 0x11,
560            enable = True,
561            address = 0xfec00000)
562    self.pc.south_bridge.io_apic.apic_id = io_apic.id
563    base_entries.append(io_apic)
564    # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
565    # but linux kernel cannot config PCI device if it was not connected to PCI bus,
566    # so we fix PCI bus id to 0, and ISA bus id to 1.
567    pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
568    base_entries.append(pci_bus)
569    isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
570    base_entries.append(isa_bus)
571    connect_busses = X86IntelMPBusHierarchy(bus_id=1,
572            subtractive_decode=True, parent_bus=0)
573    ext_entries.append(connect_busses)
574    pci_dev4_inta = X86IntelMPIOIntAssignment(
575            interrupt_type = 'INT',
576            polarity = 'ConformPolarity',
577            trigger = 'ConformTrigger',
578            source_bus_id = 0,
579            source_bus_irq = 0 + (4 << 2),
580            dest_io_apic_id = io_apic.id,
581            dest_io_apic_intin = 16)
582    base_entries.append(pci_dev4_inta)
583    def assignISAInt(irq, apicPin):
584        assign_8259_to_apic = X86IntelMPIOIntAssignment(
585                interrupt_type = 'ExtInt',
586                polarity = 'ConformPolarity',
587                trigger = 'ConformTrigger',
588                source_bus_id = 1,
589                source_bus_irq = irq,
590                dest_io_apic_id = io_apic.id,
591                dest_io_apic_intin = 0)
592        base_entries.append(assign_8259_to_apic)
593        assign_to_apic = X86IntelMPIOIntAssignment(
594                interrupt_type = 'INT',
595                polarity = 'ConformPolarity',
596                trigger = 'ConformTrigger',
597                source_bus_id = 1,
598                source_bus_irq = irq,
599                dest_io_apic_id = io_apic.id,
600                dest_io_apic_intin = apicPin)
601        base_entries.append(assign_to_apic)
602    assignISAInt(0, 2)
603    assignISAInt(1, 1)
604    for i in range(3, 15):
605        assignISAInt(i, i)
606    self.intel_mp_table.base_entries = base_entries
607    self.intel_mp_table.ext_entries = ext_entries
608
609def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
610                       cmdline=None):
611    self = LinuxX86System()
612
613    # Build up the x86 system and then specialize it for Linux
614    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
615
616    # We assume below that there's at least 1MB of memory. We'll require 2
617    # just to avoid corner cases.
618    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
619    assert(phys_mem_size >= 0x200000)
620    assert(len(self.mem_ranges) <= 2)
621
622    entries = \
623       [
624        # Mark the first megabyte of memory as reserved
625        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
626        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
627        # Mark the rest of physical memory as available
628        X86E820Entry(addr = 0x100000,
629                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
630                range_type = 1),
631        ]
632
633    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
634    # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
635    # specific range can pass though bridge to iobus.
636    if len(self.mem_ranges) == 1:
637        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
638            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
639            range_type=2))
640
641    # Reserve the last 16kB of the 32-bit address space for the m5op interface
642    entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
643
644    # In case the physical memory is greater than 3GB, we split it into two
645    # parts and add a separate e820 entry for the second part.  This entry
646    # starts at 0x100000000,  which is the first address after the space
647    # reserved for devices.
648    if len(self.mem_ranges) == 2:
649        entries.append(X86E820Entry(addr = 0x100000000,
650            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
651
652    self.e820_table.entries = entries
653
654    # Command line
655    if not cmdline:
656        cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
657    self.boot_osflags = fillInCmdline(mdesc, cmdline)
658    return self
659
660
661def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
662    self = Root(full_system = full_system)
663    self.testsys = testSystem
664    self.drivesys = driveSystem
665    self.etherlink = EtherLink()
666
667    if hasattr(testSystem, 'realview'):
668        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
669        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
670    elif hasattr(testSystem, 'tsunami'):
671        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
672        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
673    else:
674        fatal("Don't know how to connect these system together")
675
676    if dumpfile:
677        self.etherdump = EtherDump(file=dumpfile)
678        self.etherlink.dump = Parent.etherdump
679
680    return self
681
682
683def makeDistRoot(testSystem,
684                 rank,
685                 size,
686                 server_name,
687                 server_port,
688                 sync_repeat,
689                 sync_start,
690                 linkspeed,
691                 linkdelay,
692                 dumpfile):
693    self = Root(full_system = True)
694    self.testsys = testSystem
695
696    self.etherlink = DistEtherLink(speed = linkspeed,
697                                   delay = linkdelay,
698                                   dist_rank = rank,
699                                   dist_size = size,
700                                   server_name = server_name,
701                                   server_port = server_port,
702                                   sync_start = sync_start,
703                                   sync_repeat = sync_repeat)
704
705    if hasattr(testSystem, 'realview'):
706        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
707    elif hasattr(testSystem, 'tsunami'):
708        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
709    else:
710        fatal("Don't know how to connect DistEtherLink to this system")
711
712    if dumpfile:
713        self.etherdump = EtherDump(file=dumpfile)
714        self.etherlink.dump = Parent.etherdump
715
716    return self
717