Searched refs:cpu (Results 76 - 100 of 194) sorted by relevance

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/gem5/src/cpu/simple/
H A Dtiming.hh46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
48 #include "cpu/translation.hh"
112 TimingSimpleCPU *cpu; member in class:TimingSimpleCPU::FetchTranslation
116 : cpu(_cpu)
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
130 cpu->sendFetch(fault, req, tc);
165 : MasterPort(_name, _cpu), cpu(_cpu),
171 TimingSimpleCPU* cpu; member in class:TimingSimpleCPU::TimingCPUPort
176 TimingSimpleCPU *cpu; member in struct:TimingSimpleCPU::TimingCPUPort::TickEvent
331 TimingSimpleCPU *cpu; member in struct:TimingSimpleCPU::IprEvent
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H A Dtiming.cc44 #include "cpu/simple/timing.hh"
50 #include "cpu/exetrace.hh"
76 cpu->schedule(this, t);
744 // If the cpu has been suspended (i.e., _status == Idle), another
745 // cpu will wake this cpu up later.
847 cpu->completeIfetch(pkt);
858 tickEvent.schedule(pkt, cpu->clockEdge());
868 assert(cpu->ifetch_pkt != NULL);
869 assert(cpu
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H A Dexec_context.hh51 #include "cpu/base.hh"
52 #include "cpu/exec_context.hh"
53 #include "cpu/reg_class.hh"
54 #include "cpu/simple/base.hh"
55 #include "cpu/static_inst_fwd.hh"
56 #include "cpu/translation.hh"
67 BaseSimpleCPU *cpu; member in class:SimpleExecContext
172 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
443 return cpu->readMem(addr, data, size, flags, byteEnable);
452 return cpu
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H A Datomic.hh46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
143 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
145 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
152 BaseSimpleCPU *cpu; member in class:AtomicSimpleCPU::AtomicCPUDPort
182 /** Perform snoop for other cpu-local thread contexts. */
/gem5/tests/
H A Drun.py228 def initCPU(cpu):
232 cpu.createThreads()
238 if not hasattr(sys, "cpu"):
242 if isinstance(sys.cpu, list):
243 [ initCPU(cpu) for cpu in sys.cpu ]
245 initCPU(sys.cpu)
/gem5/src/cpu/o3/
H A Ddyn_inst_impl.hh47 #include "cpu/o3/dyn_inst.hh"
55 InstSeqNum seq_num, O3CPU *cpu)
56 : BaseDynInst<Impl>(staticInst, macroop, pc, predPC, seq_num, cpu)
174 if (this->cpu->checker) {
191 this->cpu->trap(fault, this->threadNumber, this->staticInst);
204 TheISA::PCState curPC = this->cpu->pcState(this->threadNumber);
205 this->cpu->syscall(callnum, this->threadNumber, fault);
206 TheISA::PCState newPC = this->cpu->pcState(this->threadNumber);
52 BaseO3DynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop, TheISA::PCState pc, TheISA::PCState predPC, InstSeqNum seq_num, O3CPU *cpu) argument
H A Dcommit_impl.hh56 #include "cpu/checker/cpu.hh"
57 #include "cpu/o3/commit.hh"
58 #include "cpu/o3/thread_state.hh"
59 #include "cpu/base.hh"
60 #include "cpu/exetrace.hh"
61 #include "cpu/timebuf.hh"
86 cpu(_cpu),
102 "\tincrease MaxWidth in src/cpu/o3/impl.hh\n",
136 return cpu
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H A Dfetch_impl.hh61 #include "cpu/base.hh"
62 //#include "cpu/checker/cpu.hh"
63 #include "cpu/o3/cpu.hh"
64 #include "cpu/o3/fetch.hh"
65 #include "cpu/exetrace.hh"
78 #include "cpu/o3/isa_specific.hh"
85 cpu(_cpu),
95 cacheBlkSize(cpu
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/gem5/tests/configs/
H A Dswitcheroo.py57 for (cpuno, cpu) in enumerate(cpus):
58 if not cpu.switched_out:
101 switcher = Sequential(root.system.cpu)
H A Dmemtest-ruby.py75 system = System(cpu = cpus)
87 for cpu in cpus:
88 cpu.clk_domain = system.cpu_clk_domain
102 # Tie the cpu port to the ruby cpu ports and
H A Darm_generic.py61 def create_caches_private(self, cpu):
65 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
108 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.{}cpu.dtb" \
133 def create_caches_private(self, cpu):
135 cpu.addTwoLevelCacheHierarchy(O3_ARM_v7a_ICache(),
H A Dgpu-ruby.py78 root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
126 parser.add_option("--cpu-voltage", action="store", type="string",
252 cpu = TimingSimpleCPU(cpu_id=0) variable
256 host_cpu = cpu
260 cpu_list = [cpu] + [shader] + [dispatcher]
262 system = System(cpu = cpu_list,
273 system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
290 cpu.createInterruptController()
293 # Tie the cpu cache ports to the ruby cpu port
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/gem5/src/arch/mips/
H A Disa.hh40 #include "cpu/reg_class.hh"
120 void processCP0Event(BaseCPU *cpu, CP0EventType);
123 void scheduleCP0Update(BaseCPU *cpu, Cycles delay = Cycles(0));
127 void updateCPU(BaseCPU *cpu);
/gem5/src/arch/alpha/
H A DAlphaSystem.py49 boot_cpu_frequency = Param.Frequency(Self.cpu[0].clk_domain.clock[0]
/gem5/src/dev/arm/
H A Dgeneric_timer.hh226 void setMiscReg(int misc_reg, unsigned cpu, RegVal val);
227 RegVal readMiscReg(int misc_reg, unsigned cpu);
231 CoreTimers(GenericTimer &parent, ArmSystem &system, unsigned cpu, argument
238 physS(csprintf("%s.phys_s_timer%d", parent.name(), cpu),
243 physNS(csprintf("%s.arch_timer%d", parent.name(), cpu),
246 virt(csprintf("%s.virt_timer%d", parent.name(), cpu),
249 hyp(csprintf("%s.hyp_timer%d", parent.name(), cpu),
287 : parent(_parent), cpu(_cpu) {}
294 unsigned cpu; member in class:GenericTimerISA
H A Dgic_v3.cc45 #include "cpu/intr_control.hh"
189 Gicv3::sendPPInt(uint32_t int_id, uint32_t cpu) argument
191 panic_if(cpu >= redistributors.size(), "Invalid cpuID sending PPI!");
195 int_id, cpu);
196 redistributors[cpu]->sendPPInt(int_id);
200 Gicv3::clearPPInt(uint32_t num, uint32_t cpu) argument
205 Gicv3::postInt(uint32_t cpu, ArmISA::InterruptTypes int_type) argument
207 platform->intrctrl->post(cpu, int_type, 0);
211 Gicv3::deassertInt(uint32_t cpu, ArmISA::InterruptTypes int_type) argument
213 platform->intrctrl->clear(cpu, int_typ
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/gem5/configs/common/
H A DCacheConfig.py171 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
177 system.cpu[i].dcache = dcache_real
178 system.cpu[i].dcache_mon = dcache_mon
187 system.cpu[i].addPrivateSplitL1Caches(
188 ExternalCache("cpu%d.icache" % i),
189 ExternalCache("cpu%d.dcache" % i),
190 ExternalCache("cpu%d.itb_walker_cache" % i),
191 ExternalCache("cpu%d.dtb_walker_cache" % i))
193 system.cpu[i].addPrivateSplitL1Caches(
194 ExternalCache("cpu
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H A DSimulation.py61 """Returns the required cpu class and the mode of operation."""
66 """Returns two cpu classes and the initial mode of operation.
69 can be done using one type of cpu, and then the actual
145 if testsys.cpu[0].workload[0].simpoint == 0:
147 inst += int(testsys.cpu[0].workload[0].simpoint)
181 testsys.cpu[0].simpoint_start_insts = simpoint_start_insts
351 testsys.cpu[0].simpoint_start_insts = simpoint_start_insts
458 testsys.cpu[i].progress_interval = options.prog_interval
462 testsys.cpu[i].max_insts_any_thread = options.maxinsts
470 testsys.cpu[
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/gem5/system/arm/dt/
H A DMakefile36 CREATE_TARGET=$(foreach n, $(NUM_CPUS), $(1)_$(n)cpu.dtb)
65 .gen/armv7_gem5_v1_%cpu.dts: armv7.dts $(VEXPRESS_GEM5_V1_DTSIS)
68 .gen/armv8_gem5_v1_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V1_DTSIS)
71 .gen/armv8_gem5_v2_%cpu.dts: armv8.dts $(VEXPRESS_GEM5_V2_DTSIS)
/gem5/src/mem/ruby/profiler/
H A DAccessTraceForAddress.cc63 RubyAccessMode access_mode, NodeID cpu,
66 m_touched_by.add(cpu);
62 update(RubyRequestType type, RubyAccessMode access_mode, NodeID cpu, bool sharing_miss) argument
/gem5/src/cpu/minor/
H A Dfetch1.cc40 #include "cpu/minor/fetch1.hh"
47 #include "cpu/minor/pipeline.hh"
63 cpu(cpu_),
82 lineSnap = cpu.cacheLineSize();
88 maxLineWidth = cpu.cacheLineSize();
121 switch (cpu.threadPolicy) {
126 priority_list = cpu.roundRobinPriority(threadPriority);
129 priority_list = cpu.randomPriority();
136 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
171 request->request->setContext(cpu
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/gem5/configs/example/arm/
H A Ddevices.py132 for cpu in self.cpus:
133 cpu.createThreads()
134 cpu.createInterruptController()
135 cpu.socket_id = system.numCpuClusters()
145 for cpu in self.cpus:
150 cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
157 for cpu in self.cpus:
158 cpu.connectAllPorts(self.toL2Bus)
166 for cpu in self.cpus:
167 cpu
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/gem5/src/arch/arm/kvm/
H A Dgic.cc257 MuxingKvmGic::sendPPInt(uint32_t num, uint32_t cpu) argument
260 return GicV2::sendPPInt(num, cpu);
261 DPRINTF(Interrupt, "Set PPI %d:%d\n", cpu, num);
262 kernelGic->setPPI(cpu, num);
266 MuxingKvmGic::clearPPInt(uint32_t num, uint32_t cpu) argument
269 return GicV2::clearPPInt(num, cpu);
271 DPRINTF(Interrupt, "Clear PPI %d:%d\n", cpu, num);
272 kernelGic->clearPPI(cpu, num);
300 DPRINTF(GIC, "copy cpu 0x%x 0x%08x\n", daddr, val);
426 for (int cpu
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/gem5/src/gpu-compute/
H A Ddispatcher.cc41 #include "cpu/base.hh"
54 dispatchCount(0), dispatchActive(false), cpu(p->cpu),
212 accessUserVar(cpu, (uint64_t)(curTask.numDispLeft), 0, 1);
298 if (doneIds.size() && cpu) {
299 shader->hostWakeUp(cpu);
322 accessUserVar(cpu, (uint64_t)(ndRangeMap[kern_id].addrToNotify), 1,
326 accessUserVar(cpu, (uint64_t)(ndRangeMap[kern_id].numDispLeft), 0, -1);
355 GpuDispatcher::accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off) argument
357 if (cpu) {
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/gem5/src/arch/riscv/
H A Dinterrupts.hh40 #include "cpu/thread_context.hh"
57 BaseCPU * cpu; member in class:RiscvISA::Interrupts
70 Interrupts(Params * p) : SimObject(p), cpu(nullptr), ip(0), ie(0) {}
72 void setCPU(BaseCPU * _cpu) { cpu = _cpu; }

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