Lines Matching refs:cpu
40 #include "cpu/minor/fetch1.hh"
47 #include "cpu/minor/pipeline.hh"
63 cpu(cpu_),
82 lineSnap = cpu.cacheLineSize();
88 maxLineWidth = cpu.cacheLineSize();
121 switch (cpu.threadPolicy) {
126 priority_list = cpu.roundRobinPriority(threadPriority);
129 priority_list = cpu.randomPriority();
136 if (cpu.getContext(tid)->status() == ThreadContext::Active &&
171 request->request->setContext(cpu.threads[tid]->getTC()->contextId());
173 aligned_pc, request_size, Request::INST_FETCH, cpu.instMasterId(),
189 cpu.threads[request->id.threadId]->itb->translateTiming(
191 cpu.getContext(request->id.threadId),
249 fetch.cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
306 cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
447 cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
581 for (ThreadID tid = 0; tid < cpu.numThreads; tid++)
680 cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
694 cpu.activityRecorder->activity();
716 ThreadContext *thread_ctx = cpu.getContext(tid);
724 cpu.wakeupOnEvent(Pipeline::Fetch1StageId);
731 for (ThreadID tid = 0; tid < cpu.numThreads; tid++) {