Lines Matching refs:cpu
78 root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096)
126 parser.add_option("--cpu-voltage", action="store", type="string",
252 cpu = TimingSimpleCPU(cpu_id=0)
256 host_cpu = cpu
260 cpu_list = [cpu] + [shader] + [dispatcher]
262 system = System(cpu = cpu_list,
273 system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
290 cpu.createInterruptController()
293 # Tie the cpu cache ports to the ruby cpu ports and
296 cpu.connectAllPorts(system.ruby._cpu_ports[0])
315 system.cpu[shader_idx].CUs[i].memory_port[j] = \
322 system.cpu[shader_idx].CUs[i].sqc_port = \
340 # parameters must be after the explicit setting of the System cpu list
342 dispatcher.cpu = host_cpu