/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64ui/ |
H A D | srlw.S | 38 # Verify that shifts only use bottom five bits
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/gem5/src/arch/arm/ |
H A D | types.hh | 59 * is always the concatenation of the top 3 bits and the next bit, 60 * which applies when one of the bottom 4 bits is set. 79 // ITSTATE bits 403 uint8_t new_bit = bits(cond_mask, 4); 457 if (bits(newPC, 0)) { 463 if (bits(newPC, 0)) { 466 } else if (!bits(newPC, 1)) {
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/gem5/src/arch/sparc/ |
H A D | process.cc | 509 return bits(tc->readIntReg(FirstArgumentReg + i++), 31, 0); 516 tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0)); 546 val = bits(val, 31, 0); 554 val = bits(val, 31, 0);
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H A D | faults.cc | 605 // Clear all the soft interrupt bits 647 bool is_real_address = !bits(tlbdata, 4); 651 bool trapped = bits(tlbdata, 18, 16) > 0; 657 int primary_context = bits(tlbdata, 47, 32); 707 int primary_context = bits(tlbdata, 47, 32); 712 int hpriv = bits(tlbdata, 0); 716 int red = bits(tlbdata, 1); 723 int is_real_address = !bits(tlbdata, 5); 741 bool trapped = bits(tlbdata, 18, 16) > 0;
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H A D | isa.cc | 202 bits((uint64_t)lsuCtrlReg,3,2) << 4 | 203 bits((uint64_t)partId,7,0) << 8 | 204 bits((uint64_t)tl,2,0) << 16 | 346 // I'm not sure why legion ignores the lowest two bits, but we'll go 440 // clear lower 7 bits on writes.
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/gem5/src/cpu/pred/ |
H A D | tage_base.cc | 88 // Current method for periodically resetting the u counter bits only 89 // works for 1 or 2 bits 295 // bits (N = 2 ^ logRatioBiModalHystEntries) 808 size_t bits = 0; local 810 bits += (1 << logTagTableSizes[i]) * 814 bits += numUseAltOnNa * useAltOnNaBits; 815 bits += bimodalTableSize; 816 bits += (bimodalTableSize >> logRatioBiModalHystEntries); 817 bits += histLengths[nHistoryTables]; 818 bits [all...] |
/gem5/src/base/ |
H A D | bitunion.hh | 171 return bits(storage, first, last); 191 return sext<first - last + 1>(bits(storage, first, last));
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/gem5/src/dev/x86/ |
H A D | i82094aa.cc | 138 id = bits(value, 31, 24); 142 arbId = bits(value, 31, 24);
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/gem5/src/arch/hsail/ |
H A D | operand.hh | 353 T bits; member in class:ImmOperand 373 return *(OperandType*)&bits; 403 bits = *((T*)(obj->getData(cbptr->bytes + 4))); 411 bits = std::numeric_limits<unsigned long long>::digits; 452 return csprintf("0x%08x", bits); 634 // bits of the offset must be set to 0 in the BRIG 638 * so here we cast the raw bits we get from the BRIG file to
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/gem5/src/dev/pci/ |
H A D | copy_engine.cc | 259 pkt->setLE<uint32_t>(bits(cr.descChainAddr,0,31)); 263 pkt->setLE<uint32_t>(bits(cr.descChainAddr,32,63)); 274 pkt->setLE<uint32_t>(bits(cr.completionAddr,0,31)); 278 pkt->setLE<uint32_t>(bits(cr.completionAddr,32,63)); 339 regs.intrctrl.master_int_enable(bits(pkt->getLE<uint8_t>(), 0, 1));
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H A D | pcireg.h | 142 #define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw 143 #define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw 300 uint64_t bits; member in struct:MSIXPbaEntry
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 567 newVal = bits(val, 31, 0); 633 if (IRRV > ISRV && bits(IRRV, 7, 4) > 634 bits(regs[APIC_TASK_PRIORITY], 7, 4)) { 646 (IRRV > ISRV && bits(IRRV, 7, 4) > 647 bits(regs[APIC_TASK_PRIORITY], 7, 4));
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H A D | interrupts.hh | 165 return bits(regs[base + (vector / 32)], vector % 32);
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H A D | utility.cc | 267 // make sure reserved bits have the expected values. 358 memcpy(fp80.bits, _mem, 10); 367 memcpy(_mem, fp80.bits, 10);
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H A D | process.cc | 327 TSSDescLow.base = bits(TSSVirtAddr, 31, 0); 330 TSSDescHigh.base = bits(TSSVirtAddr, 63, 32); 507 PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16); 508 PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0); 516 PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
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/gem5/src/dev/arm/ |
H A D | gic_v3_its.hh | 226 * Returns TRUE if the eventID supplied has bits above the implemented 232 * Returns TRUE if the value supplied has bits above the implemented range 247 * Returns TRUE if the value supplied has bits above the implemented range 527 const auto size = bits(command.raw[1], 4, 0); 528 const auto valid = bits(command.raw[2], 63); 537 return its.collectionOutOfRange(bits(command.raw[2], 15, 0));
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H A D | gic_v3_distributor.cc | 102 * (The number of interrupt identifier bits supported, minus one) 385 // 2 bits per interrupt 710 uint8_t prio = bits(data, (i + 1) * 8 - 1, (i * 8)); 773 irqGrpmod[int_id] = bits(data, i); 782 // 2 bits per interrupt 925 const uint32_t intid = bits(data, 9, 0); 944 const uint32_t intid = bits(data, 9, 0); 962 const uint32_t intid = bits(data, 9, 0); 978 const uint32_t intid = bits(data, 9, 0);
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H A D | gic_v3_cpu_interface.cc | 134 // only implemented if supporting 6 or more bits of priority 138 // only implemented if supporting 7 or more bits of priority 141 // only implemented if supporting 7 or more bits of priority 157 // only implemented if supporting 6 or more bits of priority 161 // only implemented if supporting 7 or more bits of priority 164 // only implemented if supporting 7 or more bits of priority 564 // Enforce value for RO bits 570 // IDbits [13:11], 001 = 24 bits | 000 = 16 bits 571 // PRIbits [10:8], number of priority bits implemente [all...] |
/gem5/ext/systemc/src/sysc/datatypes/int/ |
H A D | sc_nbcommon.inc | 50 // Create a CLASS_TYPE number with nb bits. 2459 digit[digit_num] &= DIGIT_MASK; // Needed to zero the overflow bits. 2476 digit[digit_num] &= DIGIT_MASK; // Needed to zero the overflow bits. 2517 // digit. Since buf doesn't have overflow bits, we cannot also do 2530 // Copy the bits from digit to buf. The division and mod operations 2562 // Copy the bits from buf to digit. 2638 // This constructor is mainly used in finding a "range" of bits from a 2656 // make sure that l and r point to the bits of u 2683 // The number of bits up to and including l and r, respectively. 2687 // The indices of the digits that have lth and rth bits, respectivel [all...] |
/gem5/src/dev/storage/ |
H A D | ide_ctrl.cc | 194 pkt->setLE<uint8_t>(bits(htole(primaryTiming), 15, 8)); 197 pkt->setLE<uint8_t>(bits(htole(secondaryTiming), 15, 8)); 200 pkt->setLE<uint8_t>(bits(htole(ideConfig), 7, 0)); 203 pkt->setLE<uint8_t>(bits(htole(ideConfig), 15, 8));
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64si/ |
H A D | dirty.S | 7 # Test VM referenced and dirty bits. 98 # The implementation doesn't appear to set D bits in HW.
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/gem5/src/arch/hsail/insts/ |
H A D | branch.hh | 392 if (width.bits != 1) { 393 widthClause = csprintf("_width(%d)", width.bits);
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/gem5/ext/systemc/src/sysc/kernel/ |
H A D | sc_simcontext.cpp | 1986 if( s & SC_STATUS_ANY ) // combination of status bits 1995 // pretty-print a combination of sc_status bits (i.e. a callback mask) 1999 std::vector<sc_status> bits; local 2002 // collect bits 2006 bits.push_back( (sc_status)is_set ); 2009 if( s & ~SC_STATUS_ANY ) // remaining bits 2010 bits.push_back( (sc_status)( s & ~SC_STATUS_ANY ) ); 2013 std::vector<sc_status>::size_type i=0, n=bits.size(); 2017 os << bits[i] << "|"; local 2018 os << bits[ local [all...] |
/gem5/src/arch/arm/insts/ |
H A D | static_inst.cc | 112 int sign_bit = bits(base, intWidth - 1); 167 uint64_t tmp = (uint64_t) bits(base, len - 1, 0) << shiftAmt; 169 int sign_bit = bits(tmp, len + shiftAmt - 1); 1031 // The IT bits are forced to zero when they are set to a reserved 1033 if (bits(it, 7, 4) != 0 && bits(it, 3, 0) == 0) 1040 // The IT bits are forced to zero when returning to A32 state, or 1042 // bits are describing a multi-instruction block. 1043 if (itd && bits(it, 2, 0) != 0)
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/gem5/src/arch/x86/linux/ |
H A D | process.cc | 227 segDesc.limitLow = bits(userDesc->limit, 15, 0); 228 segDesc.baseLow = bits(userDesc->base_addr, 23, 0); 232 if (bits((uint8_t)flags.contents, 0)) 234 if (bits((uint8_t)flags.contents, 1)) 240 segDesc.limitHigh = bits(userDesc->limit, 19, 16); 248 segDesc.baseHigh = bits(userDesc->base_addr, 31, 24);
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