14166Sgblack@eecs.umich.edu/*
210554Salexandru.dutu@amd.com * Copyright (c) 2014 Advanced Micro Devices, Inc.
37087Snate@binkert.org * Copyright (c) 2007 The Hewlett-Packard Development Company
47087Snate@binkert.org * All rights reserved.
57087Snate@binkert.org *
67087Snate@binkert.org * The license below extends only to copyright in the software and shall
77087Snate@binkert.org * not be construed as granting a license to any other intellectual
87087Snate@binkert.org * property including but not limited to intellectual property relating
97087Snate@binkert.org * to a hardware implementation of the functionality of the software
107087Snate@binkert.org * licensed hereunder.  You may use the software subject to the license
117087Snate@binkert.org * terms below provided that you ensure that this notice is replicated
127087Snate@binkert.org * unmodified and in its entirety in all distributions of the software,
137087Snate@binkert.org * modified or unmodified, in source code or in binary form.
147087Snate@binkert.org *
154166Sgblack@eecs.umich.edu * Copyright (c) 2003-2006 The Regents of The University of Michigan
164166Sgblack@eecs.umich.edu * All rights reserved.
174166Sgblack@eecs.umich.edu *
184166Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without
194166Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are
204166Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright
214166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer;
224166Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright
234166Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the
244166Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution;
254166Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its
264166Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from
274166Sgblack@eecs.umich.edu * this software without specific prior written permission.
284166Sgblack@eecs.umich.edu *
294166Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
304166Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
314166Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
324166Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
334166Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
344166Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
354166Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
364166Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
374166Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
384166Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
394166Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
404166Sgblack@eecs.umich.edu *
414166Sgblack@eecs.umich.edu * Authors: Gabe Black
424166Sgblack@eecs.umich.edu *          Ali Saidi
434166Sgblack@eecs.umich.edu */
444166Sgblack@eecs.umich.edu
4511793Sbrandon.potter@amd.com#include "arch/x86/process.hh"
4611793Sbrandon.potter@amd.com
4711854Sbrandon.potter@amd.com#include <string>
4811854Sbrandon.potter@amd.com#include <vector>
4911854Sbrandon.potter@amd.com
5011793Sbrandon.potter@amd.com#include "arch/x86/isa_traits.hh"
518229Snate@binkert.org#include "arch/x86/regs/misc.hh"
528229Snate@binkert.org#include "arch/x86/regs/segment.hh"
5310554Salexandru.dutu@amd.com#include "arch/x86/system.hh"
544166Sgblack@eecs.umich.edu#include "arch/x86/types.hh"
558229Snate@binkert.org#include "base/loader/elf_object.hh"
564166Sgblack@eecs.umich.edu#include "base/loader/object_file.hh"
5712334Sgabeblack@google.com#include "base/logging.hh"
585004Sgblack@eecs.umich.edu#include "base/trace.hh"
594166Sgblack@eecs.umich.edu#include "cpu/thread_context.hh"
608232Snate@binkert.org#include "debug/Stack.hh"
6110554Salexandru.dutu@amd.com#include "mem/multi_level_page_table.hh"
624166Sgblack@eecs.umich.edu#include "mem/page_table.hh"
6312431Sgabeblack@google.com#include "params/Process.hh"
6411854Sbrandon.potter@amd.com#include "sim/aux_vector.hh"
654434Ssaidi@eecs.umich.edu#include "sim/process_impl.hh"
6611794Sbrandon.potter@amd.com#include "sim/syscall_desc.hh"
6711800Sbrandon.potter@amd.com#include "sim/syscall_return.hh"
684166Sgblack@eecs.umich.edu#include "sim/system.hh"
694166Sgblack@eecs.umich.edu
704166Sgblack@eecs.umich.eduusing namespace std;
714166Sgblack@eecs.umich.eduusing namespace X86ISA;
724166Sgblack@eecs.umich.edu
735958Sgblack@eecs.umich.edustatic const int ArgumentReg[] = {
745958Sgblack@eecs.umich.edu    INTREG_RDI,
755958Sgblack@eecs.umich.edu    INTREG_RSI,
765958Sgblack@eecs.umich.edu    INTREG_RDX,
7711906SBrandon.Potter@amd.com    // This argument register is r10 for syscalls and rcx for C.
785958Sgblack@eecs.umich.edu    INTREG_R10W,
7911906SBrandon.Potter@amd.com    // INTREG_RCX,
805958Sgblack@eecs.umich.edu    INTREG_R8W,
815958Sgblack@eecs.umich.edu    INTREG_R9W
825958Sgblack@eecs.umich.edu};
8311704Santhony.gutierrez@amd.com
8411704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs M5_VAR_USED =
8511704Santhony.gutierrez@amd.com    sizeof(ArgumentReg) / sizeof(const int);
8611704Santhony.gutierrez@amd.com
875959Sgblack@eecs.umich.edustatic const int ArgumentReg32[] = {
885959Sgblack@eecs.umich.edu    INTREG_EBX,
895959Sgblack@eecs.umich.edu    INTREG_ECX,
905959Sgblack@eecs.umich.edu    INTREG_EDX,
915959Sgblack@eecs.umich.edu    INTREG_ESI,
925959Sgblack@eecs.umich.edu    INTREG_EDI,
9311385Sbrandon.potter@amd.com    INTREG_EBP
945959Sgblack@eecs.umich.edu};
9511704Santhony.gutierrez@amd.com
9611704Santhony.gutierrez@amd.comstatic const int NumArgumentRegs32 M5_VAR_USED =
9711704Santhony.gutierrez@amd.com    sizeof(ArgumentReg) / sizeof(const int);
984166Sgblack@eecs.umich.edu
9912460Sgabeblack@google.comtemplate class MultiLevelPageTable<LongModePTE<47, 39>,
10012460Sgabeblack@google.com                                   LongModePTE<38, 30>,
10112460Sgabeblack@google.com                                   LongModePTE<29, 21>,
10212460Sgabeblack@google.com                                   LongModePTE<20, 12> >;
10312460Sgabeblack@google.comtypedef MultiLevelPageTable<LongModePTE<47, 39>,
10412460Sgabeblack@google.com                            LongModePTE<38, 30>,
10512460Sgabeblack@google.com                            LongModePTE<29, 21>,
10612460Sgabeblack@google.com                            LongModePTE<20, 12> > ArchPageTable;
10712460Sgabeblack@google.com
10812431Sgabeblack@google.comX86Process::X86Process(ProcessParams *params, ObjectFile *objFile,
10911851Sbrandon.potter@amd.com                       SyscallDesc *_syscallDescs, int _numSyscallDescs)
11012431Sgabeblack@google.com    : Process(params, params->useArchPT ?
11112448Sgabeblack@google.com                      static_cast<EmulationPageTable *>(
11212460Sgabeblack@google.com                              new ArchPageTable(params->name, params->pid,
11312460Sgabeblack@google.com                                                params->system, PageBytes)) :
11412448Sgabeblack@google.com                      new EmulationPageTable(params->name, params->pid,
11512448Sgabeblack@google.com                                             PageBytes),
11612431Sgabeblack@google.com              objFile),
11712431Sgabeblack@google.com      syscallDescs(_syscallDescs), numSyscallDescs(_numSyscallDescs)
1184166Sgblack@eecs.umich.edu{
11911886Sbrandon.potter@amd.com}
12011886Sbrandon.potter@amd.com
12111886Sbrandon.potter@amd.comvoid X86Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
12213613Sgabeblack@google.com                       Process *p, RegVal flags)
12311886Sbrandon.potter@amd.com{
12411886Sbrandon.potter@amd.com    Process::clone(old_tc, new_tc, p, flags);
12511886Sbrandon.potter@amd.com    X86Process *process = (X86Process*)p;
12611886Sbrandon.potter@amd.com    *process = *this;
1275956Sgblack@eecs.umich.edu}
1284166Sgblack@eecs.umich.edu
12911851Sbrandon.potter@amd.comX86_64Process::X86_64Process(ProcessParams *params, ObjectFile *objFile,
13011851Sbrandon.potter@amd.com                             SyscallDesc *_syscallDescs, int _numSyscallDescs)
13111851Sbrandon.potter@amd.com    : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
1325956Sgblack@eecs.umich.edu{
1336709Svince@csl.cornell.edu
1346709Svince@csl.cornell.edu    vsyscallPage.base = 0xffffffffff600000ULL;
13510318Sandreas.hansson@arm.com    vsyscallPage.size = PageBytes;
1366709Svince@csl.cornell.edu    vsyscallPage.vtimeOffset = 0x400;
1379679Smjleven@sandia.gov    vsyscallPage.vgettimeofdayOffset = 0x0;
1386709Svince@csl.cornell.edu
13911905SBrandon.Potter@amd.com    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
14011905SBrandon.Potter@amd.com                             objFile->bssSize(), PageBytes);
14111905SBrandon.Potter@amd.com    Addr stack_base = 0x7FFFFFFFF000ULL;
14211905SBrandon.Potter@amd.com    Addr max_stack_size = 8 * 1024 * 1024;
14311905SBrandon.Potter@amd.com    Addr next_thread_stack_base = stack_base - max_stack_size;
14411905SBrandon.Potter@amd.com    Addr mmap_end = 0x7FFFF7FFF000ULL;
1454166Sgblack@eecs.umich.edu
14611905SBrandon.Potter@amd.com    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
14711905SBrandon.Potter@amd.com                                     next_thread_stack_base, mmap_end);
1484166Sgblack@eecs.umich.edu}
1494166Sgblack@eecs.umich.edu
1505973Sgblack@eecs.umich.eduvoid
15111877Sbrandon.potter@amd.comI386Process::syscall(int64_t callnum, ThreadContext *tc, Fault *fault)
1525973Sgblack@eecs.umich.edu{
15313915Sgabeblack@google.com    PCState pc = tc->pcState();
1547720Sgblack@eecs.umich.edu    Addr eip = pc.pc();
1555973Sgblack@eecs.umich.edu    if (eip >= vsyscallPage.base &&
1565973Sgblack@eecs.umich.edu            eip < vsyscallPage.base + vsyscallPage.size) {
1577720Sgblack@eecs.umich.edu        pc.npc(vsyscallPage.base + vsyscallPage.vsysexitOffset);
1587720Sgblack@eecs.umich.edu        tc->pcState(pc);
1595973Sgblack@eecs.umich.edu    }
16011877Sbrandon.potter@amd.com    X86Process::syscall(callnum, tc, fault);
1615973Sgblack@eecs.umich.edu}
1625973Sgblack@eecs.umich.edu
1635973Sgblack@eecs.umich.edu
16411851Sbrandon.potter@amd.comI386Process::I386Process(ProcessParams *params, ObjectFile *objFile,
16511851Sbrandon.potter@amd.com                         SyscallDesc *_syscallDescs, int _numSyscallDescs)
16611851Sbrandon.potter@amd.com    : X86Process(params, objFile, _syscallDescs, _numSyscallDescs)
1674166Sgblack@eecs.umich.edu{
16813867Salexandru.dutu@amd.com    if (kvmInSE)
16913867Salexandru.dutu@amd.com        panic("KVM CPU model does not support 32 bit processes");
17013867Salexandru.dutu@amd.com
1719026Sgblack@eecs.umich.edu    _gdtStart = ULL(0xffffd000);
17210318Sandreas.hansson@arm.com    _gdtSize = PageBytes;
1735973Sgblack@eecs.umich.edu
1745973Sgblack@eecs.umich.edu    vsyscallPage.base = 0xffffe000ULL;
17510318Sandreas.hansson@arm.com    vsyscallPage.size = PageBytes;
1765973Sgblack@eecs.umich.edu    vsyscallPage.vsyscallOffset = 0x400;
1775973Sgblack@eecs.umich.edu    vsyscallPage.vsysexitOffset = 0x410;
1785973Sgblack@eecs.umich.edu
17911905SBrandon.Potter@amd.com    Addr brk_point = roundUp(objFile->dataBase() + objFile->dataSize() +
18011905SBrandon.Potter@amd.com                             objFile->bssSize(), PageBytes);
18111905SBrandon.Potter@amd.com    Addr stack_base = _gdtStart;
18211905SBrandon.Potter@amd.com    Addr max_stack_size = 8 * 1024 * 1024;
18311905SBrandon.Potter@amd.com    Addr next_thread_stack_base = stack_base - max_stack_size;
18411905SBrandon.Potter@amd.com    Addr mmap_end = 0xB7FFF000ULL;
1855956Sgblack@eecs.umich.edu
18611905SBrandon.Potter@amd.com    memState = make_shared<MemState>(brk_point, stack_base, max_stack_size,
18711905SBrandon.Potter@amd.com                                     next_thread_stack_base, mmap_end);
1885956Sgblack@eecs.umich.edu}
1895956Sgblack@eecs.umich.edu
1905956Sgblack@eecs.umich.eduSyscallDesc*
19111851Sbrandon.potter@amd.comX86Process::getDesc(int callnum)
1925956Sgblack@eecs.umich.edu{
1935956Sgblack@eecs.umich.edu    if (callnum < 0 || callnum >= numSyscallDescs)
1945956Sgblack@eecs.umich.edu        return NULL;
1955956Sgblack@eecs.umich.edu    return &syscallDescs[callnum];
1964166Sgblack@eecs.umich.edu}
1974166Sgblack@eecs.umich.edu
1984166Sgblack@eecs.umich.eduvoid
19911851Sbrandon.potter@amd.comX86_64Process::initState()
2004166Sgblack@eecs.umich.edu{
20111851Sbrandon.potter@amd.com    X86Process::initState();
2025183Ssaidi@eecs.umich.edu
20313867Salexandru.dutu@amd.com    if (useForClone)
20413867Salexandru.dutu@amd.com        return;
20513867Salexandru.dutu@amd.com
20611884Sbrandon.potter@amd.com    argsInit(PageBytes);
2075140Sgblack@eecs.umich.edu
20811906SBrandon.Potter@amd.com    // Set up the vsyscall page for this process.
2098601Ssteve.reinhardt@amd.com    allocateMem(vsyscallPage.base, vsyscallPage.size);
2106709Svince@csl.cornell.edu    uint8_t vtimeBlob[] = {
2116709Svince@csl.cornell.edu        0x48,0xc7,0xc0,0xc9,0x00,0x00,0x00,    // mov    $0xc9,%rax
2126709Svince@csl.cornell.edu        0x0f,0x05,                             // syscall
2136709Svince@csl.cornell.edu        0xc3                                   // retq
2146709Svince@csl.cornell.edu    };
2158852Sandreas.hansson@arm.com    initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vtimeOffset,
2166709Svince@csl.cornell.edu            vtimeBlob, sizeof(vtimeBlob));
2176709Svince@csl.cornell.edu
2186709Svince@csl.cornell.edu    uint8_t vgettimeofdayBlob[] = {
2196709Svince@csl.cornell.edu        0x48,0xc7,0xc0,0x60,0x00,0x00,0x00,    // mov    $0x60,%rax
2206709Svince@csl.cornell.edu        0x0f,0x05,                             // syscall
2216709Svince@csl.cornell.edu        0xc3                                   // retq
2226709Svince@csl.cornell.edu    };
2238852Sandreas.hansson@arm.com    initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vgettimeofdayOffset,
2246709Svince@csl.cornell.edu            vgettimeofdayBlob, sizeof(vgettimeofdayBlob));
2256709Svince@csl.cornell.edu
22610554Salexandru.dutu@amd.com    if (kvmInSE) {
22710554Salexandru.dutu@amd.com        PortProxy physProxy = system->physProxy;
2285140Sgblack@eecs.umich.edu
22912458Sgabeblack@google.com        Addr syscallCodePhysAddr = system->allocPhysPages(1);
23012458Sgabeblack@google.com        Addr gdtPhysAddr = system->allocPhysPages(1);
23112458Sgabeblack@google.com        Addr idtPhysAddr = system->allocPhysPages(1);
23212458Sgabeblack@google.com        Addr istPhysAddr = system->allocPhysPages(1);
23312458Sgabeblack@google.com        Addr tssPhysAddr = system->allocPhysPages(1);
23412458Sgabeblack@google.com        Addr pfHandlerPhysAddr = system->allocPhysPages(1);
23512458Sgabeblack@google.com
23610554Salexandru.dutu@amd.com        /*
23710554Salexandru.dutu@amd.com         * Set up the gdt.
23810554Salexandru.dutu@amd.com         */
23910554Salexandru.dutu@amd.com        uint8_t numGDTEntries = 0;
24010554Salexandru.dutu@amd.com        uint64_t nullDescriptor = 0;
24112458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
24214010Sgabeblack@google.com                            &nullDescriptor, 8);
24310554Salexandru.dutu@amd.com        numGDTEntries++;
2445140Sgblack@eecs.umich.edu
24510554Salexandru.dutu@amd.com        SegDescriptor initDesc = 0;
24610554Salexandru.dutu@amd.com        initDesc.type.codeOrData = 0; // code or data type
24710554Salexandru.dutu@amd.com        initDesc.type.c = 0;          // conforming
24810554Salexandru.dutu@amd.com        initDesc.type.r = 1;          // readable
24910554Salexandru.dutu@amd.com        initDesc.dpl = 0;             // privilege
25010554Salexandru.dutu@amd.com        initDesc.p = 1;               // present
25110554Salexandru.dutu@amd.com        initDesc.l = 1;               // longmode - 64 bit
25210554Salexandru.dutu@amd.com        initDesc.d = 0;               // operand size
25310554Salexandru.dutu@amd.com        initDesc.s = 1;               // system segment
25412588Sgabeblack@google.com        initDesc.limit = 0xFFFFFFFF;
25512588Sgabeblack@google.com        initDesc.base = 0;
25610554Salexandru.dutu@amd.com
25710554Salexandru.dutu@amd.com        //64 bit code segment
25810554Salexandru.dutu@amd.com        SegDescriptor csLowPLDesc = initDesc;
25910554Salexandru.dutu@amd.com        csLowPLDesc.type.codeOrData = 1;
26010554Salexandru.dutu@amd.com        csLowPLDesc.dpl = 0;
26110554Salexandru.dutu@amd.com        uint64_t csLowPLDescVal = csLowPLDesc;
26212458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
26314010Sgabeblack@google.com                            &csLowPLDescVal, 8);
26410554Salexandru.dutu@amd.com
26510554Salexandru.dutu@amd.com        numGDTEntries++;
26610554Salexandru.dutu@amd.com
26710554Salexandru.dutu@amd.com        SegSelector csLowPL = 0;
26810554Salexandru.dutu@amd.com        csLowPL.si = numGDTEntries - 1;
26910554Salexandru.dutu@amd.com        csLowPL.rpl = 0;
27010554Salexandru.dutu@amd.com
27110554Salexandru.dutu@amd.com        //64 bit data segment
27210554Salexandru.dutu@amd.com        SegDescriptor dsLowPLDesc = initDesc;
27310554Salexandru.dutu@amd.com        dsLowPLDesc.type.codeOrData = 0;
27410554Salexandru.dutu@amd.com        dsLowPLDesc.dpl = 0;
27510554Salexandru.dutu@amd.com        uint64_t dsLowPLDescVal = dsLowPLDesc;
27612458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
27714010Sgabeblack@google.com                            &dsLowPLDescVal, 8);
27810554Salexandru.dutu@amd.com
27910554Salexandru.dutu@amd.com        numGDTEntries++;
28010554Salexandru.dutu@amd.com
28110554Salexandru.dutu@amd.com        SegSelector dsLowPL = 0;
28210554Salexandru.dutu@amd.com        dsLowPL.si = numGDTEntries - 1;
28310554Salexandru.dutu@amd.com        dsLowPL.rpl = 0;
28410554Salexandru.dutu@amd.com
28510554Salexandru.dutu@amd.com        //64 bit data segment
28610554Salexandru.dutu@amd.com        SegDescriptor dsDesc = initDesc;
28710554Salexandru.dutu@amd.com        dsDesc.type.codeOrData = 0;
28810554Salexandru.dutu@amd.com        dsDesc.dpl = 3;
28910554Salexandru.dutu@amd.com        uint64_t dsDescVal = dsDesc;
29012458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
29114010Sgabeblack@google.com                            &dsDescVal, 8);
29210554Salexandru.dutu@amd.com
29310554Salexandru.dutu@amd.com        numGDTEntries++;
29410554Salexandru.dutu@amd.com
29510554Salexandru.dutu@amd.com        SegSelector ds = 0;
29610554Salexandru.dutu@amd.com        ds.si = numGDTEntries - 1;
29710554Salexandru.dutu@amd.com        ds.rpl = 3;
29810554Salexandru.dutu@amd.com
29910554Salexandru.dutu@amd.com        //64 bit code segment
30010554Salexandru.dutu@amd.com        SegDescriptor csDesc = initDesc;
30110554Salexandru.dutu@amd.com        csDesc.type.codeOrData = 1;
30210554Salexandru.dutu@amd.com        csDesc.dpl = 3;
30310554Salexandru.dutu@amd.com        uint64_t csDescVal = csDesc;
30412458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
30514010Sgabeblack@google.com                            &csDescVal, 8);
30610554Salexandru.dutu@amd.com
30710554Salexandru.dutu@amd.com        numGDTEntries++;
30810554Salexandru.dutu@amd.com
30910554Salexandru.dutu@amd.com        SegSelector cs = 0;
31010554Salexandru.dutu@amd.com        cs.si = numGDTEntries - 1;
31110554Salexandru.dutu@amd.com        cs.rpl = 3;
31210554Salexandru.dutu@amd.com
31310554Salexandru.dutu@amd.com        SegSelector scall = 0;
31410554Salexandru.dutu@amd.com        scall.si = csLowPL.si;
31510554Salexandru.dutu@amd.com        scall.rpl = 0;
31610554Salexandru.dutu@amd.com
31710554Salexandru.dutu@amd.com        SegSelector sret = 0;
31810554Salexandru.dutu@amd.com        sret.si = dsLowPL.si;
31910554Salexandru.dutu@amd.com        sret.rpl = 3;
32010554Salexandru.dutu@amd.com
32110554Salexandru.dutu@amd.com        /* In long mode the TSS has been extended to 16 Bytes */
32210554Salexandru.dutu@amd.com        TSSlow TSSDescLow = 0;
32310554Salexandru.dutu@amd.com        TSSDescLow.type = 0xB;
32410554Salexandru.dutu@amd.com        TSSDescLow.dpl = 0; // Privelege level 0
32510554Salexandru.dutu@amd.com        TSSDescLow.p = 1; // Present
32612588Sgabeblack@google.com        TSSDescLow.limit = 0xFFFFFFFF;
32712588Sgabeblack@google.com        TSSDescLow.base = bits(TSSVirtAddr, 31, 0);
32810554Salexandru.dutu@amd.com
32910554Salexandru.dutu@amd.com        TSShigh TSSDescHigh = 0;
33010590Sgabeblack@google.com        TSSDescHigh.base = bits(TSSVirtAddr, 63, 32);
33110554Salexandru.dutu@amd.com
33210554Salexandru.dutu@amd.com        struct TSSDesc {
33310554Salexandru.dutu@amd.com            uint64_t low;
33410554Salexandru.dutu@amd.com            uint64_t high;
33510554Salexandru.dutu@amd.com        } tssDescVal = {TSSDescLow, TSSDescHigh};
33610554Salexandru.dutu@amd.com
33712458Sgabeblack@google.com        physProxy.writeBlob(gdtPhysAddr + numGDTEntries * 8,
33814010Sgabeblack@google.com                            &tssDescVal, sizeof(tssDescVal));
33910554Salexandru.dutu@amd.com
34010554Salexandru.dutu@amd.com        numGDTEntries++;
34110554Salexandru.dutu@amd.com
34210554Salexandru.dutu@amd.com        SegSelector tssSel = 0;
34310554Salexandru.dutu@amd.com        tssSel.si = numGDTEntries - 1;
34410554Salexandru.dutu@amd.com
34512588Sgabeblack@google.com        uint64_t tss_base_addr = (TSSDescHigh.base << 32) | TSSDescLow.base;
34612588Sgabeblack@google.com        uint64_t tss_limit = TSSDescLow.limit;
34710554Salexandru.dutu@amd.com
34810554Salexandru.dutu@amd.com        SegAttr tss_attr = 0;
34910554Salexandru.dutu@amd.com
35010554Salexandru.dutu@amd.com        tss_attr.type = TSSDescLow.type;
35110554Salexandru.dutu@amd.com        tss_attr.dpl = TSSDescLow.dpl;
35210554Salexandru.dutu@amd.com        tss_attr.present = TSSDescLow.p;
35310554Salexandru.dutu@amd.com        tss_attr.granularity = TSSDescLow.g;
35410554Salexandru.dutu@amd.com        tss_attr.unusable = 0;
35510554Salexandru.dutu@amd.com
35610554Salexandru.dutu@amd.com        for (int i = 0; i < contextIds.size(); i++) {
35710554Salexandru.dutu@amd.com            ThreadContext * tc = system->getThreadContext(contextIds[i]);
35810554Salexandru.dutu@amd.com
35910590Sgabeblack@google.com            tc->setMiscReg(MISCREG_CS, cs);
36010590Sgabeblack@google.com            tc->setMiscReg(MISCREG_DS, ds);
36110590Sgabeblack@google.com            tc->setMiscReg(MISCREG_ES, ds);
36210590Sgabeblack@google.com            tc->setMiscReg(MISCREG_FS, ds);
36310590Sgabeblack@google.com            tc->setMiscReg(MISCREG_GS, ds);
36410590Sgabeblack@google.com            tc->setMiscReg(MISCREG_SS, ds);
36510554Salexandru.dutu@amd.com
36610554Salexandru.dutu@amd.com            // LDT
36710554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_TSL, 0);
36810554Salexandru.dutu@amd.com            SegAttr tslAttr = 0;
36910554Salexandru.dutu@amd.com            tslAttr.present = 1;
37010554Salexandru.dutu@amd.com            tslAttr.type = 2;
37110554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
37210554Salexandru.dutu@amd.com
37310554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
37410554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_TSG_LIMIT, 8 * numGDTEntries - 1);
37510554Salexandru.dutu@amd.com
37610590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TR, tssSel);
37710590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TR_BASE, tss_base_addr);
37810590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TR_EFF_BASE, 0);
37910590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TR_LIMIT, tss_limit);
38010590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TR_ATTR, tss_attr);
38110554Salexandru.dutu@amd.com
38210554Salexandru.dutu@amd.com            //Start using longmode segments.
38310554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_CS, csDesc, true);
38410554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_DS, dsDesc, true);
38510554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_ES, dsDesc, true);
38610554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_FS, dsDesc, true);
38710554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_GS, dsDesc, true);
38810554Salexandru.dutu@amd.com            installSegDesc(tc, SEGMENT_REG_SS, dsDesc, true);
38910554Salexandru.dutu@amd.com
39010554Salexandru.dutu@amd.com            Efer efer = 0;
39110554Salexandru.dutu@amd.com            efer.sce = 1; // Enable system call extensions.
39210554Salexandru.dutu@amd.com            efer.lme = 1; // Enable long mode.
39310554Salexandru.dutu@amd.com            efer.lma = 1; // Activate long mode.
39410554Salexandru.dutu@amd.com            efer.nxe = 0; // Enable nx support.
39510554Salexandru.dutu@amd.com            efer.svme = 1; // Enable svm support for now.
39610554Salexandru.dutu@amd.com            efer.ffxsr = 0; // Turn on fast fxsave and fxrstor.
39710554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_EFER, efer);
39810554Salexandru.dutu@amd.com
39910554Salexandru.dutu@amd.com            //Set up the registers that describe the operating mode.
40010554Salexandru.dutu@amd.com            CR0 cr0 = 0;
40110554Salexandru.dutu@amd.com            cr0.pg = 1; // Turn on paging.
40210554Salexandru.dutu@amd.com            cr0.cd = 0; // Don't disable caching.
40310554Salexandru.dutu@amd.com            cr0.nw = 0; // This is bit is defined to be ignored.
40410554Salexandru.dutu@amd.com            cr0.am = 1; // No alignment checking
40510554Salexandru.dutu@amd.com            cr0.wp = 1; // Supervisor mode can write read only pages
40610554Salexandru.dutu@amd.com            cr0.ne = 1;
40710554Salexandru.dutu@amd.com            cr0.et = 1; // This should always be 1
40810554Salexandru.dutu@amd.com            cr0.ts = 0; // We don't do task switching, so causing fp exceptions
40910554Salexandru.dutu@amd.com                        // would be pointless.
41010554Salexandru.dutu@amd.com            cr0.em = 0; // Allow x87 instructions to execute natively.
41110554Salexandru.dutu@amd.com            cr0.mp = 1; // This doesn't really matter, but the manual suggests
41210554Salexandru.dutu@amd.com                        // setting it to one.
41310554Salexandru.dutu@amd.com            cr0.pe = 1; // We're definitely in protected mode.
41410554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR0, cr0);
41510554Salexandru.dutu@amd.com
41610554Salexandru.dutu@amd.com            CR0 cr2 = 0;
41710554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR2, cr2);
41810554Salexandru.dutu@amd.com
41912458Sgabeblack@google.com            CR3 cr3 = dynamic_cast<ArchPageTable *>(pTable)->basePtr();
42010554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR3, cr3);
42110554Salexandru.dutu@amd.com
42210554Salexandru.dutu@amd.com            CR4 cr4 = 0;
42310554Salexandru.dutu@amd.com            //Turn on pae.
42410554Salexandru.dutu@amd.com            cr4.osxsave = 1; // Enable XSAVE and Proc Extended States
42510554Salexandru.dutu@amd.com            cr4.osxmmexcpt = 1; // Operating System Unmasked Exception
42610554Salexandru.dutu@amd.com            cr4.osfxsr = 1; // Operating System FXSave/FSRSTOR Support
42710554Salexandru.dutu@amd.com            cr4.pce = 0; // Performance-Monitoring Counter Enable
42810554Salexandru.dutu@amd.com            cr4.pge = 0; // Page-Global Enable
42910554Salexandru.dutu@amd.com            cr4.mce = 0; // Machine Check Enable
43010554Salexandru.dutu@amd.com            cr4.pae = 1; // Physical-Address Extension
43110554Salexandru.dutu@amd.com            cr4.pse = 0; // Page Size Extensions
43210554Salexandru.dutu@amd.com            cr4.de = 0; // Debugging Extensions
43310554Salexandru.dutu@amd.com            cr4.tsd = 0; // Time Stamp Disable
43410554Salexandru.dutu@amd.com            cr4.pvi = 0; // Protected-Mode Virtual Interrupts
43510554Salexandru.dutu@amd.com            cr4.vme = 0; // Virtual-8086 Mode Extensions
43610554Salexandru.dutu@amd.com
43710554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR4, cr4);
43810554Salexandru.dutu@amd.com
43910554Salexandru.dutu@amd.com            CR4 cr8 = 0;
44010554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR8, cr8);
44110554Salexandru.dutu@amd.com
44210554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
44310554Salexandru.dutu@amd.com
44410554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_APIC_BASE, 0xfee00900);
44510554Salexandru.dutu@amd.com
44610590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TSG_BASE, GDTVirtAddr);
44710590Sgabeblack@google.com            tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
44810554Salexandru.dutu@amd.com
44910590Sgabeblack@google.com            tc->setMiscReg(MISCREG_IDTR_BASE, IDTVirtAddr);
45010590Sgabeblack@google.com            tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
45110554Salexandru.dutu@amd.com
45210554Salexandru.dutu@amd.com            /* enabling syscall and sysret */
45313613Sgabeblack@google.com            RegVal star = ((RegVal)sret << 48) | ((RegVal)scall << 32);
45410554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_STAR, star);
45513613Sgabeblack@google.com            RegVal lstar = (RegVal)syscallCodeVirtAddr;
45610554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_LSTAR, lstar);
45713613Sgabeblack@google.com            RegVal sfmask = (1 << 8) | (1 << 10); // TF | DF
45810554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_SF_MASK, sfmask);
4595140Sgblack@eecs.umich.edu        }
4605140Sgblack@eecs.umich.edu
46110590Sgabeblack@google.com        /* Set up the content of the TSS and write it to physical memory. */
4625140Sgblack@eecs.umich.edu
46310554Salexandru.dutu@amd.com        struct {
46410554Salexandru.dutu@amd.com            uint32_t reserved0;        // +00h
46510554Salexandru.dutu@amd.com            uint32_t RSP0_low;         // +04h
46610554Salexandru.dutu@amd.com            uint32_t RSP0_high;        // +08h
46710554Salexandru.dutu@amd.com            uint32_t RSP1_low;         // +0Ch
46810554Salexandru.dutu@amd.com            uint32_t RSP1_high;        // +10h
46910554Salexandru.dutu@amd.com            uint32_t RSP2_low;         // +14h
47010554Salexandru.dutu@amd.com            uint32_t RSP2_high;        // +18h
47110554Salexandru.dutu@amd.com            uint32_t reserved1;        // +1Ch
47210554Salexandru.dutu@amd.com            uint32_t reserved2;        // +20h
47310554Salexandru.dutu@amd.com            uint32_t IST1_low;         // +24h
47410554Salexandru.dutu@amd.com            uint32_t IST1_high;        // +28h
47510554Salexandru.dutu@amd.com            uint32_t IST2_low;         // +2Ch
47610554Salexandru.dutu@amd.com            uint32_t IST2_high;        // +30h
47710554Salexandru.dutu@amd.com            uint32_t IST3_low;         // +34h
47810554Salexandru.dutu@amd.com            uint32_t IST3_high;        // +38h
47910554Salexandru.dutu@amd.com            uint32_t IST4_low;         // +3Ch
48010554Salexandru.dutu@amd.com            uint32_t IST4_high;        // +40h
48110554Salexandru.dutu@amd.com            uint32_t IST5_low;         // +44h
48210554Salexandru.dutu@amd.com            uint32_t IST5_high;        // +48h
48310554Salexandru.dutu@amd.com            uint32_t IST6_low;         // +4Ch
48410554Salexandru.dutu@amd.com            uint32_t IST6_high;        // +50h
48510554Salexandru.dutu@amd.com            uint32_t IST7_low;         // +54h
48610554Salexandru.dutu@amd.com            uint32_t IST7_high;        // +58h
48710554Salexandru.dutu@amd.com            uint32_t reserved3;        // +5Ch
48810554Salexandru.dutu@amd.com            uint32_t reserved4;        // +60h
48910554Salexandru.dutu@amd.com            uint16_t reserved5;        // +64h
49010554Salexandru.dutu@amd.com            uint16_t IO_MapBase;       // +66h
49110554Salexandru.dutu@amd.com        } tss;
4925140Sgblack@eecs.umich.edu
49310554Salexandru.dutu@amd.com        /** setting Interrupt Stack Table */
49410554Salexandru.dutu@amd.com        uint64_t IST_start = ISTVirtAddr + PageBytes;
49510590Sgabeblack@google.com        tss.IST1_low  = IST_start;
49610590Sgabeblack@google.com        tss.IST1_high = IST_start >> 32;
49710554Salexandru.dutu@amd.com        tss.RSP0_low  = tss.IST1_low;
49810554Salexandru.dutu@amd.com        tss.RSP0_high = tss.IST1_high;
49910554Salexandru.dutu@amd.com        tss.RSP1_low  = tss.IST1_low;
50010554Salexandru.dutu@amd.com        tss.RSP1_high = tss.IST1_high;
50110554Salexandru.dutu@amd.com        tss.RSP2_low  = tss.IST1_low;
50210554Salexandru.dutu@amd.com        tss.RSP2_high = tss.IST1_high;
50314010Sgabeblack@google.com        physProxy.writeBlob(tssPhysAddr, &tss, sizeof(tss));
5046140Sgblack@eecs.umich.edu
50510554Salexandru.dutu@amd.com        /* Setting IDT gates */
50610554Salexandru.dutu@amd.com        GateDescriptorLow PFGateLow = 0;
50710590Sgabeblack@google.com        PFGateLow.offsetHigh = bits(PFHandlerVirtAddr, 31, 16);
50810590Sgabeblack@google.com        PFGateLow.offsetLow = bits(PFHandlerVirtAddr, 15, 0);
50910590Sgabeblack@google.com        PFGateLow.selector = csLowPL;
51010554Salexandru.dutu@amd.com        PFGateLow.p = 1;
51110554Salexandru.dutu@amd.com        PFGateLow.dpl = 0;
51210554Salexandru.dutu@amd.com        PFGateLow.type = 0xe;      // gate interrupt type
51310554Salexandru.dutu@amd.com        PFGateLow.IST = 0;         // setting IST to 0 and using RSP0
5146609Sgblack@eecs.umich.edu
51510554Salexandru.dutu@amd.com        GateDescriptorHigh PFGateHigh = 0;
51610590Sgabeblack@google.com        PFGateHigh.offset = bits(PFHandlerVirtAddr, 63, 32);
51710554Salexandru.dutu@amd.com
51810554Salexandru.dutu@amd.com        struct {
51910554Salexandru.dutu@amd.com            uint64_t low;
52010554Salexandru.dutu@amd.com            uint64_t high;
52110554Salexandru.dutu@amd.com        } PFGate = {PFGateLow, PFGateHigh};
52210554Salexandru.dutu@amd.com
52314010Sgabeblack@google.com        physProxy.writeBlob(idtPhysAddr + 0xE0, &PFGate, sizeof(PFGate));
52410554Salexandru.dutu@amd.com
52510590Sgabeblack@google.com        /* System call handler */
52610554Salexandru.dutu@amd.com        uint8_t syscallBlob[] = {
52710590Sgabeblack@google.com            // mov    %rax, (0xffffc90000005600)
52810590Sgabeblack@google.com            0x48, 0xa3, 0x00, 0x60, 0x00,
52910590Sgabeblack@google.com            0x00, 0x00, 0xc9, 0xff, 0xff,
53010590Sgabeblack@google.com            // sysret
53110590Sgabeblack@google.com            0x48, 0x0f, 0x07
53210554Salexandru.dutu@amd.com        };
53310554Salexandru.dutu@amd.com
53410554Salexandru.dutu@amd.com        physProxy.writeBlob(syscallCodePhysAddr,
53510554Salexandru.dutu@amd.com                            syscallBlob, sizeof(syscallBlob));
53610554Salexandru.dutu@amd.com
53710554Salexandru.dutu@amd.com        /** Page fault handler */
53810554Salexandru.dutu@amd.com        uint8_t faultBlob[] = {
53910590Sgabeblack@google.com            // mov    %rax, (0xffffc90000005700)
54010590Sgabeblack@google.com            0x48, 0xa3, 0x00, 0x61, 0x00,
54110590Sgabeblack@google.com            0x00, 0x00, 0xc9, 0xff, 0xff,
54210590Sgabeblack@google.com            // add    $0x8, %rsp # skip error
54310590Sgabeblack@google.com            0x48, 0x83, 0xc4, 0x08,
54410590Sgabeblack@google.com            // iretq
54510590Sgabeblack@google.com            0x48, 0xcf
54610554Salexandru.dutu@amd.com        };
54710554Salexandru.dutu@amd.com
54812458Sgabeblack@google.com        physProxy.writeBlob(pfHandlerPhysAddr, faultBlob, sizeof(faultBlob));
54910554Salexandru.dutu@amd.com
55010554Salexandru.dutu@amd.com        /* Syscall handler */
55112460Sgabeblack@google.com        pTable->map(syscallCodeVirtAddr, syscallCodePhysAddr,
55212460Sgabeblack@google.com                    PageBytes, false);
55310554Salexandru.dutu@amd.com        /* GDT */
55412460Sgabeblack@google.com        pTable->map(GDTVirtAddr, gdtPhysAddr, PageBytes, false);
55510554Salexandru.dutu@amd.com        /* IDT */
55612460Sgabeblack@google.com        pTable->map(IDTVirtAddr, idtPhysAddr, PageBytes, false);
55710554Salexandru.dutu@amd.com        /* TSS */
55812460Sgabeblack@google.com        pTable->map(TSSVirtAddr, tssPhysAddr, PageBytes, false);
55910554Salexandru.dutu@amd.com        /* IST */
56012460Sgabeblack@google.com        pTable->map(ISTVirtAddr, istPhysAddr, PageBytes, false);
56110554Salexandru.dutu@amd.com        /* PF handler */
56212460Sgabeblack@google.com        pTable->map(PFHandlerVirtAddr, pfHandlerPhysAddr, PageBytes, false);
56310554Salexandru.dutu@amd.com        /* MMIO region for m5ops */
56412460Sgabeblack@google.com        pTable->map(MMIORegionVirtAddr, MMIORegionPhysAddr,
56512460Sgabeblack@google.com                    16 * PageBytes, false);
56610554Salexandru.dutu@amd.com    } else {
56710554Salexandru.dutu@amd.com        for (int i = 0; i < contextIds.size(); i++) {
56810554Salexandru.dutu@amd.com            ThreadContext * tc = system->getThreadContext(contextIds[i]);
56910554Salexandru.dutu@amd.com
57010554Salexandru.dutu@amd.com            SegAttr dataAttr = 0;
57110554Salexandru.dutu@amd.com            dataAttr.dpl = 3;
57210554Salexandru.dutu@amd.com            dataAttr.unusable = 0;
57310554Salexandru.dutu@amd.com            dataAttr.defaultSize = 1;
57410554Salexandru.dutu@amd.com            dataAttr.longMode = 1;
57510554Salexandru.dutu@amd.com            dataAttr.avl = 0;
57610554Salexandru.dutu@amd.com            dataAttr.granularity = 1;
57710554Salexandru.dutu@amd.com            dataAttr.present = 1;
57810554Salexandru.dutu@amd.com            dataAttr.type = 3;
57910554Salexandru.dutu@amd.com            dataAttr.writable = 1;
58010554Salexandru.dutu@amd.com            dataAttr.readable = 1;
58110554Salexandru.dutu@amd.com            dataAttr.expandDown = 0;
58210554Salexandru.dutu@amd.com            dataAttr.system = 1;
58310554Salexandru.dutu@amd.com
58411906SBrandon.Potter@amd.com            // Initialize the segment registers.
58511321Ssteve.reinhardt@amd.com            for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
58610554Salexandru.dutu@amd.com                tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
58710554Salexandru.dutu@amd.com                tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
58810554Salexandru.dutu@amd.com                tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
58910554Salexandru.dutu@amd.com            }
59010554Salexandru.dutu@amd.com
59110554Salexandru.dutu@amd.com            SegAttr csAttr = 0;
59210554Salexandru.dutu@amd.com            csAttr.dpl = 3;
59310554Salexandru.dutu@amd.com            csAttr.unusable = 0;
59410554Salexandru.dutu@amd.com            csAttr.defaultSize = 0;
59510554Salexandru.dutu@amd.com            csAttr.longMode = 1;
59610554Salexandru.dutu@amd.com            csAttr.avl = 0;
59710554Salexandru.dutu@amd.com            csAttr.granularity = 1;
59810554Salexandru.dutu@amd.com            csAttr.present = 1;
59910554Salexandru.dutu@amd.com            csAttr.type = 10;
60010554Salexandru.dutu@amd.com            csAttr.writable = 0;
60110554Salexandru.dutu@amd.com            csAttr.readable = 1;
60210554Salexandru.dutu@amd.com            csAttr.expandDown = 0;
60310554Salexandru.dutu@amd.com            csAttr.system = 1;
60410554Salexandru.dutu@amd.com
60510554Salexandru.dutu@amd.com            tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
60610554Salexandru.dutu@amd.com
60710554Salexandru.dutu@amd.com            Efer efer = 0;
60810554Salexandru.dutu@amd.com            efer.sce = 1; // Enable system call extensions.
60910554Salexandru.dutu@amd.com            efer.lme = 1; // Enable long mode.
61010554Salexandru.dutu@amd.com            efer.lma = 1; // Activate long mode.
61110554Salexandru.dutu@amd.com            efer.nxe = 1; // Enable nx support.
61210554Salexandru.dutu@amd.com            efer.svme = 0; // Disable svm support for now. It isn't implemented.
61310554Salexandru.dutu@amd.com            efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
61410554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_EFER, efer);
61510554Salexandru.dutu@amd.com
61611906SBrandon.Potter@amd.com            // Set up the registers that describe the operating mode.
61710554Salexandru.dutu@amd.com            CR0 cr0 = 0;
61810554Salexandru.dutu@amd.com            cr0.pg = 1; // Turn on paging.
61910554Salexandru.dutu@amd.com            cr0.cd = 0; // Don't disable caching.
62010554Salexandru.dutu@amd.com            cr0.nw = 0; // This is bit is defined to be ignored.
62110554Salexandru.dutu@amd.com            cr0.am = 0; // No alignment checking
62210554Salexandru.dutu@amd.com            cr0.wp = 0; // Supervisor mode can write read only pages
62310554Salexandru.dutu@amd.com            cr0.ne = 1;
62410554Salexandru.dutu@amd.com            cr0.et = 1; // This should always be 1
62510554Salexandru.dutu@amd.com            cr0.ts = 0; // We don't do task switching, so causing fp exceptions
62610554Salexandru.dutu@amd.com                        // would be pointless.
62710554Salexandru.dutu@amd.com            cr0.em = 0; // Allow x87 instructions to execute natively.
62810554Salexandru.dutu@amd.com            cr0.mp = 1; // This doesn't really matter, but the manual suggests
62910554Salexandru.dutu@amd.com                        // setting it to one.
63010554Salexandru.dutu@amd.com            cr0.pe = 1; // We're definitely in protected mode.
63110554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_CR0, cr0);
63210554Salexandru.dutu@amd.com
63310554Salexandru.dutu@amd.com            tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
63410554Salexandru.dutu@amd.com        }
6355140Sgblack@eecs.umich.edu    }
6364166Sgblack@eecs.umich.edu}
6374166Sgblack@eecs.umich.edu
6384166Sgblack@eecs.umich.eduvoid
63911851Sbrandon.potter@amd.comI386Process::initState()
6404166Sgblack@eecs.umich.edu{
64111851Sbrandon.potter@amd.com    X86Process::initState();
6425956Sgblack@eecs.umich.edu
64311884Sbrandon.potter@amd.com    argsInit(PageBytes);
6445956Sgblack@eecs.umich.edu
64511320Ssteve.reinhardt@amd.com    /*
6465962Sgblack@eecs.umich.edu     * Set up a GDT for this process. The whole GDT wouldn't really be for
6475962Sgblack@eecs.umich.edu     * this process, but the only parts we care about are.
6485962Sgblack@eecs.umich.edu     */
6498601Ssteve.reinhardt@amd.com    allocateMem(_gdtStart, _gdtSize);
6505962Sgblack@eecs.umich.edu    uint64_t zero = 0;
6515962Sgblack@eecs.umich.edu    assert(_gdtSize % sizeof(zero) == 0);
6525962Sgblack@eecs.umich.edu    for (Addr gdtCurrent = _gdtStart;
6535962Sgblack@eecs.umich.edu            gdtCurrent < _gdtStart + _gdtSize; gdtCurrent += sizeof(zero)) {
6548852Sandreas.hansson@arm.com        initVirtMem.write(gdtCurrent, zero);
6555962Sgblack@eecs.umich.edu    }
6565962Sgblack@eecs.umich.edu
6575973Sgblack@eecs.umich.edu    // Set up the vsyscall page for this process.
6588601Ssteve.reinhardt@amd.com    allocateMem(vsyscallPage.base, vsyscallPage.size);
6595973Sgblack@eecs.umich.edu    uint8_t vsyscallBlob[] = {
6605973Sgblack@eecs.umich.edu        0x51,       // push %ecx
6615973Sgblack@eecs.umich.edu        0x52,       // push %edp
6625973Sgblack@eecs.umich.edu        0x55,       // push %ebp
6635973Sgblack@eecs.umich.edu        0x89, 0xe5, // mov %esp, %ebp
6645973Sgblack@eecs.umich.edu        0x0f, 0x34  // sysenter
6655973Sgblack@eecs.umich.edu    };
6668852Sandreas.hansson@arm.com    initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsyscallOffset,
6675973Sgblack@eecs.umich.edu            vsyscallBlob, sizeof(vsyscallBlob));
6685973Sgblack@eecs.umich.edu
6695973Sgblack@eecs.umich.edu    uint8_t vsysexitBlob[] = {
6705973Sgblack@eecs.umich.edu        0x5d,       // pop %ebp
6715973Sgblack@eecs.umich.edu        0x5a,       // pop %edx
6725973Sgblack@eecs.umich.edu        0x59,       // pop %ecx
6735973Sgblack@eecs.umich.edu        0xc3        // ret
6745973Sgblack@eecs.umich.edu    };
6758852Sandreas.hansson@arm.com    initVirtMem.writeBlob(vsyscallPage.base + vsyscallPage.vsysexitOffset,
6765973Sgblack@eecs.umich.edu            vsysexitBlob, sizeof(vsysexitBlob));
6775973Sgblack@eecs.umich.edu
6785956Sgblack@eecs.umich.edu    for (int i = 0; i < contextIds.size(); i++) {
6795956Sgblack@eecs.umich.edu        ThreadContext * tc = system->getThreadContext(contextIds[i]);
6805956Sgblack@eecs.umich.edu
6815956Sgblack@eecs.umich.edu        SegAttr dataAttr = 0;
6826222Sgblack@eecs.umich.edu        dataAttr.dpl = 3;
6836222Sgblack@eecs.umich.edu        dataAttr.unusable = 0;
6846222Sgblack@eecs.umich.edu        dataAttr.defaultSize = 1;
6856222Sgblack@eecs.umich.edu        dataAttr.longMode = 0;
6866222Sgblack@eecs.umich.edu        dataAttr.avl = 0;
6876222Sgblack@eecs.umich.edu        dataAttr.granularity = 1;
6886222Sgblack@eecs.umich.edu        dataAttr.present = 1;
6896222Sgblack@eecs.umich.edu        dataAttr.type = 3;
6905956Sgblack@eecs.umich.edu        dataAttr.writable = 1;
6915956Sgblack@eecs.umich.edu        dataAttr.readable = 1;
6925956Sgblack@eecs.umich.edu        dataAttr.expandDown = 0;
6936222Sgblack@eecs.umich.edu        dataAttr.system = 1;
6945956Sgblack@eecs.umich.edu
69511906SBrandon.Potter@amd.com        // Initialize the segment registers.
69611321Ssteve.reinhardt@amd.com        for (int seg = 0; seg < NUM_SEGMENTREGS; seg++) {
6975956Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(MISCREG_SEG_BASE(seg), 0);
6985956Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(MISCREG_SEG_EFF_BASE(seg), 0);
6995956Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(MISCREG_SEG_ATTR(seg), dataAttr);
7005956Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(MISCREG_SEG_SEL(seg), 0xB);
7015959Sgblack@eecs.umich.edu            tc->setMiscRegNoEffect(MISCREG_SEG_LIMIT(seg), (uint32_t)(-1));
7025956Sgblack@eecs.umich.edu        }
7035956Sgblack@eecs.umich.edu
7045956Sgblack@eecs.umich.edu        SegAttr csAttr = 0;
7056222Sgblack@eecs.umich.edu        csAttr.dpl = 3;
7066222Sgblack@eecs.umich.edu        csAttr.unusable = 0;
7076222Sgblack@eecs.umich.edu        csAttr.defaultSize = 1;
7086222Sgblack@eecs.umich.edu        csAttr.longMode = 0;
7096222Sgblack@eecs.umich.edu        csAttr.avl = 0;
7106222Sgblack@eecs.umich.edu        csAttr.granularity = 1;
7116222Sgblack@eecs.umich.edu        csAttr.present = 1;
7126222Sgblack@eecs.umich.edu        csAttr.type = 0xa;
7135956Sgblack@eecs.umich.edu        csAttr.writable = 0;
7145956Sgblack@eecs.umich.edu        csAttr.readable = 1;
7155956Sgblack@eecs.umich.edu        csAttr.expandDown = 0;
7166222Sgblack@eecs.umich.edu        csAttr.system = 1;
7175956Sgblack@eecs.umich.edu
7185956Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(MISCREG_CS_ATTR, csAttr);
7195956Sgblack@eecs.umich.edu
7205962Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(MISCREG_TSG_BASE, _gdtStart);
7215962Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(MISCREG_TSG_EFF_BASE, _gdtStart);
7225962Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(MISCREG_TSG_LIMIT, _gdtStart + _gdtSize - 1);
7235962Sgblack@eecs.umich.edu
7245963Sgblack@eecs.umich.edu        // Set the LDT selector to 0 to deactivate it.
7255963Sgblack@eecs.umich.edu        tc->setMiscRegNoEffect(MISCREG_TSL, 0);
7265963Sgblack@eecs.umich.edu
7276140Sgblack@eecs.umich.edu        Efer efer = 0;
7286140Sgblack@eecs.umich.edu        efer.sce = 1; // Enable system call extensions.
7296140Sgblack@eecs.umich.edu        efer.lme = 1; // Enable long mode.
7306140Sgblack@eecs.umich.edu        efer.lma = 0; // Deactivate long mode.
7316140Sgblack@eecs.umich.edu        efer.nxe = 1; // Enable nx support.
7326140Sgblack@eecs.umich.edu        efer.svme = 0; // Disable svm support for now. It isn't implemented.
7336140Sgblack@eecs.umich.edu        efer.ffxsr = 1; // Turn on fast fxsave and fxrstor.
7346140Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_EFER, efer);
7356140Sgblack@eecs.umich.edu
73611906SBrandon.Potter@amd.com        // Set up the registers that describe the operating mode.
7375956Sgblack@eecs.umich.edu        CR0 cr0 = 0;
7385956Sgblack@eecs.umich.edu        cr0.pg = 1; // Turn on paging.
7395956Sgblack@eecs.umich.edu        cr0.cd = 0; // Don't disable caching.
7405956Sgblack@eecs.umich.edu        cr0.nw = 0; // This is bit is defined to be ignored.
7415956Sgblack@eecs.umich.edu        cr0.am = 0; // No alignment checking
7425956Sgblack@eecs.umich.edu        cr0.wp = 0; // Supervisor mode can write read only pages
7435956Sgblack@eecs.umich.edu        cr0.ne = 1;
7445956Sgblack@eecs.umich.edu        cr0.et = 1; // This should always be 1
7455956Sgblack@eecs.umich.edu        cr0.ts = 0; // We don't do task switching, so causing fp exceptions
7465956Sgblack@eecs.umich.edu                    // would be pointless.
7475956Sgblack@eecs.umich.edu        cr0.em = 0; // Allow x87 instructions to execute natively.
7485956Sgblack@eecs.umich.edu        cr0.mp = 1; // This doesn't really matter, but the manual suggests
7495956Sgblack@eecs.umich.edu                    // setting it to one.
7505956Sgblack@eecs.umich.edu        cr0.pe = 1; // We're definitely in protected mode.
7515956Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_CR0, cr0);
7526609Sgblack@eecs.umich.edu
7536609Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_MXCSR, 0x1f80);
7545956Sgblack@eecs.umich.edu    }
7555956Sgblack@eecs.umich.edu}
7565956Sgblack@eecs.umich.edu
7575956Sgblack@eecs.umich.edutemplate<class IntType>
7585956Sgblack@eecs.umich.eduvoid
75911851Sbrandon.potter@amd.comX86Process::argsInit(int pageSize,
76011884Sbrandon.potter@amd.com                     std::vector<AuxVector<IntType> > extraAuxvs)
7615956Sgblack@eecs.umich.edu{
7625956Sgblack@eecs.umich.edu    int intSize = sizeof(IntType);
7635956Sgblack@eecs.umich.edu
76413894Sgabeblack@google.com    std::vector<AuxVector<IntType>> auxv = extraAuxvs;
7655758Shsul@eecs.umich.edu
7664166Sgblack@eecs.umich.edu    string filename;
76711321Ssteve.reinhardt@amd.com    if (argv.size() < 1)
7684166Sgblack@eecs.umich.edu        filename = "";
7694166Sgblack@eecs.umich.edu    else
7704166Sgblack@eecs.umich.edu        filename = argv[0];
7714166Sgblack@eecs.umich.edu
77211906SBrandon.Potter@amd.com    // We want 16 byte alignment
7734849Sgblack@eecs.umich.edu    uint64_t align = 16;
7744166Sgblack@eecs.umich.edu
77511389Sbrandon.potter@amd.com    // Patch the ld_bias for dynamic executables.
77611389Sbrandon.potter@amd.com    updateBias();
77711389Sbrandon.potter@amd.com
7784166Sgblack@eecs.umich.edu    // load object file into target memory
7794166Sgblack@eecs.umich.edu    objFile->loadSections(initVirtMem);
7804166Sgblack@eecs.umich.edu
7814793Sgblack@eecs.umich.edu    enum X86CpuFeature {
7824793Sgblack@eecs.umich.edu        X86_OnboardFPU = 1 << 0,
7834793Sgblack@eecs.umich.edu        X86_VirtualModeExtensions = 1 << 1,
7844793Sgblack@eecs.umich.edu        X86_DebuggingExtensions = 1 << 2,
7854793Sgblack@eecs.umich.edu        X86_PageSizeExtensions = 1 << 3,
7864777Sgblack@eecs.umich.edu
7874793Sgblack@eecs.umich.edu        X86_TimeStampCounter = 1 << 4,
7884793Sgblack@eecs.umich.edu        X86_ModelSpecificRegisters = 1 << 5,
7894793Sgblack@eecs.umich.edu        X86_PhysicalAddressExtensions = 1 << 6,
7904793Sgblack@eecs.umich.edu        X86_MachineCheckExtensions = 1 << 7,
7914777Sgblack@eecs.umich.edu
7924793Sgblack@eecs.umich.edu        X86_CMPXCHG8Instruction = 1 << 8,
7934793Sgblack@eecs.umich.edu        X86_OnboardAPIC = 1 << 9,
7944793Sgblack@eecs.umich.edu        X86_SYSENTER_SYSEXIT = 1 << 11,
7954793Sgblack@eecs.umich.edu
7964793Sgblack@eecs.umich.edu        X86_MemoryTypeRangeRegisters = 1 << 12,
7974793Sgblack@eecs.umich.edu        X86_PageGlobalEnable = 1 << 13,
7984793Sgblack@eecs.umich.edu        X86_MachineCheckArchitecture = 1 << 14,
7994793Sgblack@eecs.umich.edu        X86_CMOVInstruction = 1 << 15,
8004793Sgblack@eecs.umich.edu
8014793Sgblack@eecs.umich.edu        X86_PageAttributeTable = 1 << 16,
8024793Sgblack@eecs.umich.edu        X86_36BitPSEs = 1 << 17,
8034793Sgblack@eecs.umich.edu        X86_ProcessorSerialNumber = 1 << 18,
8044793Sgblack@eecs.umich.edu        X86_CLFLUSHInstruction = 1 << 19,
8054793Sgblack@eecs.umich.edu
8064793Sgblack@eecs.umich.edu        X86_DebugTraceStore = 1 << 21,
8074793Sgblack@eecs.umich.edu        X86_ACPIViaMSR = 1 << 22,
8084793Sgblack@eecs.umich.edu        X86_MultimediaExtensions = 1 << 23,
8094793Sgblack@eecs.umich.edu
8104793Sgblack@eecs.umich.edu        X86_FXSAVE_FXRSTOR = 1 << 24,
8114793Sgblack@eecs.umich.edu        X86_StreamingSIMDExtensions = 1 << 25,
8124793Sgblack@eecs.umich.edu        X86_StreamingSIMDExtensions2 = 1 << 26,
8134793Sgblack@eecs.umich.edu        X86_CPUSelfSnoop = 1 << 27,
8144793Sgblack@eecs.umich.edu
8154793Sgblack@eecs.umich.edu        X86_HyperThreading = 1 << 28,
8164793Sgblack@eecs.umich.edu        X86_AutomaticClockControl = 1 << 29,
8174793Sgblack@eecs.umich.edu        X86_IA64Processor = 1 << 30
8184166Sgblack@eecs.umich.edu    };
8194166Sgblack@eecs.umich.edu
82011389Sbrandon.potter@amd.com    // Setup the auxiliary vectors. These will already have endian
82111389Sbrandon.potter@amd.com    // conversion. Auxiliary vectors are loaded only for elf formatted
82211389Sbrandon.potter@amd.com    // executables; the auxv is responsible for passing information from
82311389Sbrandon.potter@amd.com    // the OS to the interpreter.
8244166Sgblack@eecs.umich.edu    ElfObject * elfObject = dynamic_cast<ElfObject *>(objFile);
82510590Sgabeblack@google.com    if (elfObject) {
8264793Sgblack@eecs.umich.edu        uint64_t features =
8274793Sgblack@eecs.umich.edu            X86_OnboardFPU |
8284793Sgblack@eecs.umich.edu            X86_VirtualModeExtensions |
8294793Sgblack@eecs.umich.edu            X86_DebuggingExtensions |
8304793Sgblack@eecs.umich.edu            X86_PageSizeExtensions |
8314793Sgblack@eecs.umich.edu            X86_TimeStampCounter |
8324793Sgblack@eecs.umich.edu            X86_ModelSpecificRegisters |
8334793Sgblack@eecs.umich.edu            X86_PhysicalAddressExtensions |
8344793Sgblack@eecs.umich.edu            X86_MachineCheckExtensions |
8354793Sgblack@eecs.umich.edu            X86_CMPXCHG8Instruction |
8364793Sgblack@eecs.umich.edu            X86_OnboardAPIC |
8374793Sgblack@eecs.umich.edu            X86_SYSENTER_SYSEXIT |
8384793Sgblack@eecs.umich.edu            X86_MemoryTypeRangeRegisters |
8394793Sgblack@eecs.umich.edu            X86_PageGlobalEnable |
8404793Sgblack@eecs.umich.edu            X86_MachineCheckArchitecture |
8414793Sgblack@eecs.umich.edu            X86_CMOVInstruction |
8424793Sgblack@eecs.umich.edu            X86_PageAttributeTable |
8434793Sgblack@eecs.umich.edu            X86_36BitPSEs |
8444793Sgblack@eecs.umich.edu//            X86_ProcessorSerialNumber |
8454793Sgblack@eecs.umich.edu            X86_CLFLUSHInstruction |
8464793Sgblack@eecs.umich.edu//            X86_DebugTraceStore |
8474793Sgblack@eecs.umich.edu//            X86_ACPIViaMSR |
8484793Sgblack@eecs.umich.edu            X86_MultimediaExtensions |
8494793Sgblack@eecs.umich.edu            X86_FXSAVE_FXRSTOR |
8504793Sgblack@eecs.umich.edu            X86_StreamingSIMDExtensions |
8514793Sgblack@eecs.umich.edu            X86_StreamingSIMDExtensions2 |
8524793Sgblack@eecs.umich.edu//            X86_CPUSelfSnoop |
8534793Sgblack@eecs.umich.edu//            X86_HyperThreading |
8544793Sgblack@eecs.umich.edu//            X86_AutomaticClockControl |
8554793Sgblack@eecs.umich.edu//            X86_IA64Processor |
8564793Sgblack@eecs.umich.edu            0;
8574793Sgblack@eecs.umich.edu
85811906SBrandon.Potter@amd.com        // Bits which describe the system hardware capabilities
85911906SBrandon.Potter@amd.com        // XXX Figure out what these should be
86013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_HWCAP, features);
86111906SBrandon.Potter@amd.com        // The system page size
86213894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PAGESZ, X86ISA::PageBytes);
86311906SBrandon.Potter@amd.com        // Frequency at which times() increments
86411906SBrandon.Potter@amd.com        // Defined to be 100 in the kernel source.
86513894Sgabeblack@google.com        auxv.emplace_back(M5_AT_CLKTCK, 100);
86611389Sbrandon.potter@amd.com        // This is the virtual address of the program header tables if they
86711389Sbrandon.potter@amd.com        // appear in the executable image.
86813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHDR, elfObject->programHeaderTable());
8694166Sgblack@eecs.umich.edu        // This is the size of a program header entry from the elf file.
87013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHENT, elfObject->programHeaderSize());
8714166Sgblack@eecs.umich.edu        // This is the number of program headers from the original elf file.
87213894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PHNUM, elfObject->programHeaderCount());
87311389Sbrandon.potter@amd.com        // This is the base address of the ELF interpreter; it should be
87411389Sbrandon.potter@amd.com        // zero for static executables or contain the base address for
87511389Sbrandon.potter@amd.com        // dynamic executables.
87613894Sgabeblack@google.com        auxv.emplace_back(M5_AT_BASE, getBias());
87711906SBrandon.Potter@amd.com        // XXX Figure out what this should be.
87813894Sgabeblack@google.com        auxv.emplace_back(M5_AT_FLAGS, 0);
87911906SBrandon.Potter@amd.com        // The entry point to the program
88013894Sgabeblack@google.com        auxv.emplace_back(M5_AT_ENTRY, objFile->entryPoint());
88111906SBrandon.Potter@amd.com        // Different user and group IDs
88213894Sgabeblack@google.com        auxv.emplace_back(M5_AT_UID, uid());
88313894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EUID, euid());
88413894Sgabeblack@google.com        auxv.emplace_back(M5_AT_GID, gid());
88513894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EGID, egid());
88611906SBrandon.Potter@amd.com        // Whether to enable "secure mode" in the executable
88713894Sgabeblack@google.com        auxv.emplace_back(M5_AT_SECURE, 0);
88811906SBrandon.Potter@amd.com        // The address of 16 "random" bytes.
88913894Sgabeblack@google.com        auxv.emplace_back(M5_AT_RANDOM, 0);
89011906SBrandon.Potter@amd.com        // The name of the program
89113894Sgabeblack@google.com        auxv.emplace_back(M5_AT_EXECFN, 0);
89211906SBrandon.Potter@amd.com        // The platform string
89313894Sgabeblack@google.com        auxv.emplace_back(M5_AT_PLATFORM, 0);
8944166Sgblack@eecs.umich.edu    }
8954166Sgblack@eecs.umich.edu
89611906SBrandon.Potter@amd.com    // Figure out how big the initial stack needs to be
8974166Sgblack@eecs.umich.edu
8984849Sgblack@eecs.umich.edu    // A sentry NULL void pointer at the top of the stack.
8994849Sgblack@eecs.umich.edu    int sentry_size = intSize;
9004166Sgblack@eecs.umich.edu
90111906SBrandon.Potter@amd.com    // This is the name of the file which is present on the initial stack
90211906SBrandon.Potter@amd.com    // It's purpose is to let the user space linker examine the original file.
9034847Sgblack@eecs.umich.edu    int file_name_size = filename.size() + 1;
9044793Sgblack@eecs.umich.edu
9057073Sgblack@eecs.umich.edu    const int numRandomBytes = 16;
9067073Sgblack@eecs.umich.edu    int aux_data_size = numRandomBytes;
9077073Sgblack@eecs.umich.edu
9084793Sgblack@eecs.umich.edu    string platform = "x86_64";
9097073Sgblack@eecs.umich.edu    aux_data_size += platform.size() + 1;
9104166Sgblack@eecs.umich.edu
9114166Sgblack@eecs.umich.edu    int env_data_size = 0;
91210590Sgabeblack@google.com    for (int i = 0; i < envp.size(); ++i)
9134847Sgblack@eecs.umich.edu        env_data_size += envp[i].size() + 1;
9144166Sgblack@eecs.umich.edu    int arg_data_size = 0;
91510590Sgabeblack@google.com    for (int i = 0; i < argv.size(); ++i)
9164847Sgblack@eecs.umich.edu        arg_data_size += argv[i].size() + 1;
9174166Sgblack@eecs.umich.edu
91811906SBrandon.Potter@amd.com    // The info_block needs to be padded so its size is a multiple of the
91911906SBrandon.Potter@amd.com    // alignment mask. Also, it appears that there needs to be at least some
92011906SBrandon.Potter@amd.com    // padding, so if the size is already a multiple, we need to increase it
92111906SBrandon.Potter@amd.com    // anyway.
9224849Sgblack@eecs.umich.edu    int base_info_block_size =
9234849Sgblack@eecs.umich.edu        sentry_size + file_name_size + env_data_size + arg_data_size;
9244166Sgblack@eecs.umich.edu
9254849Sgblack@eecs.umich.edu    int info_block_size = roundUp(base_info_block_size, align);
9264849Sgblack@eecs.umich.edu
9274849Sgblack@eecs.umich.edu    int info_block_padding = info_block_size - base_info_block_size;
9284166Sgblack@eecs.umich.edu
92911906SBrandon.Potter@amd.com    // Each auxiliary vector is two 8 byte words
9304166Sgblack@eecs.umich.edu    int aux_array_size = intSize * 2 * (auxv.size() + 1);
9314166Sgblack@eecs.umich.edu
9324166Sgblack@eecs.umich.edu    int envp_array_size = intSize * (envp.size() + 1);
9334166Sgblack@eecs.umich.edu    int argv_array_size = intSize * (argv.size() + 1);
9344166Sgblack@eecs.umich.edu
9354166Sgblack@eecs.umich.edu    int argc_size = intSize;
9364166Sgblack@eecs.umich.edu
93711906SBrandon.Potter@amd.com    // Figure out the size of the contents of the actual initial frame
9384849Sgblack@eecs.umich.edu    int frame_size =
9394166Sgblack@eecs.umich.edu        aux_array_size +
9404166Sgblack@eecs.umich.edu        envp_array_size +
9414166Sgblack@eecs.umich.edu        argv_array_size +
9424607Sgblack@eecs.umich.edu        argc_size;
9434166Sgblack@eecs.umich.edu
94411906SBrandon.Potter@amd.com    // There needs to be padding after the auxiliary vector data so that the
94511906SBrandon.Potter@amd.com    // very bottom of the stack is aligned properly.
9464849Sgblack@eecs.umich.edu    int partial_size = frame_size + aux_data_size;
9474849Sgblack@eecs.umich.edu    int aligned_partial_size = roundUp(partial_size, align);
9484849Sgblack@eecs.umich.edu    int aux_padding = aligned_partial_size - partial_size;
9494849Sgblack@eecs.umich.edu
9504849Sgblack@eecs.umich.edu    int space_needed =
9514849Sgblack@eecs.umich.edu        info_block_size +
9524849Sgblack@eecs.umich.edu        aux_data_size +
9534849Sgblack@eecs.umich.edu        aux_padding +
9544849Sgblack@eecs.umich.edu        frame_size;
9554849Sgblack@eecs.umich.edu
95611905SBrandon.Potter@amd.com    Addr stack_base = memState->getStackBase();
95711905SBrandon.Potter@amd.com
95811905SBrandon.Potter@amd.com    Addr stack_min = stack_base - space_needed;
95911905SBrandon.Potter@amd.com    stack_min = roundDown(stack_min, align);
96011905SBrandon.Potter@amd.com
96111905SBrandon.Potter@amd.com    unsigned stack_size = stack_base - stack_min;
96211905SBrandon.Potter@amd.com    stack_size = roundUp(stack_size, pageSize);
96311905SBrandon.Potter@amd.com    memState->setStackSize(stack_size);
9644166Sgblack@eecs.umich.edu
9654166Sgblack@eecs.umich.edu    // map memory
96611905SBrandon.Potter@amd.com    Addr stack_end = roundDown(stack_base - stack_size, pageSize);
96710554Salexandru.dutu@amd.com
96811905SBrandon.Potter@amd.com    DPRINTF(Stack, "Mapping the stack: 0x%x %dB\n", stack_end, stack_size);
96911905SBrandon.Potter@amd.com    allocateMem(stack_end, stack_size);
9704166Sgblack@eecs.umich.edu
9714166Sgblack@eecs.umich.edu    // map out initial stack contents
97211905SBrandon.Potter@amd.com    IntType sentry_base = stack_base - sentry_size;
9735956Sgblack@eecs.umich.edu    IntType file_name_base = sentry_base - file_name_size;
9745956Sgblack@eecs.umich.edu    IntType env_data_base = file_name_base - env_data_size;
9755956Sgblack@eecs.umich.edu    IntType arg_data_base = env_data_base - arg_data_size;
9765956Sgblack@eecs.umich.edu    IntType aux_data_base = arg_data_base - info_block_padding - aux_data_size;
9775956Sgblack@eecs.umich.edu    IntType auxv_array_base = aux_data_base - aux_array_size - aux_padding;
9785956Sgblack@eecs.umich.edu    IntType envp_array_base = auxv_array_base - envp_array_size;
9795956Sgblack@eecs.umich.edu    IntType argv_array_base = envp_array_base - argv_array_size;
9805956Sgblack@eecs.umich.edu    IntType argc_base = argv_array_base - argc_size;
9814166Sgblack@eecs.umich.edu
9825941Sgblack@eecs.umich.edu    DPRINTF(Stack, "The addresses of items on the initial stack:\n");
9835941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - file name\n", file_name_base);
9845941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - env data\n", env_data_base);
9855941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - arg data\n", arg_data_base);
9865941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - aux data\n", aux_data_base);
9875941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - auxv array\n", auxv_array_base);
9885941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - envp array\n", envp_array_base);
9895941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - argv array\n", argv_array_base);
9905941Sgblack@eecs.umich.edu    DPRINTF(Stack, "0x%x - argc \n", argc_base);
99111905SBrandon.Potter@amd.com    DPRINTF(Stack, "0x%x - stack min\n", stack_min);
9924166Sgblack@eecs.umich.edu
9934166Sgblack@eecs.umich.edu    // write contents to stack
9944166Sgblack@eecs.umich.edu
9954166Sgblack@eecs.umich.edu    // figure out argc
9965956Sgblack@eecs.umich.edu    IntType argc = argv.size();
9975956Sgblack@eecs.umich.edu    IntType guestArgc = X86ISA::htog(argc);
9984166Sgblack@eecs.umich.edu
99911906SBrandon.Potter@amd.com    // Write out the sentry void *
10005956Sgblack@eecs.umich.edu    IntType sentry_NULL = 0;
100114010Sgabeblack@google.com    initVirtMem.writeBlob(sentry_base, &sentry_NULL, sentry_size);
10024166Sgblack@eecs.umich.edu
100311906SBrandon.Potter@amd.com    // Write the file name
10048852Sandreas.hansson@arm.com    initVirtMem.writeString(file_name_base, filename.c_str());
10054166Sgblack@eecs.umich.edu
100611906SBrandon.Potter@amd.com    // Fix up the aux vectors which point to data
100713894Sgabeblack@google.com    assert(auxv[auxv.size() - 3].type == M5_AT_RANDOM);
100813894Sgabeblack@google.com    auxv[auxv.size() - 3].val = aux_data_base;
100913894Sgabeblack@google.com    assert(auxv[auxv.size() - 2].type == M5_AT_EXECFN);
101013894Sgabeblack@google.com    auxv[auxv.size() - 2].val = argv_array_base;
101113894Sgabeblack@google.com    assert(auxv[auxv.size() - 1].type == M5_AT_PLATFORM);
101213894Sgabeblack@google.com    auxv[auxv.size() - 1].val = aux_data_base + numRandomBytes;
10134793Sgblack@eecs.umich.edu
101411906SBrandon.Potter@amd.com
101511906SBrandon.Potter@amd.com    // Copy the aux stuff
101613894Sgabeblack@google.com    Addr auxv_array_end = auxv_array_base;
101713894Sgabeblack@google.com    for (const auto &aux: auxv) {
101813894Sgabeblack@google.com        initVirtMem.write(auxv_array_end, aux, GuestByteOrder);
101913894Sgabeblack@google.com        auxv_array_end += sizeof(aux);
10204166Sgblack@eecs.umich.edu    }
102111906SBrandon.Potter@amd.com    // Write out the terminating zeroed auxiliary vector
102213894Sgabeblack@google.com    const AuxVector<uint64_t> zero(0, 0);
102313894Sgabeblack@google.com    initVirtMem.write(auxv_array_end, zero);
102413894Sgabeblack@google.com    auxv_array_end += sizeof(zero);
10254166Sgblack@eecs.umich.edu
10268852Sandreas.hansson@arm.com    initVirtMem.writeString(aux_data_base, platform.c_str());
10274793Sgblack@eecs.umich.edu
10284166Sgblack@eecs.umich.edu    copyStringArray(envp, envp_array_base, env_data_base, initVirtMem);
10294166Sgblack@eecs.umich.edu    copyStringArray(argv, argv_array_base, arg_data_base, initVirtMem);
10304166Sgblack@eecs.umich.edu
103114010Sgabeblack@google.com    initVirtMem.writeBlob(argc_base, &guestArgc, intSize);
10324166Sgblack@eecs.umich.edu
10335713Shsul@eecs.umich.edu    ThreadContext *tc = system->getThreadContext(contextIds[0]);
103411906SBrandon.Potter@amd.com    // Set the stack pointer register
103511905SBrandon.Potter@amd.com    tc->setIntReg(StackPointerReg, stack_min);
10364166Sgblack@eecs.umich.edu
10375246Sgblack@eecs.umich.edu    // There doesn't need to be any segment base added in since we're dealing
10385246Sgblack@eecs.umich.edu    // with the flat segmentation model.
103911389Sbrandon.potter@amd.com    tc->pcState(getStartPC());
10404166Sgblack@eecs.umich.edu
104111906SBrandon.Potter@amd.com    // Align the "stack_min" to a page boundary.
104211905SBrandon.Potter@amd.com    memState->setStackMin(roundDown(stack_min, pageSize));
10434166Sgblack@eecs.umich.edu}
10445956Sgblack@eecs.umich.edu
10455956Sgblack@eecs.umich.eduvoid
104611884Sbrandon.potter@amd.comX86_64Process::argsInit(int pageSize)
10475956Sgblack@eecs.umich.edu{
10485973Sgblack@eecs.umich.edu    std::vector<AuxVector<uint64_t> > extraAuxvs;
104913894Sgabeblack@google.com    extraAuxvs.emplace_back(M5_AT_SYSINFO_EHDR, vsyscallPage.base);
105011851Sbrandon.potter@amd.com    X86Process::argsInit<uint64_t>(pageSize, extraAuxvs);
10515956Sgblack@eecs.umich.edu}
10525956Sgblack@eecs.umich.edu
10535956Sgblack@eecs.umich.eduvoid
105411884Sbrandon.potter@amd.comI386Process::argsInit(int pageSize)
10555956Sgblack@eecs.umich.edu{
10565973Sgblack@eecs.umich.edu    std::vector<AuxVector<uint32_t> > extraAuxvs;
10575973Sgblack@eecs.umich.edu    //Tell the binary where the vsyscall part of the vsyscall page is.
105813894Sgabeblack@google.com    extraAuxvs.emplace_back(M5_AT_SYSINFO,
105913894Sgabeblack@google.com            vsyscallPage.base + vsyscallPage.vsyscallOffset);
106013894Sgabeblack@google.com    extraAuxvs.emplace_back(M5_AT_SYSINFO_EHDR, vsyscallPage.base);
106111851Sbrandon.potter@amd.com    X86Process::argsInit<uint32_t>(pageSize, extraAuxvs);
10625956Sgblack@eecs.umich.edu}
10635958Sgblack@eecs.umich.edu
10645958Sgblack@eecs.umich.eduvoid
106511851Sbrandon.potter@amd.comX86Process::setSyscallReturn(ThreadContext *tc, SyscallReturn retval)
10665958Sgblack@eecs.umich.edu{
106710223Ssteve.reinhardt@amd.com    tc->setIntReg(INTREG_RAX, retval.encodedValue());
10685958Sgblack@eecs.umich.edu}
10695958Sgblack@eecs.umich.edu
107013613Sgabeblack@google.comRegVal
107111851Sbrandon.potter@amd.comX86_64Process::getSyscallArg(ThreadContext *tc, int &i)
10725958Sgblack@eecs.umich.edu{
10735958Sgblack@eecs.umich.edu    assert(i < NumArgumentRegs);
10746701Sgblack@eecs.umich.edu    return tc->readIntReg(ArgumentReg[i++]);
10755958Sgblack@eecs.umich.edu}
10765958Sgblack@eecs.umich.edu
10775958Sgblack@eecs.umich.eduvoid
107813613Sgabeblack@google.comX86_64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
10795958Sgblack@eecs.umich.edu{
10805958Sgblack@eecs.umich.edu    assert(i < NumArgumentRegs);
10815958Sgblack@eecs.umich.edu    return tc->setIntReg(ArgumentReg[i], val);
10825958Sgblack@eecs.umich.edu}
10835958Sgblack@eecs.umich.edu
108411886Sbrandon.potter@amd.comvoid
108511886Sbrandon.potter@amd.comX86_64Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
108613613Sgabeblack@google.com                     Process *p, RegVal flags)
108711886Sbrandon.potter@amd.com{
108811886Sbrandon.potter@amd.com    X86Process::clone(old_tc, new_tc, p, flags);
108911886Sbrandon.potter@amd.com    ((X86_64Process*)p)->vsyscallPage = vsyscallPage;
109011886Sbrandon.potter@amd.com}
109111886Sbrandon.potter@amd.com
109213613Sgabeblack@google.comRegVal
109311851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i)
10945958Sgblack@eecs.umich.edu{
10955959Sgblack@eecs.umich.edu    assert(i < NumArgumentRegs32);
10966701Sgblack@eecs.umich.edu    return tc->readIntReg(ArgumentReg32[i++]);
10976701Sgblack@eecs.umich.edu}
10986701Sgblack@eecs.umich.edu
109913613Sgabeblack@google.comRegVal
110011851Sbrandon.potter@amd.comI386Process::getSyscallArg(ThreadContext *tc, int &i, int width)
11016701Sgblack@eecs.umich.edu{
11026701Sgblack@eecs.umich.edu    assert(width == 32 || width == 64);
11036701Sgblack@eecs.umich.edu    assert(i < NumArgumentRegs);
11046701Sgblack@eecs.umich.edu    uint64_t retVal = tc->readIntReg(ArgumentReg32[i++]) & mask(32);
11056701Sgblack@eecs.umich.edu    if (width == 64)
11066701Sgblack@eecs.umich.edu        retVal |= ((uint64_t)tc->readIntReg(ArgumentReg[i++]) << 32);
11076701Sgblack@eecs.umich.edu    return retVal;
11085958Sgblack@eecs.umich.edu}
11095958Sgblack@eecs.umich.edu
11105958Sgblack@eecs.umich.eduvoid
111113613Sgabeblack@google.comI386Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
11125958Sgblack@eecs.umich.edu{
11135959Sgblack@eecs.umich.edu    assert(i < NumArgumentRegs);
11145959Sgblack@eecs.umich.edu    return tc->setIntReg(ArgumentReg[i], val);
11155958Sgblack@eecs.umich.edu}
111611886Sbrandon.potter@amd.com
111711886Sbrandon.potter@amd.comvoid
111811886Sbrandon.potter@amd.comI386Process::clone(ThreadContext *old_tc, ThreadContext *new_tc,
111913613Sgabeblack@google.com                   Process *p, RegVal flags)
112011886Sbrandon.potter@amd.com{
112111886Sbrandon.potter@amd.com    X86Process::clone(old_tc, new_tc, p, flags);
112211886Sbrandon.potter@amd.com    ((I386Process*)p)->vsyscallPage = vsyscallPage;
112311886Sbrandon.potter@amd.com}
1124