1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "dev/x86/i82094aa.hh"
32
33#include "arch/x86/interrupts.hh"
34#include "arch/x86/intmessage.hh"
35#include "cpu/base.hh"
36#include "debug/I82094AA.hh"
37#include "dev/x86/i8259.hh"
38#include "mem/packet.hh"
39#include "mem/packet_access.hh"
40#include "sim/system.hh"
41
42X86ISA::I82094AA::I82094AA(Params *p)
43    : BasicPioDevice(p, 20), IntDevice(this, p->int_latency),
44      extIntPic(p->external_int_pic), lowestPriorityOffset(0)
45{
46    // This assumes there's only one I/O APIC in the system and since the apic
47    // id is stored in a 8-bit field with 0xff meaning broadcast, the id must
48    // be less than 0xff
49
50    assert(p->apic_id < 0xff);
51    initialApicId = id = p->apic_id;
52    arbId = id;
53    regSel = 0;
54    RedirTableEntry entry = 0;
55    entry.mask = 1;
56    for (int i = 0; i < TableSize; i++) {
57        redirTable[i] = entry;
58        pinStates[i] = false;
59    }
60
61    for (int i = 0; i < p->port_inputs_connection_count; i++)
62        inputs.push_back(new IntSinkPin<I82094AA>(
63                    csprintf("%s.inputs[%d]", name(), i), i, this));
64}
65
66void
67X86ISA::I82094AA::init()
68{
69    // The io apic must register its address ranges on both its pio port
70    // via the piodevice init() function and its int port that it inherited
71    // from IntDevice.  Note IntDevice is not a SimObject itself.
72
73    BasicPioDevice::init();
74    IntDevice::init();
75}
76
77Port &
78X86ISA::I82094AA::getPort(const std::string &if_name, PortID idx)
79{
80    if (if_name == "int_master")
81        return intMasterPort;
82    if (if_name == "inputs")
83        return *inputs.at(idx);
84    else
85        return BasicPioDevice::getPort(if_name, idx);
86}
87
88bool
89X86ISA::I82094AA::recvResponse(PacketPtr pkt)
90{
91    // Packet instantiated calling sendMessage() in signalInterrupt()
92    delete pkt;
93    return true;
94}
95
96Tick
97X86ISA::I82094AA::read(PacketPtr pkt)
98{
99    assert(pkt->getSize() == 4);
100    Addr offset = pkt->getAddr() - pioAddr;
101    switch(offset) {
102      case 0:
103        pkt->setLE<uint32_t>(regSel);
104        break;
105      case 16:
106        pkt->setLE<uint32_t>(readReg(regSel));
107        break;
108      default:
109        panic("Illegal read from I/O APIC.\n");
110    }
111    pkt->makeAtomicResponse();
112    return pioDelay;
113}
114
115Tick
116X86ISA::I82094AA::write(PacketPtr pkt)
117{
118    assert(pkt->getSize() == 4);
119    Addr offset = pkt->getAddr() - pioAddr;
120    switch(offset) {
121      case 0:
122        regSel = pkt->getLE<uint32_t>();
123        break;
124      case 16:
125        writeReg(regSel, pkt->getLE<uint32_t>());
126        break;
127      default:
128        panic("Illegal write to I/O APIC.\n");
129    }
130    pkt->makeAtomicResponse();
131    return pioDelay;
132}
133
134void
135X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value)
136{
137    if (offset == 0x0) {
138        id = bits(value, 31, 24);
139    } else if (offset == 0x1) {
140        // The IOAPICVER register is read only.
141    } else if (offset == 0x2) {
142        arbId = bits(value, 31, 24);
143    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
144        int index = (offset - 0x10) / 2;
145        if (offset % 2) {
146            redirTable[index].topDW = value;
147            redirTable[index].topReserved = 0;
148        } else {
149            redirTable[index].bottomDW = value;
150            redirTable[index].bottomReserved = 0;
151        }
152    } else {
153        warn("Access to undefined I/O APIC register %#x.\n", offset);
154    }
155    DPRINTF(I82094AA,
156            "Wrote %#x to I/O APIC register %#x .\n", value, offset);
157}
158
159uint32_t
160X86ISA::I82094AA::readReg(uint8_t offset)
161{
162    uint32_t result = 0;
163    if (offset == 0x0) {
164        result = id << 24;
165    } else if (offset == 0x1) {
166        result = ((TableSize - 1) << 16) | APICVersion;
167    } else if (offset == 0x2) {
168        result = arbId << 24;
169    } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) {
170        int index = (offset - 0x10) / 2;
171        if (offset % 2) {
172            result = redirTable[index].topDW;
173        } else {
174            result = redirTable[index].bottomDW;
175        }
176    } else {
177        warn("Access to undefined I/O APIC register %#x.\n", offset);
178    }
179    DPRINTF(I82094AA,
180            "Read %#x from I/O APIC register %#x.\n", result, offset);
181    return result;
182}
183
184void
185X86ISA::I82094AA::signalInterrupt(int line)
186{
187    DPRINTF(I82094AA, "Received interrupt %d.\n", line);
188    assert(line < TableSize);
189    RedirTableEntry entry = redirTable[line];
190    if (entry.mask) {
191        DPRINTF(I82094AA, "Entry was masked.\n");
192        return;
193    } else {
194        TriggerIntMessage message = 0;
195        message.destination = entry.dest;
196        if (entry.deliveryMode == DeliveryMode::ExtInt) {
197            assert(extIntPic);
198            message.vector = extIntPic->getVector();
199        } else {
200            message.vector = entry.vector;
201        }
202        message.deliveryMode = entry.deliveryMode;
203        message.destMode = entry.destMode;
204        message.level = entry.polarity;
205        message.trigger = entry.trigger;
206        ApicList apics;
207        int numContexts = sys->numContexts();
208        if (message.destMode == 0) {
209            if (message.deliveryMode == DeliveryMode::LowestPriority) {
210                panic("Lowest priority delivery mode from the "
211                        "IO APIC aren't supported in physical "
212                        "destination mode.\n");
213            }
214            if (message.destination == 0xFF) {
215                for (int i = 0; i < numContexts; i++) {
216                    apics.push_back(i);
217                }
218            } else {
219                apics.push_back(message.destination);
220            }
221        } else {
222            for (int i = 0; i < numContexts; i++) {
223                Interrupts *localApic = sys->getThreadContext(i)->
224                    getCpuPtr()->getInterruptController(0);
225                if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) &
226                        message.destination) {
227                    apics.push_back(localApic->getInitialApicId());
228                }
229            }
230            if (message.deliveryMode == DeliveryMode::LowestPriority &&
231                    apics.size()) {
232                // The manual seems to suggest that the chipset just does
233                // something reasonable for these instead of actually using
234                // state from the local APIC. We'll just rotate an offset
235                // through the set of APICs selected above.
236                uint64_t modOffset = lowestPriorityOffset % apics.size();
237                lowestPriorityOffset++;
238                ApicList::iterator apicIt = apics.begin();
239                while (modOffset--) {
240                    apicIt++;
241                    assert(apicIt != apics.end());
242                }
243                int selected = *apicIt;
244                apics.clear();
245                apics.push_back(selected);
246            }
247        }
248        intMasterPort.sendMessage(apics, message, sys->isTimingMode());
249    }
250}
251
252void
253X86ISA::I82094AA::raiseInterruptPin(int number)
254{
255    assert(number < TableSize);
256    if (!pinStates[number])
257        signalInterrupt(number);
258    pinStates[number] = true;
259}
260
261void
262X86ISA::I82094AA::lowerInterruptPin(int number)
263{
264    assert(number < TableSize);
265    pinStates[number] = false;
266}
267
268void
269X86ISA::I82094AA::serialize(CheckpointOut &cp) const
270{
271    uint64_t* redirTableArray = (uint64_t*)redirTable;
272    SERIALIZE_SCALAR(regSel);
273    SERIALIZE_SCALAR(initialApicId);
274    SERIALIZE_SCALAR(id);
275    SERIALIZE_SCALAR(arbId);
276    SERIALIZE_SCALAR(lowestPriorityOffset);
277    SERIALIZE_ARRAY(redirTableArray, TableSize);
278    SERIALIZE_ARRAY(pinStates, TableSize);
279}
280
281void
282X86ISA::I82094AA::unserialize(CheckpointIn &cp)
283{
284    uint64_t redirTableArray[TableSize];
285    UNSERIALIZE_SCALAR(regSel);
286    UNSERIALIZE_SCALAR(initialApicId);
287    UNSERIALIZE_SCALAR(id);
288    UNSERIALIZE_SCALAR(arbId);
289    UNSERIALIZE_SCALAR(lowestPriorityOffset);
290    UNSERIALIZE_ARRAY(redirTableArray, TableSize);
291    UNSERIALIZE_ARRAY(pinStates, TableSize);
292    for (int i = 0; i < TableSize; i++) {
293        redirTable[i] = (RedirTableEntry)redirTableArray[i];
294    }
295}
296
297X86ISA::I82094AA *
298I82094AAParams::create()
299{
300    return new X86ISA::I82094AA(this);
301}
302