16019Shines@cs.fsu.edu/* 212763Sgiacomo.travaglini@arm.com * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited 37097Sgblack@eecs.umich.edu * All rights reserved 47097Sgblack@eecs.umich.edu * 57097Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67097Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77097Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87097Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97097Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107097Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117097Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127097Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137097Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 156019Shines@cs.fsu.edu * All rights reserved. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 186019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 196019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 206019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 216019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 226019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 236019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 246019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 256019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 266019Shines@cs.fsu.edu * this software without specific prior written permission. 276019Shines@cs.fsu.edu * 286019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396019Shines@cs.fsu.edu * 406019Shines@cs.fsu.edu * Authors: Stephen Hines 416019Shines@cs.fsu.edu */ 426019Shines@cs.fsu.edu 436019Shines@cs.fsu.edu#ifndef __ARCH_ARM_TYPES_HH__ 446019Shines@cs.fsu.edu#define __ARCH_ARM_TYPES_HH__ 456019Shines@cs.fsu.edu 467720Sgblack@eecs.umich.edu#include "arch/generic/types.hh" 476251Sgblack@eecs.umich.edu#include "base/bitunion.hh" 4812334Sgabeblack@google.com#include "base/logging.hh" 496214Snate@binkert.org#include "base/types.hh" 509023Sgblack@eecs.umich.edu#include "debug/Decoder.hh" 516019Shines@cs.fsu.edu 526019Shines@cs.fsu.edunamespace ArmISA 536019Shines@cs.fsu.edu{ 546019Shines@cs.fsu.edu typedef uint32_t MachInst; 556251Sgblack@eecs.umich.edu 568205SAli.Saidi@ARM.com BitUnion8(ITSTATE) 578205SAli.Saidi@ARM.com /* Note that the split (cond, mask) below is not as in ARM ARM. 588205SAli.Saidi@ARM.com * But it is more convenient for simulation. The condition 598205SAli.Saidi@ARM.com * is always the concatenation of the top 3 bits and the next bit, 608205SAli.Saidi@ARM.com * which applies when one of the bottom 4 bits is set. 618205SAli.Saidi@ARM.com * Refer to predecoder.cc for the use case. 628205SAli.Saidi@ARM.com */ 638205SAli.Saidi@ARM.com Bitfield<7, 4> cond; 648205SAli.Saidi@ARM.com Bitfield<3, 0> mask; 658205SAli.Saidi@ARM.com // Bitfields for moving to/from CPSR 668205SAli.Saidi@ARM.com Bitfield<7, 2> top6; 678205SAli.Saidi@ARM.com Bitfield<1, 0> bottom2; 688205SAli.Saidi@ARM.com EndBitUnion(ITSTATE) 698205SAli.Saidi@ARM.com 7010611SAndreas.Sandberg@ARM.com BitUnion64(ExtMachInst) 7110611SAndreas.Sandberg@ARM.com // Decoder state 7210611SAndreas.Sandberg@ARM.com Bitfield<63, 62> decoderFault; // See DecoderFault 7312763Sgiacomo.travaglini@arm.com Bitfield<61> illegalExecution; 748205SAli.Saidi@ARM.com 7513759Sgiacomo.gabrielli@arm.com // SVE vector length, encoded in the same format as the ZCR_EL<x>.LEN 7613759Sgiacomo.gabrielli@arm.com // bitfields 7713759Sgiacomo.gabrielli@arm.com Bitfield<59, 56> sveLen; 7813759Sgiacomo.gabrielli@arm.com 797408Sgblack@eecs.umich.edu // ITSTATE bits 807408Sgblack@eecs.umich.edu Bitfield<55, 48> itstate; 817408Sgblack@eecs.umich.edu Bitfield<55, 52> itstateCond; 827408Sgblack@eecs.umich.edu Bitfield<51, 48> itstateMask; 837408Sgblack@eecs.umich.edu 847376Sgblack@eecs.umich.edu // FPSCR fields 857376Sgblack@eecs.umich.edu Bitfield<41, 40> fpscrStride; 867376Sgblack@eecs.umich.edu Bitfield<39, 37> fpscrLen; 877376Sgblack@eecs.umich.edu 887097Sgblack@eecs.umich.edu // Bitfields to select mode. 897097Sgblack@eecs.umich.edu Bitfield<36> thumb; 907097Sgblack@eecs.umich.edu Bitfield<35> bigThumb; 9110037SARM gem5 Developers Bitfield<34> aarch64; 927097Sgblack@eecs.umich.edu 936267Sgblack@eecs.umich.edu // Made up bitfields that make life easier. 946267Sgblack@eecs.umich.edu Bitfield<33> sevenAndFour; 956267Sgblack@eecs.umich.edu Bitfield<32> isMisc; 966267Sgblack@eecs.umich.edu 977098Sgblack@eecs.umich.edu uint32_t instBits; 987098Sgblack@eecs.umich.edu 996251Sgblack@eecs.umich.edu // All the different types of opcode fields. 1006268Sgblack@eecs.umich.edu Bitfield<27, 25> encoding; 1016749Sgblack@eecs.umich.edu Bitfield<25> useImm; 1026268Sgblack@eecs.umich.edu Bitfield<24, 21> opcode; 1036269Sgblack@eecs.umich.edu Bitfield<24, 20> mediaOpcode; 1046251Sgblack@eecs.umich.edu Bitfield<24> opcode24; 1057161Sgblack@eecs.umich.edu Bitfield<24, 23> opcode24_23; 1066251Sgblack@eecs.umich.edu Bitfield<23, 20> opcode23_20; 1076251Sgblack@eecs.umich.edu Bitfield<23, 21> opcode23_21; 1086743Ssaidi@eecs.umich.edu Bitfield<20> opcode20; 1096251Sgblack@eecs.umich.edu Bitfield<22> opcode22; 1107105Sgblack@eecs.umich.edu Bitfield<19, 16> opcode19_16; 1116251Sgblack@eecs.umich.edu Bitfield<19> opcode19; 1126741Sgblack@eecs.umich.edu Bitfield<18> opcode18; 1136251Sgblack@eecs.umich.edu Bitfield<15, 12> opcode15_12; 1146251Sgblack@eecs.umich.edu Bitfield<15> opcode15; 1156268Sgblack@eecs.umich.edu Bitfield<7, 4> miscOpcode; 1166759SAli.Saidi@ARM.com Bitfield<7,5> opc2; 1176251Sgblack@eecs.umich.edu Bitfield<7> opcode7; 1187105Sgblack@eecs.umich.edu Bitfield<6> opcode6; 1196251Sgblack@eecs.umich.edu Bitfield<4> opcode4; 1206251Sgblack@eecs.umich.edu 1216251Sgblack@eecs.umich.edu Bitfield<31, 28> condCode; 1226251Sgblack@eecs.umich.edu Bitfield<20> sField; 1236251Sgblack@eecs.umich.edu Bitfield<19, 16> rn; 1246251Sgblack@eecs.umich.edu Bitfield<15, 12> rd; 1257121Sgblack@eecs.umich.edu Bitfield<15, 12> rt; 1266251Sgblack@eecs.umich.edu Bitfield<11, 7> shiftSize; 1276251Sgblack@eecs.umich.edu Bitfield<6, 5> shift; 1286251Sgblack@eecs.umich.edu Bitfield<3, 0> rm; 1296251Sgblack@eecs.umich.edu 1306251Sgblack@eecs.umich.edu Bitfield<11, 8> rs; 1316251Sgblack@eecs.umich.edu 1326251Sgblack@eecs.umich.edu SubBitUnion(puswl, 24, 20) 1336251Sgblack@eecs.umich.edu Bitfield<24> prepost; 1346251Sgblack@eecs.umich.edu Bitfield<23> up; 1356251Sgblack@eecs.umich.edu Bitfield<22> psruser; 1366251Sgblack@eecs.umich.edu Bitfield<21> writeback; 1376251Sgblack@eecs.umich.edu Bitfield<20> loadOp; 1386251Sgblack@eecs.umich.edu EndSubBitUnion(puswl) 1396251Sgblack@eecs.umich.edu 1406251Sgblack@eecs.umich.edu Bitfield<24, 20> pubwl; 1416251Sgblack@eecs.umich.edu 1426275Sgblack@eecs.umich.edu Bitfield<7, 0> imm; 1436251Sgblack@eecs.umich.edu 1446251Sgblack@eecs.umich.edu Bitfield<11, 8> rotate; 1456275Sgblack@eecs.umich.edu 1466275Sgblack@eecs.umich.edu Bitfield<11, 0> immed11_0; 1476251Sgblack@eecs.umich.edu Bitfield<7, 0> immed7_0; 1486251Sgblack@eecs.umich.edu 1496251Sgblack@eecs.umich.edu Bitfield<11, 8> immedHi11_8; 1506251Sgblack@eecs.umich.edu Bitfield<3, 0> immedLo3_0; 1516251Sgblack@eecs.umich.edu 1526251Sgblack@eecs.umich.edu Bitfield<15, 0> regList; 15310037SARM gem5 Developers 1546251Sgblack@eecs.umich.edu Bitfield<23, 0> offset; 15510037SARM gem5 Developers 1566251Sgblack@eecs.umich.edu Bitfield<23, 0> immed23_0; 1576251Sgblack@eecs.umich.edu 1586251Sgblack@eecs.umich.edu Bitfield<11, 8> cpNum; 1596251Sgblack@eecs.umich.edu Bitfield<18, 16> fn; 1606251Sgblack@eecs.umich.edu Bitfield<14, 12> fd; 1616251Sgblack@eecs.umich.edu Bitfield<3> fpRegImm; 1626251Sgblack@eecs.umich.edu Bitfield<3, 0> fm; 1636251Sgblack@eecs.umich.edu Bitfield<2, 0> fpImm; 1646251Sgblack@eecs.umich.edu Bitfield<24, 20> punwl; 1656251Sgblack@eecs.umich.edu 1667732SAli.Saidi@ARM.com Bitfield<15, 8> m5Func; 1677103Sgblack@eecs.umich.edu 1687103Sgblack@eecs.umich.edu // 16 bit thumb bitfields 1697103Sgblack@eecs.umich.edu Bitfield<15, 13> topcode15_13; 1707103Sgblack@eecs.umich.edu Bitfield<13, 11> topcode13_11; 1717103Sgblack@eecs.umich.edu Bitfield<12, 11> topcode12_11; 1727103Sgblack@eecs.umich.edu Bitfield<12, 10> topcode12_10; 1737103Sgblack@eecs.umich.edu Bitfield<11, 9> topcode11_9; 1747103Sgblack@eecs.umich.edu Bitfield<11, 8> topcode11_8; 1757103Sgblack@eecs.umich.edu Bitfield<10, 9> topcode10_9; 1767103Sgblack@eecs.umich.edu Bitfield<10, 8> topcode10_8; 1777103Sgblack@eecs.umich.edu Bitfield<9, 6> topcode9_6; 1787103Sgblack@eecs.umich.edu Bitfield<7> topcode7; 1797103Sgblack@eecs.umich.edu Bitfield<7, 6> topcode7_6; 1807103Sgblack@eecs.umich.edu Bitfield<7, 5> topcode7_5; 1817103Sgblack@eecs.umich.edu Bitfield<7, 4> topcode7_4; 1827103Sgblack@eecs.umich.edu Bitfield<3, 0> topcode3_0; 1837106Sgblack@eecs.umich.edu 1847106Sgblack@eecs.umich.edu // 32 bit thumb bitfields 1857106Sgblack@eecs.umich.edu Bitfield<28, 27> htopcode12_11; 1867106Sgblack@eecs.umich.edu Bitfield<26, 25> htopcode10_9; 1877106Sgblack@eecs.umich.edu Bitfield<25> htopcode9; 1887106Sgblack@eecs.umich.edu Bitfield<25, 24> htopcode9_8; 1897106Sgblack@eecs.umich.edu Bitfield<25, 21> htopcode9_5; 1907106Sgblack@eecs.umich.edu Bitfield<25, 20> htopcode9_4; 1917106Sgblack@eecs.umich.edu Bitfield<24> htopcode8; 1927106Sgblack@eecs.umich.edu Bitfield<24, 23> htopcode8_7; 1937106Sgblack@eecs.umich.edu Bitfield<24, 22> htopcode8_6; 1947106Sgblack@eecs.umich.edu Bitfield<24, 21> htopcode8_5; 1957113Sgblack@eecs.umich.edu Bitfield<23> htopcode7; 1967116Sgblack@eecs.umich.edu Bitfield<23, 21> htopcode7_5; 1977245Sgblack@eecs.umich.edu Bitfield<22> htopcode6; 1987106Sgblack@eecs.umich.edu Bitfield<22, 21> htopcode6_5; 1997106Sgblack@eecs.umich.edu Bitfield<21, 20> htopcode5_4; 2007106Sgblack@eecs.umich.edu Bitfield<20> htopcode4; 2017106Sgblack@eecs.umich.edu 2027106Sgblack@eecs.umich.edu Bitfield<19, 16> htrn; 2037106Sgblack@eecs.umich.edu Bitfield<20> hts; 2047106Sgblack@eecs.umich.edu 2057106Sgblack@eecs.umich.edu Bitfield<15> ltopcode15; 2067113Sgblack@eecs.umich.edu Bitfield<11, 8> ltopcode11_8; 2077113Sgblack@eecs.umich.edu Bitfield<7, 6> ltopcode7_6; 2087106Sgblack@eecs.umich.edu Bitfield<7, 4> ltopcode7_4; 2097106Sgblack@eecs.umich.edu Bitfield<4> ltopcode4; 2107106Sgblack@eecs.umich.edu 2117106Sgblack@eecs.umich.edu Bitfield<11, 8> ltrd; 2127106Sgblack@eecs.umich.edu Bitfield<11, 8> ltcoproc; 2136251Sgblack@eecs.umich.edu EndBitUnion(ExtMachInst) 2146251Sgblack@eecs.umich.edu 2157720Sgblack@eecs.umich.edu class PCState : public GenericISA::UPCState<MachInst> 2167720Sgblack@eecs.umich.edu { 2177720Sgblack@eecs.umich.edu protected: 2187720Sgblack@eecs.umich.edu 2197720Sgblack@eecs.umich.edu typedef GenericISA::UPCState<MachInst> Base; 2207720Sgblack@eecs.umich.edu 2217720Sgblack@eecs.umich.edu enum FlagBits { 2227720Sgblack@eecs.umich.edu ThumbBit = (1 << 0), 22310037SARM gem5 Developers JazelleBit = (1 << 1), 22410037SARM gem5 Developers AArch64Bit = (1 << 2) 2257720Sgblack@eecs.umich.edu }; 22612763Sgiacomo.travaglini@arm.com 2277720Sgblack@eecs.umich.edu uint8_t flags; 2287720Sgblack@eecs.umich.edu uint8_t nextFlags; 2298205SAli.Saidi@ARM.com uint8_t _itstate; 2308205SAli.Saidi@ARM.com uint8_t _nextItstate; 2318146SAli.Saidi@ARM.com uint8_t _size; 23212763Sgiacomo.travaglini@arm.com bool _illegalExec; 2337720Sgblack@eecs.umich.edu public: 23410537Sandreas.hansson@arm.com PCState() : flags(0), nextFlags(0), _itstate(0), _nextItstate(0), 23512763Sgiacomo.travaglini@arm.com _size(0), _illegalExec(false) 2367720Sgblack@eecs.umich.edu {} 2377720Sgblack@eecs.umich.edu 2387720Sgblack@eecs.umich.edu void 2397720Sgblack@eecs.umich.edu set(Addr val) 2407720Sgblack@eecs.umich.edu { 2417720Sgblack@eecs.umich.edu Base::set(val); 2427720Sgblack@eecs.umich.edu npc(val + (thumb() ? 2 : 4)); 2437720Sgblack@eecs.umich.edu } 2447720Sgblack@eecs.umich.edu 24510537Sandreas.hansson@arm.com PCState(Addr val) : flags(0), nextFlags(0), _itstate(0), 24612763Sgiacomo.travaglini@arm.com _nextItstate(0), _size(0), _illegalExec(false) 2477720Sgblack@eecs.umich.edu { set(val); } 2487720Sgblack@eecs.umich.edu 2497720Sgblack@eecs.umich.edu bool 25012763Sgiacomo.travaglini@arm.com illegalExec() const 25112763Sgiacomo.travaglini@arm.com { 25212763Sgiacomo.travaglini@arm.com return _illegalExec; 25312763Sgiacomo.travaglini@arm.com } 25412763Sgiacomo.travaglini@arm.com 25512763Sgiacomo.travaglini@arm.com void 25612763Sgiacomo.travaglini@arm.com illegalExec(bool val) 25712763Sgiacomo.travaglini@arm.com { 25812763Sgiacomo.travaglini@arm.com _illegalExec = val; 25912763Sgiacomo.travaglini@arm.com } 26012763Sgiacomo.travaglini@arm.com 26112763Sgiacomo.travaglini@arm.com bool 2627720Sgblack@eecs.umich.edu thumb() const 2637720Sgblack@eecs.umich.edu { 2647720Sgblack@eecs.umich.edu return flags & ThumbBit; 2657720Sgblack@eecs.umich.edu } 2667720Sgblack@eecs.umich.edu 2677720Sgblack@eecs.umich.edu void 2687720Sgblack@eecs.umich.edu thumb(bool val) 2697720Sgblack@eecs.umich.edu { 2707720Sgblack@eecs.umich.edu if (val) 2717720Sgblack@eecs.umich.edu flags |= ThumbBit; 2727720Sgblack@eecs.umich.edu else 2737720Sgblack@eecs.umich.edu flags &= ~ThumbBit; 2747720Sgblack@eecs.umich.edu } 2757720Sgblack@eecs.umich.edu 2767720Sgblack@eecs.umich.edu bool 2777720Sgblack@eecs.umich.edu nextThumb() const 2787720Sgblack@eecs.umich.edu { 2797720Sgblack@eecs.umich.edu return nextFlags & ThumbBit; 2807720Sgblack@eecs.umich.edu } 2817720Sgblack@eecs.umich.edu 2827720Sgblack@eecs.umich.edu void 2837720Sgblack@eecs.umich.edu nextThumb(bool val) 2847720Sgblack@eecs.umich.edu { 2857720Sgblack@eecs.umich.edu if (val) 2867720Sgblack@eecs.umich.edu nextFlags |= ThumbBit; 2877720Sgblack@eecs.umich.edu else 2887720Sgblack@eecs.umich.edu nextFlags &= ~ThumbBit; 2897720Sgblack@eecs.umich.edu } 2907720Sgblack@eecs.umich.edu 2918146SAli.Saidi@ARM.com void size(uint8_t s) { _size = s; } 2928146SAli.Saidi@ARM.com uint8_t size() const { return _size; } 2938146SAli.Saidi@ARM.com 2948146SAli.Saidi@ARM.com bool 2958146SAli.Saidi@ARM.com branching() const 2968146SAli.Saidi@ARM.com { 2978146SAli.Saidi@ARM.com return ((this->pc() + this->size()) != this->npc()); 2988146SAli.Saidi@ARM.com } 2998146SAli.Saidi@ARM.com 3008146SAli.Saidi@ARM.com 3017720Sgblack@eecs.umich.edu bool 3027720Sgblack@eecs.umich.edu jazelle() const 3037720Sgblack@eecs.umich.edu { 3047720Sgblack@eecs.umich.edu return flags & JazelleBit; 3057720Sgblack@eecs.umich.edu } 3067720Sgblack@eecs.umich.edu 3077720Sgblack@eecs.umich.edu void 3087720Sgblack@eecs.umich.edu jazelle(bool val) 3097720Sgblack@eecs.umich.edu { 3107720Sgblack@eecs.umich.edu if (val) 3117720Sgblack@eecs.umich.edu flags |= JazelleBit; 3127720Sgblack@eecs.umich.edu else 3137720Sgblack@eecs.umich.edu flags &= ~JazelleBit; 3147720Sgblack@eecs.umich.edu } 3157720Sgblack@eecs.umich.edu 3167720Sgblack@eecs.umich.edu bool 3177720Sgblack@eecs.umich.edu nextJazelle() const 3187720Sgblack@eecs.umich.edu { 3197720Sgblack@eecs.umich.edu return nextFlags & JazelleBit; 3207720Sgblack@eecs.umich.edu } 3217720Sgblack@eecs.umich.edu 3227720Sgblack@eecs.umich.edu void 3237720Sgblack@eecs.umich.edu nextJazelle(bool val) 3247720Sgblack@eecs.umich.edu { 3257720Sgblack@eecs.umich.edu if (val) 3267720Sgblack@eecs.umich.edu nextFlags |= JazelleBit; 3277720Sgblack@eecs.umich.edu else 3287720Sgblack@eecs.umich.edu nextFlags &= ~JazelleBit; 3297720Sgblack@eecs.umich.edu } 3307720Sgblack@eecs.umich.edu 33110037SARM gem5 Developers bool 33210037SARM gem5 Developers aarch64() const 33310037SARM gem5 Developers { 33410037SARM gem5 Developers return flags & AArch64Bit; 33510037SARM gem5 Developers } 33610037SARM gem5 Developers 33710037SARM gem5 Developers void 33810037SARM gem5 Developers aarch64(bool val) 33910037SARM gem5 Developers { 34010037SARM gem5 Developers if (val) 34110037SARM gem5 Developers flags |= AArch64Bit; 34210037SARM gem5 Developers else 34310037SARM gem5 Developers flags &= ~AArch64Bit; 34410037SARM gem5 Developers } 34510037SARM gem5 Developers 34610037SARM gem5 Developers bool 34710037SARM gem5 Developers nextAArch64() const 34810037SARM gem5 Developers { 34910037SARM gem5 Developers return nextFlags & AArch64Bit; 35010037SARM gem5 Developers } 35110037SARM gem5 Developers 35210037SARM gem5 Developers void 35310037SARM gem5 Developers nextAArch64(bool val) 35410037SARM gem5 Developers { 35510037SARM gem5 Developers if (val) 35610037SARM gem5 Developers nextFlags |= AArch64Bit; 35710037SARM gem5 Developers else 35810037SARM gem5 Developers nextFlags &= ~AArch64Bit; 35910037SARM gem5 Developers } 36010037SARM gem5 Developers 36110037SARM gem5 Developers 3627858SMatt.Horsnell@arm.com uint8_t 3638205SAli.Saidi@ARM.com itstate() const 3647858SMatt.Horsnell@arm.com { 3658205SAli.Saidi@ARM.com return _itstate; 3667858SMatt.Horsnell@arm.com } 3677858SMatt.Horsnell@arm.com 3687858SMatt.Horsnell@arm.com void 3698205SAli.Saidi@ARM.com itstate(uint8_t value) 3707858SMatt.Horsnell@arm.com { 3718205SAli.Saidi@ARM.com _itstate = value; 3727858SMatt.Horsnell@arm.com } 3737858SMatt.Horsnell@arm.com 3748205SAli.Saidi@ARM.com uint8_t 3758205SAli.Saidi@ARM.com nextItstate() const 3767858SMatt.Horsnell@arm.com { 3778205SAli.Saidi@ARM.com return _nextItstate; 3788205SAli.Saidi@ARM.com } 3798205SAli.Saidi@ARM.com 3808205SAli.Saidi@ARM.com void 3818205SAli.Saidi@ARM.com nextItstate(uint8_t value) 3828205SAli.Saidi@ARM.com { 3838205SAli.Saidi@ARM.com _nextItstate = value; 3847858SMatt.Horsnell@arm.com } 3857858SMatt.Horsnell@arm.com 3867720Sgblack@eecs.umich.edu void 3877720Sgblack@eecs.umich.edu advance() 3887720Sgblack@eecs.umich.edu { 3897720Sgblack@eecs.umich.edu Base::advance(); 3909074SAli.Saidi@ARM.com flags = nextFlags; 3917720Sgblack@eecs.umich.edu npc(pc() + (thumb() ? 2 : 4)); 3927858SMatt.Horsnell@arm.com 3938205SAli.Saidi@ARM.com if (_nextItstate) { 3948205SAli.Saidi@ARM.com _itstate = _nextItstate; 3958205SAli.Saidi@ARM.com _nextItstate = 0; 3968205SAli.Saidi@ARM.com } else if (_itstate) { 3978205SAli.Saidi@ARM.com ITSTATE it = _itstate; 3988205SAli.Saidi@ARM.com uint8_t cond_mask = it.mask; 3998205SAli.Saidi@ARM.com uint8_t thumb_cond = it.cond; 4009023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE from %#x,%#x.\n", 4018205SAli.Saidi@ARM.com thumb_cond, cond_mask); 4028205SAli.Saidi@ARM.com cond_mask <<= 1; 4038205SAli.Saidi@ARM.com uint8_t new_bit = bits(cond_mask, 4); 4048205SAli.Saidi@ARM.com cond_mask &= mask(4); 4058205SAli.Saidi@ARM.com if (cond_mask == 0) 4068205SAli.Saidi@ARM.com thumb_cond = 0; 4078205SAli.Saidi@ARM.com else 4088205SAli.Saidi@ARM.com replaceBits(thumb_cond, 0, new_bit); 4099023Sgblack@eecs.umich.edu DPRINTF(Decoder, "Advancing ITSTATE to %#x,%#x.\n", 4108205SAli.Saidi@ARM.com thumb_cond, cond_mask); 4118205SAli.Saidi@ARM.com it.mask = cond_mask; 4128205SAli.Saidi@ARM.com it.cond = thumb_cond; 4138205SAli.Saidi@ARM.com _itstate = it; 4147858SMatt.Horsnell@arm.com } 4157720Sgblack@eecs.umich.edu } 4167720Sgblack@eecs.umich.edu 4177720Sgblack@eecs.umich.edu void 4187720Sgblack@eecs.umich.edu uEnd() 4197720Sgblack@eecs.umich.edu { 4207720Sgblack@eecs.umich.edu advance(); 4217720Sgblack@eecs.umich.edu upc(0); 4227720Sgblack@eecs.umich.edu nupc(1); 4237720Sgblack@eecs.umich.edu } 4247720Sgblack@eecs.umich.edu 4257720Sgblack@eecs.umich.edu Addr 4267720Sgblack@eecs.umich.edu instPC() const 4277720Sgblack@eecs.umich.edu { 4287720Sgblack@eecs.umich.edu return pc() + (thumb() ? 4 : 8); 4297720Sgblack@eecs.umich.edu } 4307720Sgblack@eecs.umich.edu 4317720Sgblack@eecs.umich.edu void 43210037SARM gem5 Developers instNPC(Addr val) 4337720Sgblack@eecs.umich.edu { 43410037SARM gem5 Developers // @todo: review this when AArch32/64 interprocessing is 43510037SARM gem5 Developers // supported 43610037SARM gem5 Developers if (aarch64()) 43710037SARM gem5 Developers npc(val); // AArch64 doesn't force PC alignment, a PC 43810037SARM gem5 Developers // Alignment Fault can be raised instead 43910037SARM gem5 Developers else 44010037SARM gem5 Developers npc(val &~ mask(nextThumb() ? 1 : 2)); 4417720Sgblack@eecs.umich.edu } 4427720Sgblack@eecs.umich.edu 4437720Sgblack@eecs.umich.edu Addr 4447720Sgblack@eecs.umich.edu instNPC() const 4457720Sgblack@eecs.umich.edu { 4467720Sgblack@eecs.umich.edu return npc(); 4477720Sgblack@eecs.umich.edu } 4487720Sgblack@eecs.umich.edu 4497720Sgblack@eecs.umich.edu // Perform an interworking branch. 4507720Sgblack@eecs.umich.edu void 45110037SARM gem5 Developers instIWNPC(Addr val) 4527720Sgblack@eecs.umich.edu { 4537720Sgblack@eecs.umich.edu bool thumbEE = (thumb() && jazelle()); 4547720Sgblack@eecs.umich.edu 4557720Sgblack@eecs.umich.edu Addr newPC = val; 4567720Sgblack@eecs.umich.edu if (thumbEE) { 4577720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4587720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4598075SAli.Saidi@ARM.com } // else we have a bad interworking address; do not call 4608075SAli.Saidi@ARM.com // panic() since the instruction could be executed 4618075SAli.Saidi@ARM.com // speculatively 4627720Sgblack@eecs.umich.edu } else { 4637720Sgblack@eecs.umich.edu if (bits(newPC, 0)) { 4647720Sgblack@eecs.umich.edu nextThumb(true); 4657720Sgblack@eecs.umich.edu newPC = newPC & ~mask(1); 4667720Sgblack@eecs.umich.edu } else if (!bits(newPC, 1)) { 4677720Sgblack@eecs.umich.edu nextThumb(false); 4687720Sgblack@eecs.umich.edu } else { 4697744SAli.Saidi@ARM.com // This state is UNPREDICTABLE in the ARM architecture 4707744SAli.Saidi@ARM.com // The easy thing to do is just mask off the bit and 4717744SAli.Saidi@ARM.com // stay in the current mode, so we'll do that. 4727744SAli.Saidi@ARM.com newPC &= ~mask(2); 4737720Sgblack@eecs.umich.edu } 4747720Sgblack@eecs.umich.edu } 4757720Sgblack@eecs.umich.edu npc(newPC); 4767720Sgblack@eecs.umich.edu } 4777720Sgblack@eecs.umich.edu 4787720Sgblack@eecs.umich.edu // Perform an interworking branch in ARM mode, a regular branch 4797720Sgblack@eecs.umich.edu // otherwise. 4807720Sgblack@eecs.umich.edu void 48110037SARM gem5 Developers instAIWNPC(Addr val) 4827720Sgblack@eecs.umich.edu { 4837720Sgblack@eecs.umich.edu if (!thumb() && !jazelle()) 4847720Sgblack@eecs.umich.edu instIWNPC(val); 4857720Sgblack@eecs.umich.edu else 4867720Sgblack@eecs.umich.edu instNPC(val); 4877720Sgblack@eecs.umich.edu } 4887720Sgblack@eecs.umich.edu 4897720Sgblack@eecs.umich.edu bool 4907720Sgblack@eecs.umich.edu operator == (const PCState &opc) const 4917720Sgblack@eecs.umich.edu { 4927720Sgblack@eecs.umich.edu return Base::operator == (opc) && 4938205SAli.Saidi@ARM.com flags == opc.flags && nextFlags == opc.nextFlags && 49412763Sgiacomo.travaglini@arm.com _itstate == opc._itstate && 49512763Sgiacomo.travaglini@arm.com _nextItstate == opc._nextItstate && 49612763Sgiacomo.travaglini@arm.com _illegalExec == opc._illegalExec; 4977720Sgblack@eecs.umich.edu } 4987720Sgblack@eecs.umich.edu 4998361Sksewell@umich.edu bool 5008361Sksewell@umich.edu operator != (const PCState &opc) const 5018361Sksewell@umich.edu { 5028361Sksewell@umich.edu return !(*this == opc); 5038361Sksewell@umich.edu } 5048361Sksewell@umich.edu 5057720Sgblack@eecs.umich.edu void 50611168Sandreas.hansson@arm.com serialize(CheckpointOut &cp) const override 5077720Sgblack@eecs.umich.edu { 50810905Sandreas.sandberg@arm.com Base::serialize(cp); 5097720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(flags); 5108146SAli.Saidi@ARM.com SERIALIZE_SCALAR(_size); 5117720Sgblack@eecs.umich.edu SERIALIZE_SCALAR(nextFlags); 5128205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_itstate); 5138205SAli.Saidi@ARM.com SERIALIZE_SCALAR(_nextItstate); 51412763Sgiacomo.travaglini@arm.com SERIALIZE_SCALAR(_illegalExec); 5157720Sgblack@eecs.umich.edu } 5167720Sgblack@eecs.umich.edu 5177720Sgblack@eecs.umich.edu void 51811168Sandreas.hansson@arm.com unserialize(CheckpointIn &cp) override 5197720Sgblack@eecs.umich.edu { 52010905Sandreas.sandberg@arm.com Base::unserialize(cp); 5217720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(flags); 5228146SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_size); 5237720Sgblack@eecs.umich.edu UNSERIALIZE_SCALAR(nextFlags); 5248205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_itstate); 5258205SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(_nextItstate); 52612763Sgiacomo.travaglini@arm.com UNSERIALIZE_SCALAR(_illegalExec); 5277720Sgblack@eecs.umich.edu } 5287720Sgblack@eecs.umich.edu }; 5297720Sgblack@eecs.umich.edu 5306254Sgblack@eecs.umich.edu // Shift types for ARM instructions 5316254Sgblack@eecs.umich.edu enum ArmShiftType { 5326254Sgblack@eecs.umich.edu LSL = 0, 5336254Sgblack@eecs.umich.edu LSR, 5346254Sgblack@eecs.umich.edu ASR, 5356254Sgblack@eecs.umich.edu ROR 5366254Sgblack@eecs.umich.edu }; 5376254Sgblack@eecs.umich.edu 53810037SARM gem5 Developers // Extension types for ARM instructions 53910037SARM gem5 Developers enum ArmExtendType { 54010037SARM gem5 Developers UXTB = 0, 54110037SARM gem5 Developers UXTH = 1, 54210037SARM gem5 Developers UXTW = 2, 54310037SARM gem5 Developers UXTX = 3, 54410037SARM gem5 Developers SXTB = 4, 54510037SARM gem5 Developers SXTH = 5, 54610037SARM gem5 Developers SXTW = 6, 54710037SARM gem5 Developers SXTX = 7 54810037SARM gem5 Developers }; 54910037SARM gem5 Developers 5506019Shines@cs.fsu.edu typedef int RegContextParam; 5516019Shines@cs.fsu.edu typedef int RegContextVal; 5526019Shines@cs.fsu.edu 5536019Shines@cs.fsu.edu //used in FP convert & round function 5546019Shines@cs.fsu.edu enum ConvertType{ 5556019Shines@cs.fsu.edu SINGLE_TO_DOUBLE, 5566019Shines@cs.fsu.edu SINGLE_TO_WORD, 5576019Shines@cs.fsu.edu SINGLE_TO_LONG, 5586019Shines@cs.fsu.edu 5596019Shines@cs.fsu.edu DOUBLE_TO_SINGLE, 5606019Shines@cs.fsu.edu DOUBLE_TO_WORD, 5616019Shines@cs.fsu.edu DOUBLE_TO_LONG, 5626019Shines@cs.fsu.edu 5636019Shines@cs.fsu.edu LONG_TO_SINGLE, 5646019Shines@cs.fsu.edu LONG_TO_DOUBLE, 5656019Shines@cs.fsu.edu LONG_TO_WORD, 5666019Shines@cs.fsu.edu LONG_TO_PS, 5676019Shines@cs.fsu.edu 5686019Shines@cs.fsu.edu WORD_TO_SINGLE, 5696019Shines@cs.fsu.edu WORD_TO_DOUBLE, 5706019Shines@cs.fsu.edu WORD_TO_LONG, 5716019Shines@cs.fsu.edu WORD_TO_PS, 5726019Shines@cs.fsu.edu 5736019Shines@cs.fsu.edu PL_TO_SINGLE, 5746019Shines@cs.fsu.edu PU_TO_SINGLE 5756019Shines@cs.fsu.edu }; 5766019Shines@cs.fsu.edu 5776019Shines@cs.fsu.edu //used in FP convert & round function 5786019Shines@cs.fsu.edu enum RoundMode{ 5796019Shines@cs.fsu.edu RND_ZERO, 5806019Shines@cs.fsu.edu RND_DOWN, 5816019Shines@cs.fsu.edu RND_UP, 5826019Shines@cs.fsu.edu RND_NEAREST 5836019Shines@cs.fsu.edu }; 5846019Shines@cs.fsu.edu 58510037SARM gem5 Developers enum ExceptionLevel { 58610037SARM gem5 Developers EL0 = 0, 58710037SARM gem5 Developers EL1, 58810037SARM gem5 Developers EL2, 58910037SARM gem5 Developers EL3 59010037SARM gem5 Developers }; 59110037SARM gem5 Developers 5926019Shines@cs.fsu.edu enum OperatingMode { 59310037SARM gem5 Developers MODE_EL0T = 0x0, 59410037SARM gem5 Developers MODE_EL1T = 0x4, 59510037SARM gem5 Developers MODE_EL1H = 0x5, 59610037SARM gem5 Developers MODE_EL2T = 0x8, 59710037SARM gem5 Developers MODE_EL2H = 0x9, 59810037SARM gem5 Developers MODE_EL3T = 0xC, 59910037SARM gem5 Developers MODE_EL3H = 0xD, 6006019Shines@cs.fsu.edu MODE_USER = 16, 6016019Shines@cs.fsu.edu MODE_FIQ = 17, 6026019Shines@cs.fsu.edu MODE_IRQ = 18, 6036019Shines@cs.fsu.edu MODE_SVC = 19, 6046723Sgblack@eecs.umich.edu MODE_MON = 22, 6056019Shines@cs.fsu.edu MODE_ABORT = 23, 60610037SARM gem5 Developers MODE_HYP = 26, 6076019Shines@cs.fsu.edu MODE_UNDEFINED = 27, 6087498Sgblack@eecs.umich.edu MODE_SYSTEM = 31, 6097498Sgblack@eecs.umich.edu MODE_MAXMODE = MODE_SYSTEM 6106019Shines@cs.fsu.edu }; 6116019Shines@cs.fsu.edu 61210037SARM gem5 Developers enum ExceptionClass { 61310037SARM gem5 Developers EC_INVALID = -1, 61410037SARM gem5 Developers EC_UNKNOWN = 0x0, 61510037SARM gem5 Developers EC_TRAPPED_WFI_WFE = 0x1, 61610037SARM gem5 Developers EC_TRAPPED_CP15_MCR_MRC = 0x3, 61710037SARM gem5 Developers EC_TRAPPED_CP15_MCRR_MRRC = 0x4, 61810037SARM gem5 Developers EC_TRAPPED_CP14_MCR_MRC = 0x5, 61910037SARM gem5 Developers EC_TRAPPED_CP14_LDC_STC = 0x6, 62010037SARM gem5 Developers EC_TRAPPED_HCPTR = 0x7, 62110037SARM gem5 Developers EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias 62210037SARM gem5 Developers EC_TRAPPED_CP10_MRC_VMRS = 0x8, 62310037SARM gem5 Developers EC_TRAPPED_BXJ = 0xA, 62410037SARM gem5 Developers EC_TRAPPED_CP14_MCRR_MRRC = 0xC, 62510037SARM gem5 Developers EC_ILLEGAL_INST = 0xE, 62610037SARM gem5 Developers EC_SVC_TO_HYP = 0x11, 62710037SARM gem5 Developers EC_SVC = 0x11, // AArch64 alias 62810037SARM gem5 Developers EC_HVC = 0x12, 62910037SARM gem5 Developers EC_SMC_TO_HYP = 0x13, 63010037SARM gem5 Developers EC_SMC = 0x13, // AArch64 alias 63110037SARM gem5 Developers EC_SVC_64 = 0x15, 63210037SARM gem5 Developers EC_HVC_64 = 0x16, 63310037SARM gem5 Developers EC_SMC_64 = 0x17, 63410037SARM gem5 Developers EC_TRAPPED_MSR_MRS_64 = 0x18, 63513759Sgiacomo.gabrielli@arm.com EC_TRAPPED_SVE = 0x19, 63610037SARM gem5 Developers EC_PREFETCH_ABORT_TO_HYP = 0x20, 63710037SARM gem5 Developers EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias 63810037SARM gem5 Developers EC_PREFETCH_ABORT_FROM_HYP = 0x21, 63910037SARM gem5 Developers EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias 64010037SARM gem5 Developers EC_PC_ALIGNMENT = 0x22, 64110037SARM gem5 Developers EC_DATA_ABORT_TO_HYP = 0x24, 64210037SARM gem5 Developers EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias 64310037SARM gem5 Developers EC_DATA_ABORT_FROM_HYP = 0x25, 64410037SARM gem5 Developers EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias 64510037SARM gem5 Developers EC_STACK_PTR_ALIGNMENT = 0x26, 64610037SARM gem5 Developers EC_FP_EXCEPTION = 0x28, 64710037SARM gem5 Developers EC_FP_EXCEPTION_64 = 0x2C, 64812299Sandreas.sandberg@arm.com EC_SERROR = 0x2F, 64912299Sandreas.sandberg@arm.com EC_SOFTWARE_BREAKPOINT = 0x38, 65012732Sandreas.sandberg@arm.com EC_SOFTWARE_BREAKPOINT_64 = 0x3C, 65110037SARM gem5 Developers }; 65210037SARM gem5 Developers 65310611SAndreas.Sandberg@ARM.com /** 65410611SAndreas.Sandberg@ARM.com * Instruction decoder fault codes in ExtMachInst. 65510611SAndreas.Sandberg@ARM.com */ 65610611SAndreas.Sandberg@ARM.com enum DecoderFault : std::uint8_t { 65710611SAndreas.Sandberg@ARM.com OK = 0x0, ///< No fault 65810611SAndreas.Sandberg@ARM.com UNALIGNED = 0x1, ///< Unaligned instruction fault 65910611SAndreas.Sandberg@ARM.com 66010611SAndreas.Sandberg@ARM.com PANIC = 0x3, ///< Internal gem5 error 66110611SAndreas.Sandberg@ARM.com }; 66210611SAndreas.Sandberg@ARM.com 66310037SARM gem5 Developers BitUnion8(OperatingMode64) 66410037SARM gem5 Developers Bitfield<0> spX; 66510037SARM gem5 Developers Bitfield<3, 2> el; 66610037SARM gem5 Developers Bitfield<4> width; 66710037SARM gem5 Developers EndBitUnion(OperatingMode64) 66810037SARM gem5 Developers 66910037SARM gem5 Developers static bool inline 67010037SARM gem5 Developers opModeIs64(OperatingMode mode) 67110037SARM gem5 Developers { 67210037SARM gem5 Developers return ((OperatingMode64)(uint8_t)mode).width == 0; 67310037SARM gem5 Developers } 67410037SARM gem5 Developers 67510037SARM gem5 Developers static bool inline 67610037SARM gem5 Developers opModeIsH(OperatingMode mode) 67710037SARM gem5 Developers { 67810037SARM gem5 Developers return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H); 67910037SARM gem5 Developers } 68010037SARM gem5 Developers 68110037SARM gem5 Developers static bool inline 68210037SARM gem5 Developers opModeIsT(OperatingMode mode) 68310037SARM gem5 Developers { 68410037SARM gem5 Developers return (mode == MODE_EL0T || mode == MODE_EL1T || mode == MODE_EL2T || 68510037SARM gem5 Developers mode == MODE_EL3T); 68610037SARM gem5 Developers } 68710037SARM gem5 Developers 68810037SARM gem5 Developers static ExceptionLevel inline 68910037SARM gem5 Developers opModeToEL(OperatingMode mode) 69010037SARM gem5 Developers { 69110037SARM gem5 Developers bool aarch32 = ((mode >> 4) & 1) ? true : false; 69210037SARM gem5 Developers if (aarch32) { 69310037SARM gem5 Developers switch (mode) { 69410037SARM gem5 Developers case MODE_USER: 69510037SARM gem5 Developers return EL0; 69610037SARM gem5 Developers case MODE_FIQ: 69710037SARM gem5 Developers case MODE_IRQ: 69810037SARM gem5 Developers case MODE_SVC: 69910037SARM gem5 Developers case MODE_ABORT: 70010037SARM gem5 Developers case MODE_UNDEFINED: 70110037SARM gem5 Developers case MODE_SYSTEM: 70210037SARM gem5 Developers return EL1; 70310037SARM gem5 Developers case MODE_HYP: 70410037SARM gem5 Developers return EL2; 70510037SARM gem5 Developers case MODE_MON: 70610037SARM gem5 Developers return EL3; 70710037SARM gem5 Developers default: 70810037SARM gem5 Developers panic("Invalid operating mode: %d", mode); 70910037SARM gem5 Developers break; 71010037SARM gem5 Developers } 71110037SARM gem5 Developers } else { 71210037SARM gem5 Developers // aarch64 71310037SARM gem5 Developers return (ExceptionLevel) ((mode >> 2) & 3); 71410037SARM gem5 Developers } 71510037SARM gem5 Developers } 71610037SARM gem5 Developers 7177311Sgblack@eecs.umich.edu static inline bool 71812788Sgiacomo.travaglini@arm.com unknownMode(OperatingMode mode) 7197311Sgblack@eecs.umich.edu { 7207311Sgblack@eecs.umich.edu switch (mode) { 72110037SARM gem5 Developers case MODE_EL0T: 72210037SARM gem5 Developers case MODE_EL1T: 72310037SARM gem5 Developers case MODE_EL1H: 72410037SARM gem5 Developers case MODE_EL2T: 72510037SARM gem5 Developers case MODE_EL2H: 72610037SARM gem5 Developers case MODE_EL3T: 72710037SARM gem5 Developers case MODE_EL3H: 72810037SARM gem5 Developers case MODE_USER: 72910037SARM gem5 Developers case MODE_FIQ: 73010037SARM gem5 Developers case MODE_IRQ: 73110037SARM gem5 Developers case MODE_SVC: 73210037SARM gem5 Developers case MODE_MON: 73310037SARM gem5 Developers case MODE_ABORT: 73410037SARM gem5 Developers case MODE_HYP: 73510037SARM gem5 Developers case MODE_UNDEFINED: 73610037SARM gem5 Developers case MODE_SYSTEM: 73710037SARM gem5 Developers return false; 73810037SARM gem5 Developers default: 73910037SARM gem5 Developers return true; 74010037SARM gem5 Developers } 74110037SARM gem5 Developers } 74210037SARM gem5 Developers 74310037SARM gem5 Developers static inline bool 74412788Sgiacomo.travaglini@arm.com unknownMode32(OperatingMode mode) 74510037SARM gem5 Developers { 74610037SARM gem5 Developers switch (mode) { 7477311Sgblack@eecs.umich.edu case MODE_USER: 7487311Sgblack@eecs.umich.edu case MODE_FIQ: 7497311Sgblack@eecs.umich.edu case MODE_IRQ: 7507311Sgblack@eecs.umich.edu case MODE_SVC: 7517311Sgblack@eecs.umich.edu case MODE_MON: 7527311Sgblack@eecs.umich.edu case MODE_ABORT: 75310037SARM gem5 Developers case MODE_HYP: 7547311Sgblack@eecs.umich.edu case MODE_UNDEFINED: 7557311Sgblack@eecs.umich.edu case MODE_SYSTEM: 7567311Sgblack@eecs.umich.edu return false; 7577311Sgblack@eecs.umich.edu default: 7587311Sgblack@eecs.umich.edu return true; 7597311Sgblack@eecs.umich.edu } 7607311Sgblack@eecs.umich.edu } 7617311Sgblack@eecs.umich.edu 76213759Sgiacomo.gabrielli@arm.com constexpr unsigned MaxSveVecLenInBits = 2048; 76313759Sgiacomo.gabrielli@arm.com static_assert(MaxSveVecLenInBits >= 128 && 76413759Sgiacomo.gabrielli@arm.com MaxSveVecLenInBits <= 2048 && 76513759Sgiacomo.gabrielli@arm.com MaxSveVecLenInBits % 128 == 0, 76613759Sgiacomo.gabrielli@arm.com "Unsupported max. SVE vector length"); 76713759Sgiacomo.gabrielli@arm.com constexpr unsigned MaxSveVecLenInBytes = MaxSveVecLenInBits >> 3; 76813759Sgiacomo.gabrielli@arm.com constexpr unsigned MaxSveVecLenInWords = MaxSveVecLenInBits >> 5; 76913759Sgiacomo.gabrielli@arm.com constexpr unsigned MaxSveVecLenInDWords = MaxSveVecLenInBits >> 6; 77013759Sgiacomo.gabrielli@arm.com 77113759Sgiacomo.gabrielli@arm.com constexpr unsigned VecRegSizeBytes = MaxSveVecLenInBytes; 77213759Sgiacomo.gabrielli@arm.com constexpr unsigned VecPredRegSizeBits = MaxSveVecLenInBytes; 77313759Sgiacomo.gabrielli@arm.com constexpr unsigned VecPredRegHasPackedRepr = false; 7746019Shines@cs.fsu.edu} // namespace ArmISA 7756019Shines@cs.fsu.edu 7766019Shines@cs.fsu.edu#endif 777