dev/arm/gic_v3_cpu_interface.cc

134         // only implemented if supporting 6 or more bits of priority
138         // only implemented if supporting 7 or more bits of priority
141         // only implemented if supporting 7 or more bits of priority
157         // only implemented if supporting 6 or more bits of priority
161         // only implemented if supporting 7 or more bits of priority
164         // only implemented if supporting 7 or more bits of priority
564           // Enforce value for RO bits
570           // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
571           // PRIbits [10:8], number of priority bits implemented, minus one
598           // Enforce value for RO bits
605           // IDbits [13:11], 001 = 24 bits | 000 = 16 bits
606           // PRIbits [10:8], number of priority bits implemented, minus one
629       // only implemented if supporting 6 or more bits of priority
632       // only implemented if supporting 7 or more bits of priority
635       // only implemented if supporting 7 or more bits of priority
646       // only implemented if supporting 6 or more bits of priority
649       // only implemented if supporting 7 or more bits of priority
652       // only implemented if supporting 7 or more bits of priority
756         // only implemented if supporting 6 or more bits of priority
760         // only implemented if supporting 7 or more bits of priority
763         // only implemented if supporting 7 or more bits of priority
778         // only implemented if supporting 6 or more bits of priority
782         // only implemented if supporting 7 or more bits of priority
785         // only implemented if supporting 7 or more bits of priority
1415         // All bits are RAO/WI
1461         // Priority, bits [23:16]
1462         // At least five bits must be implemented.
1463         // Unimplemented bits are RES0 and start from bit[16] up to bit[18].
1464         // We implement 5 bits.
1468         // pINTID, bits [12:0]
1474         // - This field is only required to implement enough bits to hold a
1476         // order bits are RES0.
1506           // Priority, bits [55:48]
1507           // At least five bits must be implemented.
1508           // Unimplemented bits are RES0 and start from bit[48] up to bit[50].
1509           // We implement 5 bits.
1513           // pINTID, bits [44:32]
1519           // - This field is only required to implement enough bits to hold a
1521           // order bits are RES0.
1528           // vINTID, bits [31:0]
1529           // It is IMPLEMENTATION DEFINED how many bits are implemented,
1530           // though at least 16 bits must be implemented.
1531           // Unimplemented bits are RES0.
1575       // only implemented if supporting 6 or more bits of priority
1578       // only implemented if supporting 7 or more bits of priority
1581       // only implemented if supporting 7 or more bits of priority
1592       // only implemented if supporting 6 or more bits of priority
1595       // only implemented if supporting 7 or more bits of priority
1598       // only implemented if supporting 7 or more bits of priority
1770     uint8_t aff3 = bits(val, 55, 48);
1771     uint8_t aff2 = bits(val, 39, 32);
1772     uint8_t aff1 = bits(val, 23, 16);;
1773     uint16_t target_list = bits(val, 15, 0);
1774     uint32_t int_id = bits(val, 27, 24);
1775     bool irm = bits(val, 40, 40);
1776     uint8_t rs = bits(val, 47, 44);
1799             uint8_t aff0_i = bits(affinity_i, 7, 0);
2163         bits(isa->readMiscRegNoEffect(MISCREG_ICH_VMCR_EL2), 31, 24);
2212     uint32_t EOI_cout = bits(ich_hcr_el2, 31, 27);
2467     // interrupt, that is, if the corresponding ICH_LR<n>_EL2.State bits