/gem5/src/arch/arm/ |
H A D | decoder.cc | 87 emi.sevenAndFour = bits(data, 7) && bits(data, 4); 88 emi.isMisc = (bits(data, 24, 23) == 0x2 && 89 bits(data, 20) == 0); 132 if (bits(word, 15, 8) == 0xbf && 133 bits(word, 3, 0) != 0x0) { 135 itBits = bits(word, 7, 0);
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H A D | utility.cc | 94 // If the argument is 64 bits, it must be in an even regiser 391 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 393 else if (!bits(addr, 55, 48) && tcr.tbi0) 394 return bits(addr,55, 0); 424 if (bits(addr, 55, 48) == 0xFF && tcr.tbi1) 426 else if (!bits(addr, 55, 48) && tcr.tbi0) 427 return bits(addr,55, 0); 746 int sysM4To3 = bits(sysM, 4, 3); 750 regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8); 753 regIdx = intRegInMode(mode, bits(sys [all...] |
H A D | isa.cc | 440 DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 444 DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 700 // Set the bits for unimplemented coprocessors to RAO/WI 728 return 0; // bits [63:0] RES0 (reserved for future use) 763 miscRegs[lower] = bits(v, 31, 0); 764 miscRegs[upper] = bits(v, 63, 32); 1161 bits(newVal, 7,0)); 1176 bits(newVal, 7,0)); 1189 bits(newVal, 7,0)); 1202 bits(newVa [all...] |
/gem5/ext/fputils/ |
H A D | fpbits.h | 67 { .bits = BUILD_IFP64(sign, frac, exp) } 107 (fp64.bits & FP64_FRAC_MASK) 110 ((fp64.bits & FP64_EXP_MASK) >> FP64_EXP_SHIFT)
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/gem5/src/base/ |
H A D | sat_counter.hh | 66 * of bits. 68 * @param bits How many bits the counter will have. 71 explicit SatCounter(unsigned bits, uint8_t initial_val = 0) argument 72 : initialVal(initial_val), maxVal((1 << bits) - 1), 75 fatal_if(bits > 8*sizeof(uint8_t), 76 "Number of bits exceeds counter size");
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H A D | condcodes.hh | 82 return bits(dest, width - 1, width - 1);
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H A D | addr_range.test.cc | 147 return bits(addr, xorBits1[1], xorBits0[1]) ^ 148 bits(addr, xorBits1[0], xorBits0[0]); 204 return (bits(addr, xorBits0[0]) ^ bits(addr, xorBits0[1])) | 205 (bits(addr, xorBits1[0]) ^ bits(addr, xorBits1[1])) << 1;
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/gem5/src/base/filters/ |
H A D | h3_bloom_filter.cc | 378 bits(addr, std::numeric_limits<Addr>::digits - 1, offsetBits);
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/gem5/src/dev/net/ |
H A D | i8254xGBe_defs.hh | 237 inline bool isLegacy(TxDesc *d) { return !bits(d->d2,29,29); } 238 inline uint8_t getType(TxDesc *d) { return bits(d->d2, 23,20); } 246 inline Addr getLen(TxDesc *d) { if (isLegacy(d)) return bits(d->d2,15,0); else return bits(d->d2, 19,0); } 249 inline bool ide(TxDesc *d) { return bits(d->d2, 31,31) && (getType(d) == TXD_DATA || isLegacy(d)); } 250 inline bool vle(TxDesc *d) { assert(isLegacy(d) || isData(d)); return bits(d->d2, 30,30); } 251 inline bool rs(TxDesc *d) { return bits(d->d2, 27,27); } 252 inline bool ic(TxDesc *d) { assert(isLegacy(d) || isData(d)); return isLegacy(d) && bits(d->d2, 26,26); } 255 return bits(d->d2, 26,26); 257 return bits( [all...] |
/gem5/src/arch/sparc/ |
H A D | tlb.cc | 221 // Mark the entries used bit and clear other used bits in needed 226 // Update the used bits only if this is a real access (not a fake 445 bool hpriv = bits(tlbdata,0,0); 446 bool red = bits(tlbdata,1,1); 447 bool priv = bits(tlbdata,2,2); 448 bool addr_mask = bits(tlbdata,3,3); 449 bool lsu_im = bits(tlbdata,4,4); 451 int part_id = bits(tlbdata,15,8); 452 int tl = bits(tlbdata,18,16); 453 int pri_context = bits(tlbdat [all...] |
H A D | decoder.hh | 77 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
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/gem5/src/dev/x86/ |
H A D | i8237.cc | 104 uint8_t select = bits(command, 1, 0); 105 uint8_t bitVal = bits(command, 2); 121 panic("Write to i8237 write all mask register bits unimplemented.\n");
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/gem5/src/arch/arm/insts/ |
H A D | vfp.cc | 45 * exception bits read before it, etc. 333 uint32_t op1Bits = bits(valBits, 50, 29) | 335 (bits(valBits, 63) << 31); 369 uint64_t op1Bits = ((uint64_t)bits(valBits, 21, 0) << 29) | 371 ((uint64_t)bits(valBits, 31) << 63); 414 bool neg = bits(opBits, sBitPos); 415 uint32_t exponent = bits(opBits, sBitPos-1, mWidth); 416 uint64_t oldMantissa = bits(opBits, mWidth-1, 0); 423 if (bits(mantissa, 9) == 0) { 471 (extra == (1 << 9) && bits(mantiss [all...] |
H A D | static_inst.hh | 85 if (bits(midRes, width) != bits(midRes, width - 1)) { 151 if (bits(machInst, 28, 24) == 0x10) 154 intWidth = (aarch64 && bits(machInst, 31)) ? 64 : 32; 213 if (bits(byteMask, 3)) { 217 if (bits(byteMask, 2)) { 220 if (bits(byteMask, 1)) { 226 if (bits(byteMask, 0)) { 286 if (bits(byteMask, 3)) 288 if (bits(byteMas [all...] |
/gem5/src/arch/riscv/ |
H A D | faults.cc | 66 bits(tc->readMiscReg(MISCREG_MIDELEG), _code) != 0) { 70 bits(tc->readMiscReg(MISCREG_SIDELEG), _code) != 0) { 75 bits(tc->readMiscReg(MISCREG_MEDELEG), _code) != 0) { 79 bits(tc->readMiscReg(MISCREG_SEDELEG), _code) != 0) { 131 if (isInterrupt() && bits(tc->readMiscReg(tvec), 1, 0) == 1)
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/gem5/src/dev/ps2/ |
H A D | keyboard.cc | 117 bits(data[1], 2) ? "on" : "off", 118 bits(data[1], 1) ? "on" : "off", 119 bits(data[1], 0) ? "on" : "off");
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/gem5/src/arch/sparc/insts/ |
H A D | blockmem.hh | 81 imm(sext<13>(bits(_machInst, 12, 0)))
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H A D | priv.hh | 92 Priv(mnem, _machInst, __opClass), imm(bits(_machInst, 12, 0))
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/gem5/src/dev/sparc/ |
H A D | iob.cc | 196 intMan[index].cpu = bits(data,12,8); 197 intMan[index].vector = bits(data,5,0); 206 intCtl[index].mask = bits(data,2,2); 207 if (bits(data,1,1)) 210 intCtl[index].pend, bits(data,2,2)); 215 jIntVec = bits(pkt->getBE<uint64_t>(), 5,0); 226 type = (Type)bits(data,17,16); 227 cpu_id = bits(data, 12,8); 228 vector = bits(data,5,0); 247 jIntBusy[index].busy = bits(dat [all...] |
/gem5/src/dev/pci/ |
H A D | host.cc | 193 PciBusAddr(bits(bus_addr, 15, 8), 194 bits(bus_addr, 7, 3), 195 bits(bus_addr, 2, 0)),
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H A D | copy_engine_defs.hh | 80 inline uint8_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 84 inline uint16_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 88 inline uint32_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \ 92 inline uint64_t NAME() { return bits(_data, OFFSET+BITS-1, OFFSET); } \
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/gem5/src/dev/arm/ |
H A D | gpu_nomali.cc | 344 { GPU_CONTROL_REG(SHADER_PRESENT_LO), bits(p->shader_present, 31, 0) }, 345 { GPU_CONTROL_REG(SHADER_PRESENT_HI), bits(p->shader_present, 63, 32) }, 346 { GPU_CONTROL_REG(TILER_PRESENT_LO), bits(p->tiler_present, 31, 0) }, 347 { GPU_CONTROL_REG(TILER_PRESENT_HI), bits(p->tiler_present, 63, 32) }, 348 { GPU_CONTROL_REG(L2_PRESENT_LO), bits(p->l2_present, 31, 0) }, 349 { GPU_CONTROL_REG(L2_PRESENT_HI), bits(p->l2_present, 63, 32) },
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/gem5/src/mem/cache/prefetch/ |
H A D | signature_path.hh | 62 /** Number of bits to shift when generating a new signature */ 64 /** Size of the signature, in bits */ 91 PatternStrideEntry(unsigned bits) : stride(0), counter(bits) argument
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/gem5/src/arch/x86/ |
H A D | cpuid.cc | 92 uint16_t family = bits(function, 31, 16); 93 uint16_t funcNum = bits(function, 15, 0);
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/gem5/src/arch/x86/regs/ |
H A D | misc.hh | 542 * A type to describe the condition code bits of the RFLAGS register, 724 return bits(__data, index + 2); 741 return bits(__data, index * 8 + 7, index * 8); 748 return bits(__data, index * 8 + 2, index * 8); 777 return bits(__data, index); 877 return (bits(storage, 63, 56) << 24) | bits(storage, 39, 16); 883 replaceBits(storage, 63, 56, bits(base, 31, 24)); 884 replaceBits(storage, 39, 16, bits(base, 23, 0)); 894 uint32_t limit = (bits(storag [all...] |