1/*
2 * Copyright (c) 2006-2007 The Regents of The University of Michigan
3 * All rights reserved
4 * Copyright 2017 Google Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Ali Saidi
30 *          Gabe Black
31 *          Steve Reinhardt
32 */
33
34#ifndef __ARCH_SPARC_INSTS_PRIV_HH__
35#define __ARCH_SPARC_INSTS_PRIV_HH__
36
37#include "arch/sparc/insts/static_inst.hh"
38
39namespace SparcISA
40{
41
42/**
43 * Base class for privelege mode operations.
44 */
45class Priv : public SparcStaticInst
46{
47  protected:
48    using SparcStaticInst::SparcStaticInst;
49    std::string generateDisassembly(
50            Addr pc, const SymbolTable *symtab) const override;
51};
52
53class PrivReg : public Priv
54{
55  protected:
56    PrivReg(const char *mnem, ExtMachInst _machInst,
57            OpClass __opClass, char const * _regName) :
58        Priv(mnem, _machInst, __opClass), regName(_regName)
59    {}
60
61    char const *regName;
62};
63
64// This class is for instructions that explicitly read control
65// registers. It provides a special generateDisassembly function.
66class RdPriv : public PrivReg
67{
68  protected:
69    using PrivReg::PrivReg;
70    std::string generateDisassembly(
71            Addr pc, const SymbolTable *symtab) const override;
72};
73
74// This class is for instructions that explicitly write control
75// registers. It provides a special generateDisassembly function.
76class WrPriv : public PrivReg
77{
78  protected:
79    using PrivReg::PrivReg;
80    std::string generateDisassembly(
81            Addr pc, const SymbolTable *symtab) const override;
82};
83
84/**
85 * Base class for privelege mode operations with immediates.
86 */
87class PrivImm : public Priv
88{
89  protected:
90    // Constructor
91    PrivImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
92        Priv(mnem, _machInst, __opClass), imm(bits(_machInst, 12, 0))
93    {}
94
95    int32_t imm;
96};
97
98// This class is for instructions that explicitly write control
99// registers. It provides a special generateDisassembly function.
100class WrPrivImm : public PrivImm
101{
102  protected:
103    // Constructor
104    WrPrivImm(const char *mnem, ExtMachInst _machInst,
105              OpClass __opClass, char const *_regName) :
106        PrivImm(mnem, _machInst, __opClass), regName(_regName)
107    {}
108
109    std::string generateDisassembly(
110            Addr pc, const SymbolTable *symtab) const override;
111
112    char const *regName;
113};
114
115}
116
117#endif //__ARCH_SPARC_INSTS_PRIV_HH__
118