/gem5/src/mem/probes/ |
H A D | MemTraceProbe.py | 55 # System object to look up the name associated with a master ID 56 system = Param.System(Parent.any, "System the probe belongs to")
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H A D | StackDistProbe.py | 47 system = Param.System(Parent.any, 48 "System to use when determining system cache "
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/gem5/src/mem/ |
H A D | ExternalMaster.py | 56 system = Param.System(Parent.any, 'System this external port belongs to')
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H A D | XBar.py | 42 from m5.objects.System import System 120 system = Param.System(Parent.any, "System that the crossbar belongs to.") 130 system = Param.System(Parent.any, "System that the crossbar belongs to.")
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H A D | CommMonitor.py | 41 from m5.objects.System import System 50 system = Param.System(Parent.any, "System that the monitor belongs to.")
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H A D | abstract_mem.hh | 59 class System; 185 /** Pointor to the System object. 189 System *_system; 242 System* system() const { return _system; } 250 void system(System *sys) { _system = sys; }
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/gem5/src/learning_gem5/part2/ |
H A D | SimpleCache.py | 47 system = Param.System(Parent.any, "The system this cache is part of")
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/gem5/src/base/ |
H A D | cp_annotate.hh | 66 class System; 104 void hwBegin(flags f, System *sys, uint64_t frame, std::string sm, 106 void hwQ(flags f, System *sys, uint64_t frame, std::string sm, 107 std::string q, uint64_t qid, System *q_sys = NULL, 109 void hwDq(flags f, System *sys, uint64_t frame, std::string sm, 110 std::string q, uint64_t qid, System *q_sys = NULL, 112 void hwPq(flags f, System *sys, uint64_t frame, std::string sm, 113 std::string q, uint64_t qid, System *q_sys = NULL, 115 void hwRq(flags f, System *sys, uint64_t frame, std::string sm, 116 std::string q, uint64_t qid, System *q_sy [all...] |
/gem5/src/dev/mips/ |
H A D | malta.hh | 47 class System; 63 System *system;
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/gem5/src/sim/ |
H A D | debug.cc | 102 System* curSystem = System::systemList[0];
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/gem5/src/arch/mips/ |
H A D | remote_gdb.hh | 41 class System; 83 RemoteGDB(System *_system, ThreadContext *tc, int _port);
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H A D | system.hh | 48 class MipsSystem : public System
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/gem5/src/systemc/tlm_bridge/ |
H A D | TlmBridge.py | 40 system = Param.System(Parent.any, "system") 52 system = Param.System(Parent.any, "system")
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/gem5/src/arch/x86/ |
H A D | X86TLB.py | 49 system = Param.System(Parent.any, "system object")
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/gem5/src/cpu/testers/rubytest/ |
H A D | RubyTester.py | 44 system = Param.System(Parent.any, "System we belong to")
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/gem5/src/arch/sparc/ |
H A D | SparcSystem.py | 32 from m5.objects.System import System 34 class SparcSystem(System):
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/gem5/src/arch/arm/ |
H A D | ArmTLB.py | 61 sys = Param.System(Parent.any, "system object parameter") 67 sys = Param.System(Parent.any, "system object parameter") 88 sys = Param.System(Parent.any, "system object parameter")
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/gem5/tests/configs/ |
H A D | o3-timing-ruby.py | 37 system = System(cpu = cpu,
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/gem5/src/cpu/ |
H A D | pc_event.cc | 148 sched_break_pc_sys(System *sys, Addr addr) 156 for (vector<System *>::iterator sysi = System::systemList.begin(); 157 sysi != System::systemList.end(); ++sysi) {
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/gem5/src/arch/riscv/ |
H A D | system.hh | 49 class RiscvSystem : public System
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/gem5/src/dev/virtio/ |
H A D | VirtIO.py | 54 system = Param.System(Parent.any, "system object")
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/gem5/src/cpu/testers/memtest/ |
H A D | MemTest.py | 70 system = Param.System(Parent.any, "System this tester is part of")
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/gem5/src/mem/ruby/slicc_interface/ |
H A D | Controller.py | 73 system = Param.System(Parent.any, "system object parameter")
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/gem5/ext/mcpat/ |
H A D | main.cc | 85 assert(strcmp(system_xml.getAttribute("type"), "System") == 0); 88 System* system = new System(&system_xml);
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H A D | system.cc | 51 System::System(XMLNode* _xml_data) function in class:System 56 name = "System"; 112 void System::displayDeviceType(int device_type_, uint32_t indent) { 138 void System::displayInterconnectType(int interconnect_type_, uint32_t indent) { 156 void System::displayData(uint32_t indent, int plevel) { 186 void System::set_proc_param() { 348 System::~System() {
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